Polysilicon Emitter High Performance BiCMOS Structures: The 23 masking step BiCMOS structure that is suitable for both

h 3.3 and 5V applications. The structure was built upon a two poly, two metal twin well 0.6m baseline CMOS process. Buried n+ and p+ layers were used in the CMOS section to increase latchup immunity, polycide (silicided-polysilicon ) MOS gate and polysilicon emitter bipolar were employed. The isolation approach is LOCOS. Fig Key process steps: The starting material is a p-substrate with resistivity of 16 to 24 Ohm-cm. The buried layers are of antimony and boron types. The epitaxial layer is n-type, with resistivity of 0.6 Ohm-cm and is 1.4m thick. Gate oxide thickness is 125 A, and polycide is employed for both the poly silicon gate and emitter structures. Figure (a) presents the crosssectional schematic and layout diagram of the polysilicon emitter bipolar structure. Fig It was reported then that the current gain of transistor fabricated with such polysilicon emitters is three to seven times greater than that of transistors with conventional emitters. The polysilicon emitter allows holes to diffuse directly into the polysilicon contact, thereby preventing recombination at the contact. The current gain can, therefore, be high even for a shallow emitter. The polys/Si interface with barrier oxide serves 1

as recombination traps. The hole diffusion mechanisms in the polysilicon controls the base current for the shallow emitter. The emitter drive in step is carried out by means of rapid thermal processing at 1050c. This procedure determines the final emitter / base junction, base width, and the nature of the Poly/Si interface. The step-by-step process flow for the The complete

polysilicon emitter formation is illustrated in Figure (b).

BiCMOS process flow, consisting of 23 masking steps, is presented in Figure (c) for comparison, cross-sectional nMOS SEMs are also depicted in Figure (d). Fig (a) Starting substrate is p-type <100>, with resistivity of 16-24 Ohm-cm. Initial oxidation forms tox=4500A. upon formation of buried n=mask, oxide etch (plasma + buffered oxide etch [BOE] is carried out followed by chemical resist strip. After pad oxidation (85A), buried n+ implant is performed (Antimony with implant dose of 1.60E 15 Atm/Cm2, using important energy of 70kev at 0 implant angle). Fig (b) After an oxide dip (tox loss 30A), buried n+ drive-in is carried out at 1150C (tox=1300A), Ps40/Sq.xj 1.8m). Burried P+ mask is then used, followed by oxide plasma etch (tox after = 900A). the buried p+-implant dose is 0.3OE14 cm-2 (50 ke, V.7 implant angle), and dose is 0.30E14 cm-2 (50 ke, V.7 implant angle), and after chemical resist strip cum oxide tip (tox loss 30A), the buried P+

drive-in is performed at 1000c using N2. The process is completed by and epitaxial pre-clean step. Fig (c) n-epitaxial layer is deposited, with p=0.6cm, t=1.4m, and up diffusion 0.4m. Pad oxidation produces a 300-A layer. An n-well mask (NW) is used next and the n-well implantation is developed using phosphorous, at 0.66E13cm-2, 150 kev, and at 7 tilt. Upon chemical resist strip, p-field mask (for P-well) followed by P-well implant of boron (of 0.2E13 cm-2, 50kev, and at 7 tilt) is carried out. After chemical resist strip / oxide strip well drive-in is done at 1150c at tox 150 A and xj = 1.5 m. Fig (d) The steps involved are: Oxide dip (tox loss 300A), pad 2 oxidation (200A), nitride deposition (1525A), composite mask nitride plasma etch, n-field implant using phosphorus (at 0.20E13 cm-2, 190 kev, 7), plasma chemical resist strip, P-field mask (for P-field), P-field implant (BF2 at 0.60E14 cm-2, 80 kev, 7), chemical resist strip, and field oxidation at 100c, yielding a tox of 5500A. Fig (e) The steps used here are oxide dip/nitride strip, sinker/deep collector mask, striker implant to give Ps 80/Sq, chemical resist strip, oxide dip with tox loss 300A, and sinker drive-in at 1000c giving Ps 60 /Sq. (using tox = 300A, width nj = 1.2m). 3

Fig (f) The processing sequence here involves: Polu-1 deposition (2300 A), high sheet-rho implant, TEOs deposition (2000A), TEOs densification, resistor mask, TEOs etch, plasma chemical resist strip, and poly-1 doping at 900c for 37 minutes) Fig (g) The steps used here are: TEOs strip, poly-1 mask (for forming resistor/capacitor), poly-1 etch, plasma chemical resist strip, and poly-1 oxidation (65A). Fig (h) The CMOS masking (expose CMOS), oxide removal (CMOS active area), chemical resist strip, gate oxidation (tox amorphous split poly deposition, with tox = 600A. Fig (i) Vt block mask and Vt implant of boron (at 0.19 E13 cm-2, 30 kev, and at 7) are performed here. Fig (j) Upon stripping the resist, base masking and base implant are carried out. The boron implant dosages for 3.3 and 5.0-v
=

125A), and

applications are 0.17 E14 and 0.21E14 cm-2, respectively. Fig (k) Emitter mask, poly/oxide etch, and resist strip are performed. Fig 4

(l) Light oxidation producing tox = 80A is first performed after oxide dip (tox loss=300A), poly -2 decomposition gives tpoly = 1700A. Emitter implant (1.2E16 cm-2 at 50 kev, 0) is then carried out. After back etch, emitter drive using RTA at 1010c for 30 minutes is performed. A 1500-A thick WSIx layer is next deposited. After poly deposition (500A), poly -2 mask, poly -2 etch, and plasma chemical resist strip are simultaneously done. Fig (m) The steps involved: TEOs thin spaces deposition (400A)m nDD mask (expose n MOS), nLDD implant (phosphorus 0.40E14 cm-2, at 60 kev 0). Chemical resist strip, spacer TEOs deposition (2000A), spaces etch, spacer oxidation (900c), n+ S/D implant, and finally, chemical resist strip. Fig (n) Last, these steps are carried ut: P+ - implant masking, hard bake, p+ implant, chemical resist strip, low-temperature oxide (LTO) depositon (1000A), boron-phosphate TEOs (BPTEOs) deposition (10,000A), BPTEOs densification, BPTEOs etch-back, sulfuric clean, contact mask, contact etch, chemical resist strip, and the final 0.6-m double metal interconnect process. Electrical performance: As mentioned earlier, the discussed polysilicon emitter bipolar structures are for 3.3 and 5.0 v applications. Tables a and b present the electrical parameters for the device when operated at the

two supply voltages. provided in Table c.

The CMOS electrical parameters are separately

The results show that the polysilicon emitter nPn bipolar transistors are able to achieve fTs of 13 to 19 GHz and also high current gains as compared to those with direct metal contacts to the emitter. It should be pointed out that the development of polysilicon emitters has also been pursued for other important reasons. Table a: Electrical parameters of the polysilicon emitter nPn Bipolar structure when operated at 5.0 -V. 5.0 V Process (0.6 x 2.4 mm2 emitter) Parameter FT (GHz) FMAX(GHz) HFE VA (v) BVCEO (v) BVCBO (v) BVEEO (v) Double base. Table b: Electrical parameters of the polysilicon emitter nPn Bipolar structure when operated at 3.3V 3.3 V Process (0.6 x 2.4 mm2 emitter) Parameter FT (GHz) FMAX(GHz) Min 15 16 Typical 17 19 Max 19 22 6 Min 13 14 50 12 5.3 12 5.5 Typical 15 17 95 20 6.5 16 6.3 Max 17 20 140 30 10 20 7.1

HFF VA (v) BVCEO (v) BVCBO (v) BVEBO (v) Double base.

70 8 4 12 6.2

120 14 6 16 7.0

180 23 8 20 7.8

Table c: Comparison of the new process flow with the conventional BiCMOS process. n MOS (0.6 x 40m2) Parameter VTO (V) I DSAT mA BVDSS (V) Min 0.60 16 9 Typical 0.75 19 12.7 I DSAT 475 n/m Max 0.90 22 -

p MOS (0.6 x 40m2) Parameter VTO (V) I DSAT (V) Min -0.95 -12.8 Typical -0.80 -10.8

I DSAT 270 n/m Max -0.65 -8.8

BVDSS (V) -10.8 -9.0 1. The lateral and the vertical dimensions of the emitter can be scaled in a co-ordinated manner, thereby enabling the peripheral component of its emitter/base junction capacitance to be maintained at a reasonable value. 2. Defects in the vicinity of the emitter base junctions of conventional ion implanted emitters give rise to severe yield problems [141]. These defects are associated with the residual damage caused by the emitter formation implant (i.e damage that remains even after 7

post-implant annealing) [26].

With a polysilicon emitter.

The

problem is eliminated because the dopants are implanted into the polysilicon and the emitter-base junction is formed by diffusion into undamaged silicon. 3. The occurrence of Al spiking of the emitter-base junctions is significantly reduced.