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<rehan.hafiz@seecs.edu.pk>
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010 Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library
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Outline & Introduction, Initial Assessment of students, Digital design methodology & design flow Combinational Logic Review + Verilog Introduction, Combinational Building Blocks in Verilog Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS), Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements
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Micro-Architecture
Optimizing Speed
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Optimizing Area
FIR Implementation
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CDC Issues
Fixed-Point Arithmetic
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Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW
DFG representation of DSP Algorithms, Iteration Bound & Retiming Unfolding Look ahead transformations Course Review & Project Presentations Project Presentations
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Verilog Basics
Verilog
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Description Creates your Datapath Creates your circuit Its simulation isEvent Based
Data Types
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Nets
Connection between hardware elements Default value Z High Impedance [not driven by circuit] Declared as Wire A variable that holds a value (need to be careful)? Synthesizable to register or latch Declared as reg Wire [7:0] bus; 8 bit bus, with bit-7 as the most significant
Registers
Vectors
Memories
reg reg
mem1bit [0:1023]; // 1K 1 bit words [7:0] membyte [0: 1023]; // 1K 8 bit words
Others
Accessing 3D Array
d[i1][i2][i3]
http://www.sutherland-hdl.com/papers/2000HDLCon-paper_Verilog-2000.pdf
wire Write_enable; // wire is a keyword & Write_enable is an identifier Unknown Value: X, e.g. Un-initialized value, A net driven by two primitives High Impedance: Z, e.g. Tristate Buffer, Bi-directional I/O
Rule: Input in a module is always a wire module Sample_Name (a,b,c_o,sum) output reg c_o, sum ; input a,b reg or net Input net
Output
endmodule
Verilog Operators
Arithmetic operators: +, -, *, /, % Logical operators: &&, ||, ! Bitwise operators: &, |, ~, ^, ^~ Equality operators: ==, !=, Relational operators: >, <, >=, <= Reduction operators: &, ~&, |, ~|, ^ Shift operators: >>, << Concatenation {} Conditional: cond_expr ? true_expr : false_expr
Examples
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~4'b0001 = 1110 4'b0001 & 4'b1001 = 0001 4'b0001 | 4'b1001 = 1001 & 4'b1001 = 0 // And across all the bits, Can be used to raise flags such as waiting for a 1 from multiple inputs | 4'b1001 = 1 4'b1001 << 1 = 0010 4'b1001 >> 1 = 0100 {4'b1001,4'b10x1} = 100110x1 // Can be used to concatenate wires/buses
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Combinational Logic
Output is Boolean function of its input variables on instantaneous basis Forgets its results when the inputs are no longer available
CIL
NAND Structures
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Any Boolean function can be realized Transformation of Sum of Products (SoP) to NAND
Put inverter before OR gate & after AND gates Replace inverted input NOR by NAND
NOR Structures
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Put inverter before AND gate & after OR gates Replace inverted input AND by NOR
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Gate-Level modelling
Verilog
gate Primitives
Dataflow Modelling
Continuous Assignment
Behavioural Modelling
Structured Procedures:
Initial & always blocks Blocking & Non-blocking statements HLL Higher language constructs (if, switch, case, loops)
module Sample_Name (a,b,c_o,sum) output reg c_o, sum ; reg or net input a,b Input net
Behavioural statements Procedural Assignments Always/initial blocks Blocking/Non Blocking Statements reg or net net
Output
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endmodule
reg or net Behavioural statements (always blocks) LHS must be reg reg
Output
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endmodule
Assignment
Procedural (reg, integer, real, time) Value placed on a variable will be retained unless modified by another procedural assignment In always/initial block
Blocking
Non-Blocking
Initial Block
Always block
Non synthesizable Used only in stimulus Multiple blocks execute concurrently Simulation
More like HW/ Synthesizable Can instantiate multiple initial & always blocks Simulation
Starts execution at time t=0 Execute until they come to a #delay operator; delay & than resume
A>B
A=B A<B
A1
B1
A0
B0
1 0
0 1 0 0 0 0 0 0 0
0 1
0 0 1 1 1 1 0 0 0
0 0
0 0 0 0 0 0 1 1 1
0 0
0 0 1 1 1 1 0 0 0
0 0
1 1 0 0 1 1 0 0 1
0 1
0 1 0 1 0 1 0 1 0
1
0 0 1 0
0
1 0 0 1
0
0 1 0 0
1
1 1 1 1
0
1 1 1 1
1
0 0 1 1
1
0 1 0 1
Chapter 6 <Verilog - Samir> operator types Arithmetic, Logical, Relational, Equality, Bitwise,Shift, etc
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Logic Block
Basic elements:
Configurable Logic blocks (CLB) I/O blocks Interconnection wires and switches Memories Clock Managers Multipliers, FPU Processor Cores
Other elements
I/O Block
Xilinx CLB
Configurable logic block (CLB) Slice CLB CLB Logic cell Logic cell Slice Logic cell Logic cell
Programmable Interconnects
The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)
y mux flip-flop q
The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)
= ab + ab c_out = a.b
module Add_half ( sum, c_out, a, b ); inputa, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule
Concatenation
a b
Add_half
sum c_out
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..DEMO
module test_halfadder; reg a,b; wire sum, c_out; Add_half uut ( // Instantiate the Unit Under Test (UUT) .sum(sum), .c_out(c_out), .a(a), .b(b) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100; a = 1; b = 0; end endmodule
Reading Assignment
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Suggested Reading
<Samir>
Reading Assignment
<CIL>
8.14-8.17
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Multiplexers
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n input datapath; single output datapath MUX/DEMUX establish dynamic connectivity b/w datapaths Data Routing Selecting data from different sources Example: Selecting data from Functional units in a CPU, TDM
Multiplexer [4to1]
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Symbol
De-multiplexers
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Reverse of Multiplexer Single input datapath; n output datapaths; m nit address Example: Data to Functional Units in a CPU from Register file
n = 2^m
Encoders
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Transforms an input word to a different word . n-inputs, m-outputs n = 2^m Usually Reduces the datapath Can generate a unique pattern for each input line
0000 00
Examples
0001
0010 0100
01
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Encoder Verilog
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Decoders
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an instruction and directing a Functional Unit to act Locating a word in a memory using row, column address decoding
Decoder
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Reading Assignment
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Suggested Reading
<CIL>
Reading Assignment
<CIL>
8.14-8.17
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Good Guidelines
Good Coding
HDL
Coding Guidelines for Student Projects, Nestor, J.A.; , IEEE Conference on Microelectronic Systems Education (MSE), 2011 http://www.inno-logic.com/resourcesTips.html
Stephenson and P. Metzgen, "Logic Optimization Techniques for Multiplexers," Altera Literature, 2004
Good Guidelines
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This may happen after correcting an interface mismatch or adding some missing functionality while debugging the design. Any such logic should be made part of the combinational logic of one of the constituent modules. Prevents the synthesis tool from generating a fully optimized logic.
Good Guidelines
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module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); 58 always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; 2'b10 : decoder_op = 2'b01; endcase end endmodule
module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); 59 always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; 2'b10 : decoder_op[0] = 1'b1; endcase end endmodule
module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); 60 always @ (opcode) begin case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; endcase end endmodule
Missed Case
module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) 61 begin decoder_op = 2'b01; case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; endcase end endmodule
module Decoder( input [1:0] opcode, output reg [1:0] decoder_op ); always @ (opcode) begin 62 decoder_op = 2'b01; case(opcode) 2'b01 : decoder_op = 2'b01; 2'b00 : decoder_op = 2'b01; 2'b11 : decoder_op = 2'b10; default : decoder_op = 2'b10; endcase end endmodule
In summary..
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This avoids latches for the situation where we are not assigning values to a particular reg/signal for a particular condition
This avoids latches that shall/may be inferred by synthesizer when we miss/forget specifying a particular condition This may not be required for some synthesizers; but is a good practice.
Still better to follow best practices E.g. Some synthesizers; although they are able to extract Priority Encoders they may not synthesize it Synthesis reports are good resource
Avoid Combinational Feedback The designer must avoid any combinational feedback in RTL coding
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LECTURE ENDS