Analog input subsystem

input
transducer
signal
conditioning
sample
& hold
analog to
digital conv.
Property being
measured
Digital value
to CPU
convert property to
electrical voltage/current
produce convenient voltage/current
levels over range of interest
hold value during conversion
Analog output subsystem
digital to
analog conv
signal
conditioning
output
transducer/
actuator
Property being
controlled
Digital value
from CPU
convert binary code to an
analog voltage/current
produce convenient voltage/current
levels over range of interest
convert electrical signal to
mechanical or other property
Multichannel analog input subsystem
input
transducer
signal
conditioning
sample
& hold
Analog to
Digital Conv.
Property1
Digital value
mux
input
transducer
signal
conditioning
Property2
input
transducer
signal
conditioning
PropertyN
Select
channel

Analog subsystem properties

Accuracy: degree to which measured value differs
from true value
Resolution/precision: degree to which two conditions
can be distinguished
Related to #bits in digital value
Range: minimum to maximum useful value
Linearity: y = Ax + B (correction reqd if not linear)
piecewise linear approximation over different ranges
Repeatability: same measurement for a given value
affected by hysteresis or other phenomena
Stability: value changes other than due to the
property being measured (eg. T affecting P)
Analog to digital conversion errors
May need to correct in software
Offset error
Gain error
Nonlinearity error -
Unequal distances
between transition points
Quantization error:
Difference between digital
& analog values
Usually want LSB
Transducers
Convert physical quantity to electrical signal
Self-generating generates voltage/current signal
Non-self-generating other property change (ex. R)
Examples:
Force/stress (strain gage)
Temperature (thermocouple, thermistor, semicond.)
Pressure
Humidity (gypsum block)
Smoke
Light (phototransistor, photoconductive cell)
Acceleration (accelerometer)
Flow
Position (potentiometer, displacement)
Temperature sensors
Thermocouple Seeback EMF produced by
heating junction of dissimilar metals (V)
Thermistor mix of materials in ceramic
Metal conductor:
)] ( 1 [
0 0
T T R R
t
+ =
+ V -
| | To T
t
e R R
/ 1 / 1
0

=

Negative temperature coefficient: R^ with Tv
Linear over small range
Positive temp. coefficient: R^ with T^
-
+
Vcc
V
BE
V
BE
V
BE
Semiconductor temperature sensor
(

=
Is
Ic
q
kT
V
BE
ln
Base-emitter voltage approximately proportional to T
T V
BE

Analog Devices AD590 Temperature
Transducer
IC generates current proportional to
temperature
Generated current I
T
is linear: 1 a/
o
K
Example:
Design a temperature monitor with
output in the range [0v..4v] over
temperature range [-20
o
C .. +60
o
C]
(Use summing amplifier)
I
T
Strain Gage
Measure stress by measuring change or
resistance of a conductor due to change of its
length/area
Compression: L decreases, A increases
Elongation: L increases, A decreases
Gage factor (sensitivity):
A
L
|
.
|

\
|
=
Ao
Lo
R
L L
R R
S
/
/

=
Wheatsone bridge
Measure small resistance changes
(

+
=
|
.
|

\
|
+

|
.
|

\
|
+
=
Rs R
Rs
V
Rs R
Rs
V
R R
R
V Vo
ref
ref ref
2
1
Some pressure sensors use bridge with all 4 Rs variable
Balanced: Vo = 0 when R=Rs
Signal conditioning
Produce noise-free signal over working
input range
Amplify voltage/current levels
Bias (move levels to desired range)
Filter to remove noise
Isolation/protection (optical/transformer)
Common mode rejection for differential signals
Convert current source to voltage
Conditioning often done with op amp circuits
Operational amplifiers
Amplifier types:
Inverting amplifier
Non-inverting amplifier
Summing amplifier
Differential amplifier
Instrumentation amplifier
Tradeoffs
Inverting/noninverting
High input impedance
Defined gain
Comon mode rejection
Basic op amp configurations
2
2 1
/
2 1
2
R
R R
Vi Vo
R R
R
Vo Vi
+
=
|
.
|

\
|
+
=
Inverting amplifier
Noninverting amplifier
Noninverting version has high input impedance
1
2
2 1
R
R
Vi
Vo
R
Vo
R
Vi
=
=
Differential amplifier
2 1
1 2 0 1
2 1
1
R R
V R V R
Vx
R
Vo Vx
R
Vx V
+
+
=

2 1
2 2
2 1
2
R R
R V
Vx
R
Vx
R
Vx V
+
=
=

) 1 2 (
1
2
V V
R
R
Vo =
Choose R1 to set input impedance; R2 to set gain
Eliminates common mode
voltage (noise, etc.)
Instrumentation amplifier
|
.
|

\
|
(

+ =
3
4
1
2 2
1 ) 1 2 (
R
R
R
R
V V Vo
High input impedance, common mode rejection
Can match R2, R3, R4 on chip and use external R1 to set gain
Sample-and-hold
Required if A/D conversion slow relative to
frequency of signal:
Close switch to sample Vin (charge C to Vin)
Aperture (sampling) time = duration of switch closure
Open switch to hold Vin
converter
V
in
C
Analog to digital conversion
Given: continuous-time electrical signal
v(t), t >=0
Desired: sequence of discrete numeric values that
represent the signal at selected sampling times :
v(0), v(T), v(2T),v(nT)
T = sampling time: v(t) sampled every T seconds
n = sample number
v(nT) = value of v(t) measured at the n
th
sample time and
quantized to one of 2
k
discrete levels
A/D conversion process
v(t)
t T 2T 3T 4T 5T 6T 7T
1 2 3 4 5 6 7
v(t*)
t*
k
v(kT)
Input signal
Sampled signal
(3/4)V
ref
Sampled & quantized
Sampled data sequence:
10, 10, 10, 10, 11, 11, 11
Binary values of n, where
V(kT) = (n/4)V
ref
(2/4)V
ref
(1/4)V
ref
(0/4)V
ref
A/D conversion parameters
Sampling rate, F (sampling interval T = 1/F)
Nyquist rate 2 x (highest frequency in the signal) to
reproduce sampled signals
Examples:
CD-quality music sampled at 44.1KHz
(ear can hear up to about 20-22KHz)
Voice in digital telephone sampled at 8KHz
Precision (# bits in sample value)
k = # of bits used to represent samples
precision: each step represents (1/2
k
)*V
range
accuracy: degree to which converter discerns proper level
(error when rounding to nearest level)
Analog to digital conversion
More difficult than D/A conversion
Tradeoffs:
Precision (# bits)
Accuracy
Speed (of conversion)
Linearity
Unipolar vs. bipolar input
Encoding method for output
Cost
Often built around digital to analog converters
Digital to analog conversion
R-2R Ladder Network

=
|
.
|

\
|
=
N
k
k
k
b Vr Vout
1
2
1
(Reference)
Equivalent
resistance = R
I/2
n+1
Equivalent
resistance = R
Current to
voltage
number = b
n
*2
n
+ b
n-1
*2
n-1
+ . + b
1
*2
1
+ b
0
*2
0
Digital to analog conversion
bits of digital word
reference
voltage
Vr/2 Vr/4
Vr/8
Vr/2
n-1
Vr/2
n
contribution to
Vout when switch
connected to Vr
Bit k => Vr/2
k

=
|
.
|

\
|
=
N
k
k
k
b Vr Vout
1
2
1
Source: http://www.irctt.com/pdf_files/LADDERNETWORKS.pdf
DAC 0831 8-bit D/A converter
Input latches can be made transparent
Flash A/D conversion
N-bit result requires 2
n
comparators and resistors:
encoder
V
in
...
V
ref
n-bit
output
Identify bit at which
comparator outputs
change from 1->0.
Comparator output = 1 if Vin > Vref*(N/2
n
)
(N = 1, 2, . 2
n-1)
|
|
.
|

\
|
=
R
R
Vref V
n
n
2
) 1 2 (
*
Comparators
Thermometer code bottom k bits = 1, upper 2
n-1
-k bits = 0
Dual-slope conversion
Use counter to measure time required to
charge/discharge capacitor (relatively low speed).
Charging, then discharging eliminates non-linearities
(high accuracy).
Relatively low cost
V
in
control
counter
-V
ref
clock
n-bit output
-
+
comparator
1. SW1 connects Vin for fixed time T
C charges with current = Vin(t)/R
Dual-slope conversion steps
Vin
RC
T
dt t Vin
RC
dt t i
C
t Vo
T T
c
= = =

0 0
) (
1
) (
1
) (
-Vo(t)
Constant slope
Slope Vin
T t
1
2. SW1 connects Vref until Vo discharges to 0.
C discharges with constant current = -Vref/R
When Vo(T+t1) = 0:
Dual-slope conversion steps

+
+ = +
1
1
) (
1
) (
0
1
t T
T
ref
T
dt V
RC
dt t Vin
RC
t T Vo
-Vo(t)
Constant slope
Slope Vin
T t
1
Vref
T
t
Vin
dt V
RC
dt t Vin
RC
t T
T
ref
T
|
.
|

\
|
=
=

+
1
0
1
1
) (
1
Use a counter
to measure t1.
Successive approximation A/D converter
Vin
Successive
Approximation
Register (SAR)
D/A Converter
(R/2R ladder)
clock
Digital
Output
7
6
5
4
3
2
1
0
+ -
Comparator
Vout
1. Clear all bits of SAR
2. Set SAR bit 7 = 1
3. If Vout < Vin, keep 1
If Vout > Vin, reset to 0
4. Repeat steps 2-3 for
bits 6-0.
5. SAR bits 7-0 = converted
value
Vref
National Semiconductor ADC0804
Analog-to-Digital Converter
Successive approximation A/D converter
8-bit data: precision = (1/256)V
range
Accuracy: 1 LSB
Conversion time: 100s
Input voltage range: 0 to 5v
Built-in reference (Vcc/2)
Can also use external reference: Vref/2
Microprocessor bus compatible
Input
Address
IOR*
IOW*
Address
Reference
(if used)
Clock
Components
Data bus
SAR
D/A
Data
ready
ADC0804 functional diagram
Source: National Semiconductor Data Sheet
ADC0804 pin diagram
DB7-0: data bus interface
CS*: chip select (address)
RD*: read enable (IOR*)
- CS* & RD* active puts data on
DB7-0.
- Otherwise, DB7-0 tri-stated
WR*: write enable (IOW*)
- CS* & WR* active triggers new
conversion
INTR*: interrupt
- Set to 1 at start of conversion
- Set to 0 when conversion finished
- Set to 1 when data rea
V
IN
(+),V
IN
(-) analog input voltage
CLK IN, CLK R clock components
Vref/2 reference voltage (1/2 Vcc if open)
Source: National Semiconductor
Data Sheet
HCS12 analog-to-digital converter
PORTAD pins
(Cady, Figure 17-2)
Freescale MAC7100
Successive-Approximation ADC
LPC 22xx Analog to Digital Converter
10-bit successive approximation A/D converter
2.44s conversion for 10 bits (410 Ksamples/sec)
Programmable precision: 3 to 10 bits
Conversion time = #bits + 1 clock cycles
0 to 3 volt measurement range
Ref. voltage pins: V3A (3v), VSSA (gnd)
Analog multiplexer for inputs Ain0-Ain7
4-input (LPC21xx or LPC22xx in 64-pin pkg)
8-input (LPC22xx in >64-pin pkg)
LPC 22xx A/D control register (ADCR)
Edge Start Test PDN CLKS Burst CLKDIV Sel
27 26 25 24 23 22 21 20 19 18 17 16 15 . 8 7 0
Edge = select rise/fall edge of trigger signal
Start = trigger source to start conversion
000 = halt
001 = start now (software control)
010-111 : Hardware-controlled: convert channels in Sel from 0-7
010/011 = P0-16/P0-22 pin triggers conversion
100-111 = MAT0-1, MAT0-3, MAT1-0, MAT 1-1
match event triggers conversion
Burst = 0 for software control, 1 for hardware control
CLKS = # clocks (4 to 11) => resolution 3 to 10 bits
Sel = Pin(s) to be sampled (one bit per pin)
CLKDIV = pclk divider (divide to 4.5MHz or lower)
PDN = 1 to enable the converter, o/w power down
LPC 22xx A/D data register (ADDR)
Done Overrun CHN V/V3A
31 30 29 28 27 26 25 24 23 . 16 15 . 6 5 .0
Converted sample
(represents V / Vref)
Channel #
of converted
sample
Conversion done
(sample valid)
--------------------------
Clears on data read
New sample has overwritten
previous (unread) sample
S/W-controlled example
VPBDIV = 0x02; // pclk = 30MHz
IO1DIR = 0x00FF0000; //P1.16-23 outputs
ADCR = 0x00270601; //10 bits @ 3 MHz
ADCR |= 0x01000000; // set START bit
while (1) {
val = ADDR; // read data reg
check DONE & repeat until 1
}
H/W-controlled example
VPBDIV = 0x02; // pclk = 30MHz
IO1DIR = 0x00FF0000; //P1.16-23 outputs
ADCR = 0x00270607; //10 bits @ 3 MHz
ADCR |= 0x01000000; // enable conversion
VICVectCnt10 = 0x32;
VICVectAddr0 = (unsigned) AD_ISR;
VICVectEnable = 0x00040000;
while (1) {}
ISR on next page
HW-controlled example (continued)
void AD_ISR (void) __irq {
unsigned val, chan;
static unsigned result[4];
` val = ADDR; // read data reg
val = ((val>>6) & 0x03FF); // result
chan = ((ADCR>>0x18) & 0x07); //channel
result[chan] = val; // save
}
Sigma Delta ADC
High resolution (16 or more bits)
High integration
Reasonable cost
Often used to sample CD-quality audio
16-bit resolution @ 44.1Ksamples/sec
Oversampling used to spread noise over
wider frequency range
Digital filtering eliminates the noise
Gives good dynamic range with simple ADC
Sigma-Delta ADC
High rate bitstream
Density of 1s at
modulator output
proportional to the
input signal.
Filtering extracts
Info from serial
data stream.
(lower rate)
Sigma-Delta A/D Converter
Comparator
Modulator operation
Slope of integrator output depends on
magnitude of Vin
sigma => summing/integration
Compare integrator output to 0v, producing
1 if positive and 0 if negative (1-bit ADC)
delta = difference
Density of 1s in the bitstream proportional to
magnitude of input voltage Vin
Example
Filtering determines average voltage (density of 1s) in bitstream
Maxim MAX1402 Sigma-Delta ADC
ADC converter characteristics
Type Need
SHA
?
Cycles/
conversion
Advant-
ages
Disadvant-
ages
Example
Flash No 1 Fastest Expensive,
power
6-bit @
400MHz
Successive
Approx-
imation
Yes >= 2 Fast,
cheap
Slower
than flash
8-bit @
20 MHz
Integrating Yes Varies Precise Slow 22-bit @
20Hz
Sigma-
Delta
No Many Mostly
digital,
linear,
high
resolution
Complex
digital
circuit
16-bit @
100 KHz
ADC converter comparison