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Solid State Engineering

Chapter 1 Introduction NCHU EE, Professor F. H. Wang,


e-mail : fansen@dragon.nchu.edu.tw

Many Processes used in Microelectronics Technology

In This Book:

Unit I: Hot (or energetic) Processes Unit II: Pattern Transfer (Lithography) Unit III: Thin Films Deposition Unit IV: Process Integration

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Contents (I)

Unit I: Hot (or energetic) Processes


Diffusion Thermal Oxidation Ion Implantation Rapid Thermal Processing

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Contents (II)

Unit II: Pattern Transfer


Optical Lithography Photoresists Etching

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Contents (III)

Unit III: Thin Films

Physical Deposition: Evaporation and Sputtering (chapter 12)

Chemical Vapor Deposition (chapter 13)

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Contents (VI)

Unit IV: Process Integration

Device Isolation, Contacts, and Metallization CMOS Technologies IC manufacturing

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Goal of this Course


The goal of this course is to teach the fundamentals of Microelectronic Technology Emphasis will be placed on multidisciplinary understanding Desired Outcome: Provide the student with enough basic information

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Disciplines
5 2 1 3

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Introduction to Semiconductor Manufacturing Technology Chapter 1, Introduction

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Objective
After taking this course, you will able to

Use common semiconductor terminology Describe a basic IC fabrication sequence Briefly explain each process step Relate your job or products to semiconductor manufacturing process
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IC
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Introduction

First Transistor, AT&T Bell Labs, 1947 First Single Crystal Germanium, 1952 First Single Crystal Silicon, 1954 First IC device, TI, 1958 First IC product, Fairchild Camera, 1961

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First Transistor, Bell Lab, 1947

Photo courtesy: AT&T Archive

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First Transistor and Its Inventors

John Bardeen, William Shockley and Walter Brattain


Photo courtesy: Lucent Technologies Inc.
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First IC Device Made by Jack Kilby of Texas Instrument in 1958

Photo courtesy: Texas Instruments

First Silicon IC Chip Made by Robert Noyce of Fairchild Camera in 1961

Photo courtesy: Fairchild Semiconductor International


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2005 Top 10 Semiconductor Company


Company Intel Samsung TI Toshiba ST() Renesas() Infineon NEC Hynix AMD
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2005(f) 351.36 178.5 104.5 93.06 88.25 88.01 82.77 57.93 57.3 56.87
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2005 15% 7.6% 4.4% 4.0% 3.8% 3.7% 3.5% 2.5% 2.4% 2.4%
Source:Gartner, 2005/12
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2005
(1)Applied Materials623400 (2)Tokyo Electron445500 (3)ASML Holding316 000 (4)KLA-Tencor20500 (5)Advantest 196000 (6)Nikon156600 (7)Lam Research138200 (8)Novellus Systems13200 (9)Hitachi High-Technologies127700 (10)Canon124700
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Silicon () and germanium () Compound semiconductors ()


SiGe, SiC GaAs, InP, etc.

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Classifications of Electronic Materials ()

Electrical/Computer engineers like to classify materials based on electrical behavior (insulators and conductors). Chemists or Materials Engineers/Scientists classify materials based on bond type (covalent, ionic, metallic, or van der Waals), or structure (crystalline, polycrystalline, amorphous, etc...).

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Classifications of Electronic Materials (Chemistry)

Materials Classified based on bond strength

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Classifications of Electronic Materials (EE)


metals. insulators. semiconductors.

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Material Classifications based on Bonding Method

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Material Classifications based on Bonding Method

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Type of Crystalline Solids

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P-type Dopant

Types of Semiconductors:

N-type Dopants

Elemental: Silicon or Germanium (Si or Ge) Compound: Gallium Arsenide (GaAs), Indium Phosphide (InP), Silicon Carbide (SiC), CdS and many others Note that the sum of the valence adds to 8, a complete outer shell. I.E. 4+4,3+5, 2+6, etc...
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Silicon

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Group 4 Elements

*Only has a measurable bandgap near 0K **Different bonding/Crystal Structure due to unfilled higher orbital states
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N()

Si

Si

Si

Conducting band, Ec Eg = 1.1 eV Ed ~ 0.05 eV

Si

As

Si

Si

Si

Si

Valence band, Ev
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P()
Conducting band,Ec
Si Si Si

Hole
Si B Si

Eg = 1.1 eV Ea ~ 0.05 eV

Si

Si

Si

Electron

Valence band, Ev

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Classifications of Electronic Materials

Compound Semiconductors(): Offer high performance (optical characteristics, higher frequency, higher power) than elemental semiconductors. Binary: GaAs, SiC, etc... Ternary: AlxGa1-xAs, InxGa1-xN where 0<=x<=1 Quaternary: InxGa1-xAsyP1-y where 0<=x<=1 and 0<=y<=1 Half the total number of atoms must come from group III (Column III) and the other half the atoms must come from group V (Column V) (or more precisely, IV/IV , III/V, or II/VI combinations).
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Classifications of Electronic Materials

Material Classifications based on Crystal Structure

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Classifications of Crystalline Electronic Materials

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Resistivity () P-type, Boron ()

N-type, Phosphorus () Dopant concentration ()


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(electrons) (holes)

NP

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IC
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Resistor () Capacitor () Diode () Bipolar Transistor () MOS Transistor () Memory Device DRAM , SRAM , Non-volatile memory Optoelectronic Device TFTLCD, LED

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Resistor ()

l h w

l R wh
:


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Capacitor ()

h d

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hl C d
: Dielectric Constant()

ex. DRAM () High-k


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Capacitor ()
Dielectric Layer () Poly 2

Poly Si Oxide Si

Poly Si Poly 1

Si

(flat)
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(stack)
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(trench)
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Parasitic Capacitor ()
Dielectric, Metal,

l d w

(parasitic capacitor)
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Diode ()

P-N Junction (forward bias)


V1 V2 P1 P2

V1 > V2 , V1 < V2 ,
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current no current

P1 > P2,

current

P1 < P2, no current


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-(I-V curve)

I V -I 0
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Bipolar Transistor ()

PNP or NPN Switch () Amplifier () Analog circuit () Fast high power device ()

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NPN and PNP


E B C
C

E
N P

B
N

E
B E
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B
P N P

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NPN

n+

AlCuSi SiO2 p+

p+

n+ N

Electron flow n+ P-substrate

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NPN
Metal CVD oxide Base Poly Field oxide p Emitter n+ n Epi n+ p Field oxide Buried Layer n+ Field oxide CVD oxide Collector CVD oxide

P-substrate
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MOS Transistor ()

Metal-oxide-semiconductor ( ) Also called MOSFET (MOS Field Effect Transistor) ()

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NMOS
VG Ground
VG = 0

VD
VD

Positive charges Electron flow VG > V T > 0 VD > 0

Metal Gate
Metal Gate

SiO2 SiO2 n+ Source p-Si n+ Drain

n+ Source

+++++++ p-Si

n+ Drain

Negative charges No current


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PMOS
VG Ground
VG = 0

VD
VD

Negative charges Hole flow VG < V T < 0 VD > 0

Metal Gate SiO2 SiO2 p+ Source n-Si p+ Drain Positive charges No current
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p+ Source

+++++++ n-Si

p+ Drain

Devices with Different Substrates

Silicon

Bipolar MOSFET BiCMOS

Dominate IC industry

SiliconSiliconGermanium Compound
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Bipolar: high speed devices

GaAs: up to 20 GHz device Light emission diode (LED)


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Market of Semiconductor Products


Compound 100% Bipolar

4% 8%

50% MOSFET 88%

1980
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1990
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2000
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Bipolar IC ()

Earliest IC chip 1961, four bipolar transistors, $150.00 TV VCR Cellular phone, etc.

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PMOS and NMOS

PMOS

First MOS field effect transistor, 1960 Used for digital logic devices in the 1960s Replaced by NMOS after the mid-1970s Faster than PMOS Used for digital logic devices in 1970s and 1980s Replaced by CMOS after the 1980s
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NMOS

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CMOS (Complement MOSFET)

80IC

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CMOS Inverter ()
Vdd
Gate Source

PMOS
Drain

V in
Drain

Vout NMOS
Gate Source

Vss
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BiCMOS (Bipolar + CMOS)


CMOS Mainly in 1990s CMOS as logic circuit Bipolar for input/output Faster than CMOS 1

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IC Chips

Memory () Microprocessor ()

Application specific IC (ASIC) ()

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Memory Chips

Volatile memory ()

Dynamic random access memory (DRAM) Static random access memory (SRAM) Erasable programmable read only memory (EPROM) () EEPROM FLASH Memory
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Non-volatile memory


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DRAM

DRAM, EDO DRAMSDRAMDDR DRAMDirect RDAM DDR2 IC One transistorone capacitor

Word line () NMOS Bit line ()


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Capacitor

GND
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DRAM
DRAM NMOS (word line) NMOS /(bit line)
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DRAM

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SRAM

SRAM (Cache Memory) DRAM


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Bit select
Vcc

Bit

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EPROM ()

Non-volatile memory

(Memory ) 10
bios Floating gate () UV

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EPROM
Passivation Dielectric () VG

VD

Inter-poly Dielectric

Poly 2 Poly 1

Control Gate Floating Gate

Gate Oxide

n+ Source p-Si

n+ Drain
66

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EPROM Programming
Passivation Dielectric

VG>VT>0

VD > 0

Inter-poly Dielectric

Poly 2 e- e- e- e- e- e-

Control Gate Floating Gate e-

Gate Oxide

n+ Source p-Si

n+ Drain
Electron Tunneling( )
67

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EPROM Erasing Process


Passivation Dielectric UV light

Inter-poly Dielectric

Poly 2 e- e-

Control Gate Floating Gate

Gate Oxide

n+ Source p-Si

n+ Drain
Electron Tunneling
68

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Flash Memory
(NVRAM ) 10 (EEPROM ) EEPROM (bite ) (Data) (Digital Camera ) EEPROM
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TFT-LCD

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Equivalent Circuits in TFT-LCD


LC layer

Display area

TFT

1 dot cross sectional view

Scan line (n) Data line


Clc Vcom

storage capacitor Cst

LCD Monitor 1024x768x3 dots


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Scan line (n-1)


1 dot equivalent circuit
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Amorphous-Si TFT

Comparison of two-type a-Si TFT

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Poly-Si TFT
ITO
2nd interlayer Al 1st interlayer

Gate N+ N+ P+

Gate P+
Buffer SiO2

Gate N+ N+

Glass

N channel
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P channel
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Pixel
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LED

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IC
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Development History

First Transistor(), AT&T Bell Labs, 1947 First Single Crystal Germanium(), 1952 First Single Crystal Silicon(), 1954 First IC device, TI, 1958 First IC product, Fairchild Camera, 1961

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Pioneers of Transistor

The 1st Transistor, Bell Lab, 1947

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Grown Junction Technology

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Alloy Junction Technology

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Double Diffused Mesa Transistor

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Planar Process

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State-of-the-Art ICs1960 vs. 1990

Photo courtesy: Fairchild Semiconductor International

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Wafer vs. Chip

From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall

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IC Scales
Integration level Small Scale Integration Medium Scale Integration Large Scale Integration Very Large Scale Integration Ultra Large Scale Integration Super Large Scale Integration Abbreviation SSI MSI LSI VLSI ULSI SLSI Number of devices on a chip 2 to 50 50 to 5,000 5,000 to 100,000 100,000 to 10,000,000 10,000,000 to 1,000,000,000 over 1,000,000,000

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(Chip)

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Modern Electronics

0.13 um

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Comparison : IC vs. Hair

Modern devices have lateral dimensions that are only fractions of a micron (~0.1 m) and vertical dimensions that may be only a few atoms tall.

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Moores Law
Gorden Moore 1964 12 198018 2010

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Advantages of Technology Scaling

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IC Technology Scaling

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Channel Length Scaling

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SIA Roadmap

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DRAM

DRAM

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Minimum Feature Size


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Killer Defects()

Y = 28/32 = 87.5%
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Y = 2/6 = 33.3%
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Power Density

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Process Flow: Key Issues

Number and kinds of processes and how they are integrated together. Important Metrics: thermal budget, layout density, process cost (masks and steps) Leverage Points: self-aligned techniques, trench isolation, local interconnect, planarization

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Process Integration

MOSIS is a low-cost prototyping and small-volume production service for VLSI circuit development.
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Processing Temperature

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Control of Conductivity is the Key to Modern Electronic Devices


Conductivity, , is material conducts electricity. Ohms Law: V=IR or J=E where J is current density and E is electric field.

Semiconductors: Conductivity can be varied by several orders of magnitude.

It is the ability to control conductivity that make semiconductors useful as current/voltage control elements. Current/Voltage control is the key to switches (digital logic including microprocessors etc), amplifiers, LEDs, LASERs, photodetectors, etc...
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IC
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1960s: PMOS Process


Bipolar dominated MOSFET Si substrate Diffusion for doping


Boron diffuses faster in silicon PMOS


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Wafer Clean, Field Oxidation, and Photoresist Coating


Native Oxide

N-Silicon

N-Silicon

Primer

Field Oxide

Field Oxide

Photoresist

N-Silicon

N-Silicon

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Photolithography and Etch


Source/Drain Mask Field Oxide

Source/Drain Mask

UV Light

Photoresist N-Silicon

PR N-Silicon

Field Oxide

Field Oxide

PR N-Silicon

PR N-Silicon

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Source/drain Doping and Gate Oxidation


Field Oxide
Field Oxide

N-Silicon

p+

p+

N-Silicon

Field Oxide

Gate Oxide

Field Oxide

p+

p+

p+

p+

N-Silicon

N-Silicon

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Contact, Metallization, and Passivation


Gate Oxide AlSi Field Oxide

Gate Oxide

Field Oxide

p+

p+

p+

N-Silicon

N-Silicon

p+

Gate Oxide

Field Oxide

Gate Oxide

CVD Cap Oxide

p+

p+

N-Silicon

p+

p+

N-Silicon

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CMOS Inverter

n+ Source/Drain

Gate Oxide Polysilicon

p+ Source/Drain

p-Si

STI Bulk Si

n-Si

USG

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CMOS Chip with 2 Metal Layers

Nitride PD2 Oxide PD1 Metal 2, AlCuSi IMD PMD p+ n+ Poly Si Gate P-type substrate
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USG dep/etch/dep AlCuSi BPSG LOCOS SiO2 p+

n+

p+ N-well

p+

CMOS Chip with 4 Metal Layers


Passivation 2, nitride Passivation 1, USG Metal 4 Tantalum barrier layer FSG Metal 3 Copper FSG FSG Metal 2 Tungsten plug Copper FSG M1 Cu PSG STI n+ Cu Tungsten n+ USG P-well P-epi NCHU, EE, Prof. F. H. Wang P-wafer p+ N-well p+ PMD nitride barrier layer
109

Lead-tin alloy bump

Copper

Nitride etch stop layer Nitride seal layer Tantalum barrier layer T/TiN barrier & adhesion layer

FSG FSG

Tungsten local Interconnection

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Actual Cross Section View


Metal 5

Metal 4 Metal 3
Metal 2

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Wafer Process Flow


Materials IC Fab Metallization Wafers Thermal Processes Masks Photolithography Design Final Test Implant PR strip Etch PR strip Packaging CMP Dielectric deposition Test

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Memo

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