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GR-DVF31U/DVL40EG
(1999 Fusion DVC Model)
NTSC/PAL
Septmber 1999
INDEX
SECTION 1 OUTLINE OF THE PRODUCTS
1.1 COMPARISON TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1 1.1.1 Comparison table of DV models specification by products year .....................................1-1 1.1.2 DV model chart table of LCD type..................................................................................1-2
INDEX-1
Charging time: AA-V20 used 90 min. (BN-V207) 180 min. (BN-V214) Cap Color LCD 0.55" 113k pixels B/W LCD 2.5" 480 234 = 112k pixels 3" 480 234 = 112k pixels 3.5" 480 234 = 112k pixels Horizontal resolution: 240 lines Amorphous silicon transistor 998 677 = 680k pixels (*998 797 = 800k pixels) Effective aria 711 485 = 340k pixels (*702 575 = 400k pixels) 400 Lines 16 lux (*18 lux) 60 IRE Level Slow Shutter off F1.6 f = 3.9 to 62.4 mm Optical zoom: 16 Digital zoom: 4/10,25 or 28 Max. zoom: 160 ,400 or 450 1/4" Total
Image device
Horizontal resolution Progressive scanning Electric image stabilizer Sensitivity Lens specification Tele macro Zoom ratio
Snapshot
Playback snapshot Playback digital zoom Slow motion Auto flash Video auto light Audio Snapshot search Record end search Audio dubbing
F1.6 f = 3.9 to 62.4 mm Yes Optical zoom: 16 Digital zoom: 4/10 or 8/20 Max. zoom: 160 or 320 5 mode With frame Full Pin-up Pin-up 4-division Pin-up 9-division Yes Yes 10 RM-V712U Yes RM-V712U No Yes 2ch(48kHz) /4ch(32kHz) No No No (Yes:PAL model,32kHz only,RCU only)
Yes 4 RM-V711U (optional: GR-DVF11U) Yes (Frame Advance) RM-V711U (optional: GR-DVF11U) Yes ( /No) 2ch(48kHz) /4ch(32kHz) Yes (32kHz only,RCU only)
JLIP ID number Remote control sensor Button battery (only for clock backup)
Table 1-1-1 Comparison table of DV models specification by products year (2/2) 1.1.2 DV model chart table of LCD type
1998 Fusion DV Model LCD Monitor/ VF Non/ Color 2.5"/ BW CRT 2.5"/ Color 3.0"/ Color GR-DVF20U VICTOR JVC-NTSC GR-DVA1U GR-DVF10U GR-DVF10EG GR-DVF10EK GR-DVF7A GR-DVF10EA GR-DVF25SH GR-DVF1EG GR-DVF1EK JVC-PAL GR-DVF3A GR-DVF15SH
1999 Fusion DV Model LCD Monitor/VF VICTOR JVC-NTSC JVC-PAL GR-DVL20EA GR-DVL33SH GR-DVL38SH GR-DVL40EG GR-DVL40EK GR-DVL45A GR-DVL40EA GR-DVL48ED GR-DVL28ED
2.5"/ BW LCD GR-DVF1 3.0"/ BW LCD 3.0"/ Color 3.5"/ Color GR-DVA1
1-2
IC4301
TMY(8), TMC(4) FMY(8), FMC(4)
IC4302
FIELD MEMORY
IC3001
RD(16) RA(10)
IC3002
16M DRAM
OPTICAL BLOCK
CCD
CCD_OUT
CDS/AGC A/D
CAM_AD(10)
IC3101
1394PHY
TPA+,TPATPB+,TPBDV_JACK
CAMERA_DSP
DYO(4),DCO(4)
DECK_DSP
PD(4)
SSI
DYI(4),DCI(4)
VREF_Y,VREF_C,VREF_RB
ADDT(16)
DV_C, DV_Y
DV_R-Y, DV_B-Y
BUS(16)
IC5501
SUB H1, H2, RG V1,V2,V3,V4 XAVD, XAHD
IRIS PWM
PBDATA
DODAT
IC3201
PBO
IC3301
PB_ENV
AIDAT
HSE
DVEQ
ATFO
DVANA
TG V.DRV
CLK27,CLK18,CLK13 SSI
IC1003
54MHz X5501 X1002 32kHz E 2PROM
IC3503
H_GAIN,H_OFFSET YC_GCTL,ASPECT AFZ_DATA
EVR DAC
IC1004
RTC
IC4851
FOCUS (4)
ZOOM (4)
AFZ_DATA
IC1001
AD(16)
IC1401
ADDT(16)
IC4801,IC4802
DRIVE+,-
SYSCON CPU
IRIS_O/C
S_DT_OUT S_DT_IN
DECK CPU
ANA_DATA
IRIS DRIVER
RX
TX
OSD_DATA
H_GAIN,H_OFFSET TX
PC
DODAT
RX
SRV_TX
IRIS PWM
MDA_IN MDA_OUT
AIDAT
RX
IC3501
PB_ENV HSE
ANA_DATA
ADDT(16)
TX
TX
JLIP
RX
IC2101 IC3701
MIC_AU / R
1F 1S 2F 2S
VIDEO HEAD
PB_AU / R
S OUT
VIDEO DRIVER
IND
IND LCD_IND
IC1002
ON SCREEN
PB_AU / L
RECC_ADJ
SP
A/V OUT
IC2201
AO_SIG / L AO_SIG / R
AUDIO AMP
1 0 VF
LCD PANEL
0 7 MONITOR
MON_R VF_R VF_G VF_B
IC7601 IC7604
SW
R G B LCD_Y
AFZ_DATA
IC1601
MDA_IN,MDA_OUT
CAPSTAN MOTOR
LCD PANEL
MON_G MON_B
LCD DRIVER
MDA
DRUM MOTOR
0 2 SECOND
LOADING MOTOR
3 JUNCTION
IC5501 TG V.DRV
CLK27 VCO405I
54MHz
DVDSP
27MHz
81MHz
1394 LINK
IC3301
DVANA
REF
VCXO
PWM405 VCO405
FRP GEN
PC
Serial I/F
12.288MHz 11.289MHz 8.192MHz PWMAUD
PC
VCO
A012 AVCOC
Fig. 2-1-2 PLL operation block diagram The main clock for the deck section operates at a frequency of 40.5 MHz, which is equivalent to 18 MHz for the previous models. Since two memories of the SHUFFLE memory and the ECC memory that are needed for the previous models are integrated into one DRAM, the clock frequency is raised in order to increase the processing speed. For setting the clock duty ratio exactly at 50 %, 40.5 MHz clock is produced from the 81 MHz clock. The PLL circuit of the main clock system produces 81 MHz clock by the X'TAL X301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse produced from the 81 MHz pulse as the comparison signal of the PLL, the frame pulse (29.97 Hz in NTSC or 25 Hz in PAL) is produced from the 27 MHz pulse output from the camera and this frame pulse is used as the reference signal of the PLL in the general recording and playback modes. However, the frame pulse produced by decoding the input DV signal is used as the PLL reference signal for phase comparison in the 1394 input mode. A phase error is output as the PWM405 signal, which passes through the filter circuit and controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2 V 0.1 V) of the tolerance in the condition that the PLL is locked. There are three audio sampling frequencies (32 kHz, 44.1 kHz and 48 kHz) provided, therefore, master clocks (8.192 MHz, 11.289 MHz and 12.288 MHz) are produced by the VCO in the IC3301 for the respective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjusting the FS-PLL, the respective frequencies are adjusted in the free-run status.
2-2
DV_ANA
PBO
IC3201
AINAD1
DV_EQ AUTO EQ
PB_DATA
LPF
AGC
AD1
1+D
VITERBI
PB_CLK
PLLE REFV
+ -
VOA VOB
2CH DAC
IC3203
PLLO
VCO
CLK
BPF
GCA
ATFO
AINAD2
AD2
ATF
A02 ATF_GAIN
RECCLK
Fig. 2-1-3 PB equalizer and ATF operation block diagram In the playback mode the PB ENV signal output from the PB amp. is branched into two in the IC3301 DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF. In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO EQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed as mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with the playback signal. The 41.85 MHz signal oscillated by the IC3203 VCO is output as the PB clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator (DISCRI) compares the 41.85 MHz signal oscillated from the VCO with the other 41.85 MHz signal produced from the 81 MHz of the main clock in order to detect a difference between the two frequencies. In the general playback mode, the discriminator outputs a Low level signal when the frequency difference is +1 % or more or a High level signal when the difference is -1 % or more. In the other modes, a Low level signal is output when the frequency difference is +3 % or more or a High level signal is output when the difference is -3 % or more. When the frequency difference is within 1 % in the general playback mode or within 3 % in the other modes, the output signal has a high impedance. Therefore, a frequency difference, if there is, is roughly corrected. Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from the playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201 DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection result is transmitted to the servo CPU.
2-3
SYSCON CPU
IC501 EDIT_CTL
DECK CPU
SRV_RX
J507
PC
TX RX
JLIP
To: PC RS-232C
PC Cable
N.C. N.C.
1
REMOTE
Fig. 2-1-6 4-2 edit cable The PC jack (2.5 mm , 3 poles) and JLIP jack (3.5 mm , 4 poles) are provided as the JLIP terminals of this model. Since the IC501 of an RS-232C transceiver is built in the PC terminal, a straight type PC cable (without level converter) can be used for connecting this model with a personal computer. Therefore, a straight type PC cable is contained in the personal computer connecting kit supplied as an accessory or the HS-V4KIT to be supplied as an optional. Since the JLIP terminal is the same as usual, a personal computer can be connected with this model by use of the JLIP-PC cable (QAM0099-002) that internally incorporates a level converter. However, it is recommended to use the PC terminal for connecting a
2-4
SRV_TX
RXD
TXD
GND
MAX3221
IC502
personal computer and to use the JLIP terminals for connecting other JLIP apparatus such as a video deck, video printer and so on, because such the connection enables the user to perform program editing with the JLIP video producer. If this model is used for program editing with the JLIP video producer, only the video deck having the JLIP terminal can be connected with it as a recording unit because it has no remote output terminal (editing terminal). Accordingly, neither video deck having the remote pause terminal nor multibrand remote controller can be connected with this model. This problem can be solved by use of a special 4-pole-to-2pole remote cable while connecting the EDIT CTL with a dead pin of the JLIP terminal (except the US version). When trying to make this connection for program editing with the JLIP video producer, pay heed to the point that it is required to use a special 4-pole-to-2-pole remote cable. If a 2-pole-to-2-pole remote cable is used for connection or a 4-pole-to-2-pole remote cable is revsersely connected, communication with a personal computer and editing operation result in failure because the RX pole of the JLIP terminal is grounded. However, for utilizing the program editing function of this model without use of the JLIP video producer, in other words without connection of a personal computer, either a 4-pole-to-2-pole or a 2-pole-to-2-pole remote cable can be used for connecting a video deck having the remote pause terminal and multibrand remote controller. When a 4-pole plug is inserted into the JLIP jack, the remote pause signal is output from the EDIT CTL. On the other hand, when a 2-pole plug is inserted into the jack, the remote pause signal is output from the TXD because it is detected that the RX pole is grounded. This model is capable of transferring digital still pictures with the JLIP video capture used together. The previous models having the digital still picture output terminal (GR-DVL9000, GR-DVL9500) use the VRAM (field memory) as the capture memory and output digital video data from the TXD through the CAMERA DSP and SYSCON CPU, while the personal computer receives and saves digital data in the DVF format. Differently from this system currently in use, this model outputs DV playback data that is saved in the DRAM from the SRV-TX through the DECK DSP and DECK CPU. At that time, only the image data is extracted from the DV playback data not to be accompanied with the other data such as audio data, sub code, etc., and the image data is output as the DV stream data. Receiving the image data, the personal computer (JLIP Video Capture Ver.3.0) manages the whole image data of an album in one file (extension: **.vna). For saving an image data as an image file, open an album on the personal computer and select desirable data, which will be saved as a JPEG, BMP or DVF formatted file when "Save Image As ..." operation is executed.
2-5
GND GND AL3V Chip select to DECK_CPU IC1401 Flicker detect Chip select to F/Z DRIVER IC4851 Power supply System clock (24MHz) System clock (24MHz) GND Field discrimination signal H: fixed Reset Snap shot switch input Video mute JLIP interrupt Vertical sync signal EIS data readout timing Not used Menu dial pulse Frame reference pulse
2-6
2-7
2-8
2.2.2 DECK CPU (IC1401) function 1. DECK CPU (IC1401) pin functions (1/5)
Pin No. 1 27 14 28 2 29 3 61 15 45 16 46 4 30 31 62 5 47 17 63 49 32 18 79 6 48 64 7 65 19 33 20 82 50 66 8 67 51 34 9 35 21 52 10 36 22 23 Label CAP_BRK LD_ON ANA_CS OSD_CS VSS MIC_CTL PHY_PD PHY_RST PHY_CNA ANA_PD VMUTE_IN VDDH REWSEL AS VSS DSYSCLK DRWSEL DAS VDDB ADM15 ADM14 ADM13 ADM12 ADM11 ADM10 ADM9 ADM8 VSS ADM7 ADM6 ADM5 ADM4 ADM3 ADM2 ADM1 ADM0 In/Out Out Out Out Out Out Out Out In Out In Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Description Capstan motor brake control Loading motor ON/OFF control Chip select signal to DV_ANA IC3301 Chip select signal to OSD IC1002 GND Power supply control to MIC Power down control to PHY IC3101 Reset output to PHY IC3101 IEEE1394 connection detect (Connect: L) Power down control to DV_ANA IC3301 Video mute input Not used Not used Power supply (REG_3V) Not used Not used Read/write select signal of Bus Address strobe signal of Bus Not used Not used Not used GND Not used Not used Not used Not used Not used Not used Not used Power supply (REG_3V)
GND
2-10
2-11
2-12
2-13
D.PGSOUT D.PGOUT D.PGD.FGPG+ D.FGD.FGOUT D.FGSOUT D.VS GND1 D.UIN D.VIN D.WIN D.COM D.SL D.ISET L.REF D.UNREG D.VM NC NC
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
C.ECR C.PCI C.PCV C.VS C.SD C.VCC C.FG+ C.FGC.FGOUT C.FGSOUT C.HU+ C.HUC.HV+ C.HVC.HW+ C.HWC.UNREG C.VM NC NC
10 11 12 13 14 15 16 17 18 19 20
FGND1 D.U D.v NC D.W NC D.GND NC L.FWD FGND2 L.GND L.REV C.GND L.UNREG NC C.U NC C.V NC C.W
2-14
35
24
C.VM
C.F/R
DIRECTION
23
HALL
30 29
C.HU+ C.HU-
HALL
28 27
C.HV+ C.HV-
UPPER/LOWER DIVISION
16
C.U
HALL
26 25
C.HW+ C.HW-
18
C.V
CAP.M 20 43
C.RCC C.W
RIPPLE CANCEL
CAP.M TSD
C.U C.V C.W
13
L.SATURATION PREVENT C.U C.V C.W U.SATURATION PREVENT
C.GND
CAP_REF REG_4.8V
41 40
42
C.CL
DC-DC
44 33 34
C.BRK
39 38
C.U C.V C.W C.EC PW.SAVE
C.PCI C.PCV
C . F G C . F G+
37
C.VM C.MODE
C.VS
32
CAP_FG
C.FGOUT
C.FGSOUT
31
POWER SAVE
69
GND
2-15
VCC
35
74 75
77
D.VM
78
SLOPE 70
D.UIN D.U
D.VIN
71
UPPER/LOWER DIVISION
SELECT LOGIC
D.WIN D.COM
D.V
72 73
START
D.DETECT
D.W
58
DETECT 7
D.U D.V D.W L.SATURATION PREVENT D.U D.V D.W U.SATURATION PREVENT
DRUM.M
D.GND
D.OSC
57
OSC
BRAKE TSD
55
D.PCI
DC-DC 56
D.PCV
52
REG_4.8V
53
68
D.VS
54
D.CL
CURRENT LIMIT
PW.SAVE D.PGSOUT
D.FGSOUT
D.PGOUT
D.FGOUT
D.FGPG+
65 64
66
67
D.PG
D.FG
POWER SAVE
VREG
63
62
61
69
GND
50
DRUM_FG
DRUM_PG
2-16
14
L.REF
59
60
35
76
CONTROL LOGIC
L.FWD
L.FIN
L.RIN
L.REV
12
11 SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 PW_SAVE D.PG.SM D.BRK L.FIN
DATA-LATCH
C.F/R C.MODE
47
CLK
49
DIN
48
CS
69
GND
2-17
2.2.4 CDS AGC AD IC (IC5601) function 1. CDS AGC AD IC (IC5601) pin locations and block diagram
ADCLK SPBLK SPSIG
DVDD
AVDD
VRM2
DVSS 14
AVSS
OBP
CLP
24
23
22
21
20
19
18
17
16
15
13
AVSS AVDD CDSIN TESTY TESTC AVSS AVDD VRB VRM VRT BIAS NC
25 26 27 28 29 30 31 32 33 34 35 36 BIAS Serial I/F Gain Select Output Latch 10bit A/D CDS AGC
OE
NC
12 11 10 9 8 7 6 5 4 3 2 1
NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PBLK
Clamp
37
38
39
40
41
42
43
44
45
46
47
48
AVSS
AVSS
SDATA
DVSS
AVDD
AVDD
Fig. 2-2-7 CDS AGC AD IC (IC5601) pin locations and block diagram
2-20
DVDD
DVSS
SCK
NC
NC
CS
Digital output
(MSB) Not used Digital output enable control Ground for the digital system Power supply for the digital system A/D converter clock input Optical balck clamp pulse input Pre-charge level sample and hold pulse for CDS Level sample and hold pulse for CDS Ground for the analog system Power supply for the analog system Not used Clamp voltage Reference voltage Ground for the analog system Power supply for the analog system CDS input Test signal input - Y Test signal input - C Ground for the analog system Power supply for the analog system Reference voltage Reference voltage Reference voltage Internal bias Not used Ground for the analog system Power supply for the analog system Not used Not used Power supply for the analog system Ground for the analog system Serial interface chip select input Serial clock input Serial data input Power supply for the digital system Ground for the digital system Ground for the digital system
2.2.5 B/W LCD driver IC (IC7001) function (for GR-DVF11U) 1. B/W LCD DRIVE IC (IC7001) pin locations and block diagram
BRIGHTNESS
BL_GND
GAMMA
VIDCH
VIDLC
MVDD
RENO 26
36
35
34
33
32
31
30
29
28
27
25
H_SKIPPING SSTART SMCOMP VDDH SMGND SMOUT VBAT BLACK_LEVEL H_SYNC V_SYNC VHIO_SEL REF_GND
37 38 39 40 41 42 43 44 45 46 47 48
RENE
VIDL
VBG
OK
BL
Video Amp
24 23
HCK HPL V_REF VSS VDD VEE V_COM HODL VPL VCK VIDH PDR
32fh Ramp DC-DC Convertoer 416fh 32fh 1/13 Hsync Timing Generator Vsync PLL DC Restore OSD Level Detect Blkg White Video Adjust Video Amp Sync Separator
22 21 20 19 18 17 16 15 14 13
10
11
12
PLL_FILTER
HODL_SEL
VIDEO_IN
OSD_IN
525/625
SLEEP
SFLTR
A_GND
CLAMP
Fig. 2-2-8 B/W LCD DRIVE IC (IC7001) pin locations and block diagram
2-22
D_GND
A_GND
GAIN