VIDEO TECHNICAL GUIDE

VHS-C VIDEO MOVIE

GR-SXM920U/SXM46EG/SXM760A
(2000 VHS-C CAMCORDER MODELS)

COPYRIGHT 2000 VICTOR COMPANY OF JAPAN, LTD.

July 2000

INDEX
SECTION 1 OUTLINE OF THE PRODUCTS
1.1 OUTLINE OF THE 2000 CAMCORDERS ............................................................................1-1 1.1.1 Table of the 2000 models (NTSC) ..................................................................................1-1 1.1.2 TABLE OF THE 2000 MODELS (PAL, SECAM).............................................................1-2

SECTION 2 EXPLANATION OF THE NEW TECHNOLOGY

2.1 DIGITAL ZOOM METHOD ...................................................................................................2-1 2.1.1 FIELD MEMORY ZOOM (with External VRAM) .............................................................2-1 2.1.2 CCD ZOOM (without External VRAM)............................................................................2-2 2.1.3 CCD ZOOM + SRAM ZOOM (Camera DSP with built-in SRAM) ...................................2-2 2.1.4 LINE HOLD OPERATION IN CCD ZOOM MODE ..........................................................2-3 2.2 DIGTAL IMAGE STABILIZER (DIS)......................................................................................2-4 2.3 INTERPOLATION TYPE DIGITAL TBC (TIME BASE CORRECTOR) ..................................2-5 2.3.1 Correction of jitter within 1 clock.....................................................................................2-5 2.3.2 Correction of jitter unitized by clock................................................................................2-5

SECTION 3 EXPALANATION OF THE ELECTRICAL CIRCUIT

3.1 BASIC BLOCK DIAGRAM....................................................................................................3-1 3.2 CCD IMAGE SENSOR .........................................................................................................3-2 3.2.1 Pixel arrangement..........................................................................................................3-2 3.2.2 CCD ratings ...................................................................................................................3-2 3.2.3 CCD block diagram & pin location..................................................................................3-3 3.2.4 CCD pin functions..........................................................................................................3-3 3.3 EXPLANATION OF THE CLOCK SYSTEM..........................................................................3-4 3.3.1 Clock system block diagram ..........................................................................................3-4 3.4 EXPLANATION OF THE SIGNAL FLOW .............................................................................3-5 3.4.1 Signal flow in recording mode ........................................................................................3-5 3.4.2 Signal flow in playback mode.........................................................................................3-6 3.5 EXPLANATION OF THE DSC SYSTEM...............................................................................3-7 3.5.1 In DSC recording ...........................................................................................................3-7 3.5.2 In DSC playback ............................................................................................................3-8 3.5.3 Picture Navigator ...........................................................................................................3-8 3.6 IC FUNCTIONS....................................................................................................................3-9 3.6.1 CDS / AGC / AD (IC5201: HD49326AF) ........................................................................3-9 3.6.2 TG / V. DRIVER (IC5202: JCY0098) ..............................................................................3-11 3.6.3 CAMERA_DSP (IC4001: JCY0100)...............................................................................3-13 3.6.4 VTR_DSP (IC3001: JCY0130) function..........................................................................3-19 3.6.5 VTR_ASP (IC3101: HA118219A) function .....................................................................3-23 3.6.6 CPU (IC101: UPD703039-013) function.........................................................................3-25 3.6.7 DSC_IF (IC8001: JCY0076B) function ...........................................................................3-31

INDEX-1

SECTION 1 OUTLINE OF THE PRODUCTS

1.1 OUTLINE OF THE 2000 CAMCORDERS
1. DSP (Digital Signal Processing) of VTR Process 2. Built-in Memory (0.5M bits SRAM) in Camera DSP Improvement picture quality by TBC (Time Base Corrector) High ratio Digital Zoom from the Basic Models Lower power consumption Less number of parts components Color OSD capability 1.1.1 Table of the 2000 models (NTSC)
MODEL GR-AX750U GR-AXM220U GR-AXM225U GR-SX850U GR-SX851U GR-SX950U GR-SXM320U GR-SXM520U GR-SXM525U GR-SXM527U GR-SXM720U GR-SXM920U GR-AX750UC GR-AXM220UC GR-AXM225UC GR-SX850UC GR-SX851UC GR-SXM320UC GR-SXM321UC GR-SXM520UC GR-SXM720UC GR-AX767UM GR-AXM237UM GR-SX867UM GR-SXM337UM GR-SXM737UM GR-SXM937UM *CC6163 CC6263 CC6363 CC6373 CC6383 CC6393 TAPE FORMAT VHS-C VHS-C VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C VHS-C VHS-C VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C VHS-C VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C VHS-C VHS-C VHS-C VHS-C VHS-C VHS-C VIDEO OUT SELECT CCD 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K 1/4" 270K VF B/W B/W B/W COLOR COLOR COLOR B/W B/W COLOR B/W COLOR COLOR B/W B/W B/W COLOR COLOR B/W B/W B/W COLOR B/W B/W COLOR B/W B/W COLOR B/W COLOR B/W B/W COLOR COLOR LDC MONI 2.5 INCH 2.5 INCH 2.5 INCH 3 INCH 2.5 INCH 3 INCH 3 INCH 3 INCH 2.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 3 INCH 3 INCH 2.5 INCH 2.5 INCH 3 INCH 3 INCH 2.5 INCH 2.5 INCH 3 INCH 3 INCH SNAP SHOT DIGITAL PB EFFECT ZOOM w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. 300 X 300 X 300 X 300 X 300 X 300 X 400 X 400 X 400 X 400 X 400 X 400 X 300 X 300 X 300 X 300 X 300 X 400 X 400 X 400 X 400 X 450 X 450 X 450 X 450 X 450 X 450 X 50 X 200 X 200 X 200 X 300 X 400 X RCU OPTION OPTION RM-V715U OPTION RM-V715U RM-V715U RM-V715U RM-V715U RM-V715U OPTION OPTION OPTION RM-V715U RM-V715U RM-V715U RM-V715U RM-V715U RM-V715U RM-V715U VIDEO LIGHT YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES DSC DSC DSC DSC

Note: Asterisked models are minor change of 1999 models.

Table 1-1-1 Table of the 2000 models (NTSC models)

1-1

1.1.2 TABLE OF THE 2000 MODELS (PAL, SECAM)

MODEL GR-FX11EG GR-FXM16EG GR-FXM161EG GR-SX21EG GR-SX41EG GR-SXM26EG GR-SXM46EG *GR-FX11EK *GR-FX101EK *GR-FXM16EK GR-SXM26EK *GR-FX102S *GR-FXM106S GR-SX210A GR-SXM260A GR-SXM460A GR-SXM760A GR-SX210A-S GR-SXM260A-S GR-SXM460A-S GR-SXM760A-S GR-SX21EA GR-SXM26EA GR-SXM46EA GR-SX51A GR-SXM61A GR-SXM71A GR-SXM81A GR-SXM91A GR-SX52ED GR-SXM62ED GR-SXM72ED GR-SXM75ED GR-SXM82ED GR-SXM92ED VMS081 VMS091L TAPE FORMAT VHS-C VHS-C VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C VHS-C VHS-C VHS-C S-VHS-C VHS-C VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C S-VHS-C VIDEO OUT SELECT PAL/SECAM PAL/SECAM PAL/SECAM PAL/SECAM PAL/SECAM PAL/SECAM PAL/SECAM CCD 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 470K 1/4" 470K 1/4" 470K 1/4" 470K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 470K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 470K 1/4" 470K 1/4" 470K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 470K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 320K 1/4" 470K 1/4" 470K 1/4" 470K VF B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W B/W COLOR COLOR B/W B/W B/W COLOR COLOR COLOR B/W B/W LDC MONI 2.5 INCH 2.5 INCH 2.5 INCH 3 INCH 2.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 3 INCH 3 INCH 2.5 INCH 3 INCH 3 INCH 2.5 INCH 3 INCH 2.5 INCH 3 INCH 2.5 INCH 3 INCH 2.5 INCH 3 INCH 2.5 INCH 2.5 INCH 3 INCH 2.5 INCH SNAP SHOT DIGITAL PB EFFECT ZOOM w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. w/Field Mem. 50 X 50 X 160 X 50 X 160 X 50 X 160 X 50 X 50 X 50 X 50X 50 X 50 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 50 X 50 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 50 X 50 X RCU OPTION OPTION OPTION OPTION RM-V715U OPTION RM-V715U OPTION OPTION OPTION OPTION OPTION OPTION OPTION OPTION RM-V716U RM-V716U OPTION OPTION RM-V716U RM-V716U OPTION OPTION RM-V716U RM-V716U RM-V715U RM-V715U RM-V716U RM-V716U RM-V716U RM-V715U RM-V715U RM-V705U RM-V716U RM-V716U RCS081 RCS081 VIDEO LIGHT YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES DSC DSC DSC -

Note: Asterisked models are minor change of 1999 models.

Table 1-1-2 Table of the 2000 models (PAL/SECAM models)

1-2

SECTION 2 EXPLANATION OF THE NEW TECHNOLOGY

2.1 DIGITAL ZOOM METHOD
The digital zoom system incorporated in the digital camera currently in use is roughly classified into two; one is the Field Memory Zoom system incorporated in the models having the VRAM and the other is the CCD Zoom system incorporated in the models having no VRAM. Under those circumstances, a new zoom system is developed for the 2000 model that has no VRAM. The new zoom system is a joint system of the field memory zoom system and CCD zoom system. For introducing the new zoom system into the 2000 model having no VRAM, an SRAM of small storage capacity (0.5M bits) is built in the camera DSP IC. As a result, the new digital zoom system of high zoom ratio can be introduced into the basic types of the 2000 model without VRAM.
16x LENS CDS/AGC A/D NEW CAMERA_DSP 0.5Mb SRAM

CCD

VTR

Drive

TG V.DRV

Control

CPU

Control

2.8Mb VRAM
*Only for the model with VRAM

Fig. 2-1-1 Camera block of the 2000 Models 2.1.1 FIELD MEMORY ZOOM (with External VRAM) This system saves all of image data read out of the CCD in the field memory (VRAM) once, and reads a part of the saved image data out of the VRAM by addressing the readout area and interpolation for practicing digital zoom. Since this system always reads all of image data out of the CCD, it doesn't decrease the amount of image data for automatic control and camera shake compensation. In other words, this system realizes high precision compensation of image data even at the high zoom ratio, however, the VRAM raises the production cost of the model incorporating this zoom system.

CCD OUTPUT

FIELD MEMORY MEMORY SIZE: 2.8Mbits

Fig. 2-1-2 Field memory zoom system

2-1

2.1.2 CCD ZOOM (without External VRAM) Since this system effects digital zoom by cutout of the CCD output image data, it is called the CCD zoom system. For vertical zoom effect, only the image data in a certain CCD area corresponding to the zoom ratio is read out and the read out data area is expanded with line hold and interpolation operation to be used as the digital zoom-in image. For horizontal zoom effect, the line memory is used. This CCD zoom system realizes the same digital zoom performance without field memory as the field memory system, however, it has a weak point that the image compensation performance declines as the zoom ratio is set high, because the quantity of image data to be used for automatic control and camera shake compensation decreases with rise of the zoom ratio. Therefore, the maximum zoom ratio of the 1999 model is set at 50 in total (optical zoom ratio: 16, digital zoom ratio: 3.125, total: 16 3.125 = 50).

CCD OUTPUT LINE HOLD

LINE MEMORY

Fig. 2-1-3 CCD zoom system 2.1.3 CCD ZOOM + SRAM ZOOM (Camera DSP with built-in SRAM) This system is a joint system of the field memory zoom system and CCD zoom system. This system uses the CCD zoom system up to the digital zoom ratio of 2, and it uses the SRAM built-in the Camera DSP for digital zoom of higher zoom ratio. Since this system always uses image data in the vertically and horizontally halved area of the CCD, the built-in SRAM of small storage capacity performs the duties of the memory. The merit of this system is to realize high zoom ratio without declining the automatic control performance, because quantity of CCD image data does not decrease at a high zoom ratio owing to the maximum 2 zoom ratio of the CCD zoom function. Therefore, the 2000 model realizes the surprising high zoom ratio such as 200 or 300 even for the type without field memory. Moreover, this system lowers the production cost as compared with the field memory zoom system, because the required storage capacity of the SRAM is a quarter of the VRAM used for the field memory zoom system.

1/2

1/2

CCD OUTPUT

built-in SRAM MEMORY SIZE: 0.5Mbits

Fig. 2-1-4 CCD zoom + SRAM zoom system The memory size of the field memory is 2.8M bits for matching the high resolution CCD (number of horizontal pixels: 768). On the other hand, the memory size of the SRAM built in the Camera DSP is 0.5M bits on the condition to use the standard CCD (number of horizontal pixels: 510) for the 2000 model without VRAM (field memory). The 2000 model having the field memory does not use the built-in SRAM, however, this SRAM is used as the memory for TBC in playback because it also serves as the memory for TBC in the 2000 model.

2-2

MEMORY SIZE FIELD MEMORY ZOOM CCD ZOOM CCD ZOOM + SRAM ZOOM 2.8M bits 768(H) 304(V) 12bit Non 0.5M bits 288(H) 150(V) 12bit

INFORMATION for AUTO and DIS Excellent There is little information as zoom ratio goes high Good

Table. 2-1-1 Characteristics of each zoom system 2.1.4 LINE HOLD OPERATION IN CCD ZOOM MODE In the CCD Zoom mode, LINE HOLD pulse LHFO corresponding to the zoom ratio is input from the Camera DSP to the TG+V DRIVER IC through the VGAT terminal for controlling the V1, V2, V3, V4 and ID pulses. When the VGAT is held at H level, line shift operation of the V1, V2, V3 and V4 pulses is suspended while the polarity of the ID pulse is held. Since CCD output is acquired by the V1, V2, V3 and V4 pulses, no CCD output is acquired when those pulses are held suspended from output by the VGAT operation as shown in the following timing chart.

CCD

CCD_OUT

CDS/AGC A/D TG V.DRV

VGAT ID AHD,AVD LHFO

CAMERA DSP

VTR

V1,V2,V3,V4

Fig. 2-1-5 Line holding control

AHD

VGAT

V3 Stop the Line Shift Operation ID CCD OUT n n+1 n+2 n+3

Note: "n" is vertical line number of CCD output

Fig. 2-1-6 Line hold timing chart

2-3

2.2 DIGITAL IMAGE STABILIZER (DIS)

The camera shake compensation method varies depending on the digital zoom system. The 2000 model having the field memory compensates camera shake by the memory area cutout control as usual.
CCD Field Memory Screen Output

Digital Zoom

Movement Vector Detection

Memory Partition Position Control

Fig. 2-2-1 DIS method using Field Memory The 2000 model having no field memory compensates camera shake by the CCD area cutout control when the total zoom ratio is 32 (optical: 16, digital: 2) or lower, while it uses the memory area cutout control method when the total zoom ratio is higher than 32.
CCD Built-in SRAM Screen Output

Movement Vector Detection Zoom ratio: ~ x32 CCD Partition Position Control

Zoom ratio: x32 ~ Memory Partition Position Control

Fig. 2-2-2 DIS method using built-in SRAM

2-4

2.3 INTERPOLATION TYPE DIGITAL TBC (TIME BASE CORRECTOR)

For jitter correction, jitter component is classified into two types, namely, one is the jitter component within 1 clock and the other is that unitized by clock, and the two types of jitter components are respectively controlled by the TBC. This TBC system detects the jitter component within 1 clock by arithmetic operation and corrects the jitter by interpolation operation according to the computation result, therefore, this TBC system is called the interpolation type TBC system.
Playback signal input Jitter Correction

Memory

Output

Jitter Detection
Write and read clock are used in common.

Synchronized reference clock generator

Jitter correction within 1 clock

Jitter correction per clock unit

Fig. 2-3-1 TBC system block diagram 2.3.1 Correction of jitter within 1 clock The jitter component within 1 clock "tj" is detected by the rise-up portion of the sync pulse of the playback signal. On the assumption that the leading edge (rise-up portion) of the sync pulse shapes nearly a straight line in the microperiod dt of the sampling period, relation between the tj and leading edge and that between the dt and leading edge are in the similar triangles in form. From the similarity in the said relations, the jitter component tj can be found by computation. Using the resultant value tj as the correction factor, the jitter correction circuit in the pre-stage of the memory controls the phase by interpolation.
sync 1 clock (a) Original signal Sample point: Y1 (b) Signal including Jitter Magnification figure of start up portion (c) Jitter correction within 1 clock Threshold level: Vth

Y1-Y0 (d) Jitter correction per clock unit Sample point: Y0 Vth-Y0

tj

dt

Fig. 2-3-2 Principle of Jitter correction

Fig. 2-3-3 Correction of jitter within 1 clock

2.3.2 Correction of jitter unitized by clock After correction of jitter within 1 clock is complete in the first stage, jitter unitized by clock is corrected by control of write and read operations of the memory in the second stage. Though the common clock is used for write and read of data in/from the memory, data write is executed in time with the sync pulse of the playback signal and data read is performed in time with the reference clock for correcting the jitter.
2-5

SECTION 3 EXPLANATION OF THE ELECTRICAL CIRCUIT

3.1 BASIC BLOCK DIAGRAM
0 2 CCD 0 1 MAIN
V_PB_C

0 7 MONITOR

IC5201
CDS/AGC A/D
SO3 AD(10)

IC4002
FIELD MEMORY
TMY(8) TMC(4) FMY(8) FMC(4)

LCD_R-Y LCD_B-Y LCD_Y SI3

IC7601 LCD DRIVER

R G B

OPTICAL BLOCK

CCD

CCD_OUT

MONI LCD PANEL

IC7602
DA_RY DA_BY X3001
28.63636MHz

SO3

EEP ROM

DRIVE+,- HE_OUT+,- HE_IN+,-

H1, H2, RG V1,V2,V3,V4,SUB

IC5202
TG V.DRIVER
SO3

DA_Y2 VD, HD LHFO

IC4001
CAMERA_DSP

DYO(8),DCO(4) DYI(8),DCI(4) DA_Y

IC3001
VTR_DSP

1 0 VF
IC7400 LCD DRIVER
V_REC_C V_REC_F R G B

FOCUS (4)

ZOOM (4)

BUS(16)

SO3

H_GAIN H_OFFSET IRIS_O/C IRIS PWM HALL_AD

DSY(8), DSC(4)

IC4201 IC4202
IRIS DRIVER & HALL AMP

DA_C

VF LCD PANEL

SO3

IC4003

ON SCREEN

IC2401

AMP
V_PB_C V_PB_F PA_SIG

SP

IC4501
OSD_DATA CAM_Y

IC3501
V_PB_CU
V_CH2_S V_CH2_F V_CH4_S V_CH4_F V_CH1_S V_CH1_F V_CH3_S V_CH3_F

VIDEO HEAD

FOCUS DRIVER & ZOOM DRIVER

SO3

AD(16)

CAM_C Y_GCTL

IC3101
VTR_ASP

V_REC_FM V_REC_CU

IC105 IC101
CPU EVR DAC
SO3

C_GCTL FREQ_ADJ

REC AMP & PB AMP

ENV_ADJ

SPK_VOL

IC3901

FE_F FE_S

FLY.E HEAD

JLIP

TX GND

JLIP_TX Q110

TXD AL_SO AL_SI SO2 SO3

MIC_HOT

J503

SC_OUT

SY_OUT

AO_SIG

RX

JLIP_RX

D107

RXD

V_OUT

SO3

A/C HEAD
AH_S AH_F AE_+ AE_CTL_HED_+ CTL_HED_REG_4.8V CTL_ERS_-

SI2

SI3

A_BIAS

BIAS
IC2001 Q2001

GND J501

IC8006
PC_TX PC_RX TXD RXD

IC104 E 2P R O M

Q2072

DSC

TX RX

IC8002
32D(16)
J504

IC107 RTC
32A(19)

CTL_OUT REC_CTL

CTL AMP
IC1201

Q103

V_OUT

V_OUT

M32_R/D CPU

32A(25)

REG_4.8V

IC8001
DSC_IF

32kHz X102

CTL_ERASE

C_COIL_U C_COIL_V C_COIL_W

CAP MOTOR

A_OUT
J505

A_OUT

M
16Mb FLASH

IC1601
DRUM_PWR CAP_PWR

Y_OUT C_OUT

S_OUT

IC8003
DRUM_REF CAP_REF

D_COIL_U D_COIL_V D_COIL_W

DRUM MOTOR

MDA

M
LOAD MOTOR

MIC UNIT

SO3

INT_MIC / R

LOAD_FWD LOAD_REV

M13C83

Fig. 3-1-1 Basic overall block diagram

3-1

3.2 CCD IMAGE SENSOR

3.2.1 Pixel arrangement

OPTICAL BLACK

/4

b d

c e

Fig. 3-2-1 pixel arrangement 3.2.2 CCD ratings

NTSC Item 270K Transfer system Optical format Effective pixels Overall pixels Chip size Unit cell size Interline transfer 1/4 inch 510 (H) 492 (V) Approx. 250000 pixels 537 (H) 505 (V) Approx. 270000 pixels 4.47mm (H) 3.80mm (V) 7.15 m (H) 5.55 m (V) Complementary color mosaic filter (Mg, G, Cy, Ye) Variable electronic shutter 320K Interline transfer 1/4 inch 500 (H) 582 (V) Approx. 290000 pixels 537 (H) 597 (V) Approx. 320000 pixels 4.47mm (H) 3.80mm (V) 7.3 m (H) 4.7 m (V) Complementary color mosaic filter (Mg, G, Cy, Ye) Variable electronic shutter 470K Interline transfer 1/4 inch 752 (H) 582 (V) Approx. 440000 pixels 795 (H) 596 (V) Approx. 470000 pixels 4.47mm (H) 3.80mm (V) 4.85 m (H) 4.65 m (V) Complementary color mosaic filter (Mg, G, Cy, Ye) Variable electronic shutter PAL

Color filter system

Added functions

Table 3-2-1 CCD ratings

3-2

in

ch

a b c d e f g h

NTSC 270K 2 510 25 537 12 492 1 505

PAL 320K 7 500 30 537 14 582 1 597 470K 3 752 40 795 12 582 2 596

3.2.3 CCD block diagram & pin location

VOUT GND NC V1 V2 V3 V4
1
Ye G Ye Mg Ye G

Cy Mg Cy G Cy Mg

Ye G Ye Mg Ye G

Cy Mg Cy G Cy Mg

Vertical-Register

Horizontal-Register

8 9 10 11 12 13 14

Photo Sensor

VDD

H1

SUB

GND

Fig. 3-2-2 CCD block diagram & pin location 3.2.4 CCD pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V4 V3 V2 V1 NC GND V OUT VDD GND SUB VL RG H1 H2 Label In/Out In In In In Out In In In In REF. Verticall transfer clock (4th phase) input Verticall transfer clock (3rd phase) input Verticall transfer clock (2nd phase) input Verticall transfer clock (1st phase) input Not used GND Video output Power supply GND Substrate (Electrical shutter pulse input) Transistor bias for protect Riset gate clock Horizontal transfer clock (1st phase) input Horizontal transfer clock (2nd phase) input

Table 3-2-2 CCD pin functions

3-3

RG

H2

VL

3.3 EXPLANATION OF THE CLOCK SYSTEM

3.3.1 Clock system block diagram
IC5201
PB_C PGA A/D ADCLK 270k/320k CCD: 9MHz 470k CCD: 14MHz PB_C: 14MHz CDS_CLK F.CNV 9M to14M

IC4001 CAM_DSP

IC3001 VTR_DSP

CCD

CDS

SHD

SHP

XSHP XSHD driver XRS RG

IC5202

TG + V.DRIVER
AVD

CLK GEN

CLKI

CAM_CLK

Timing Generator RG driver

AHD

SSG

CLK 28MHz

H1 H2 V1 V2 V3 V4

H driver

SW CDS_CLK AD1_CK REC PB 14MHz

V driver

SW

CAM_ADCK 270k/320k CCD: 9MHz 470k CCD: 14MHz X3001 TG_CLK

SUB

1/3 SUB driver

1/2

CLK_GEN. 2FSC To: VTR_ASP

CLK 28MHz

X'tal NTSC:28.63636MHz PAL: 28.375MHz

Fig. 3-3-1 Clock system block diagram 3.3.2 Explanation of the clock system Under the circumstances that the clock frequency for the camera block varies depending on the type of the CCD incorporated in the camera, the clock system of this model can deal with different clock frequencies. For example, the horizontal drive frequency for the 270,000-pixel CCD of the NTSC model and 320,000-pixel CCD of the PAL model is 9 MHz, and the sampling frequency of the A-D converter is 9 MHz also. On the other hand, those frequencies for the 470,000-pixel CCD of the PAL model is 14 MHz in common. The CCD drive pulse and CDS sampling pulse are generated by the IC5202 (TG + V. DRIVER), namely, the 28 MHz pulse oscillated by the X3001 X'tal in the periphery of the IC3001 (VTR DSP) is input into the IC5202, which divides the 28 MHz pulse into 9 MHz (nearly triparted) pulse and 14 MHz (halved) pulse to use the two kinds of pulses by switching them by the CCD. Based on these reference clocks and horizontal and vertical sync signals (AHD, AVD) output from the IC4001 (CAMERA DSP), a variety of pulses are produced in the IC5202. The 9 MHz or 14 MHz clock selected in the IC5202 is output as CAM ADCK, which is then supplied to the IC5201 through the switch of the IC3001 (VTR DSP) to be used as the sampling clock of the A-D converter in the IC5201. This A-D converter also serves as the A-D converter for the PB C signal in playback with the 14 MHz clock produced in the VTR DSP. The FCNV block in the IC4001 converts the 9 MHz CCD image data into 14 MHz image data, therefore, image data that is transferred from the CAMERA DSP to the VTR DSP is always 14 MHz image data.

3-4

3.4 EXPLANATION OF THE SIGNAL FLOW

3.4.1 Signal flow in recording mode
IC4002 FIELD MEMORY

CVF / LCD MONI

TMY(8) TMC(4)

FMY(8) FMC(4)

R-Y

IC4001 CAM_DSP

B-Y

IC3001 VTR_DSP

CCD

CPU I/F

FMC/EIS

FCNV
9M to14M

D/A

D/A

D/A

Sync ADD

N.L Emph Sub Emph

Main Emph W/D Clip

FM MOD

D/A

AUTO
CDS AGC AD(10)

SRAM

CVF D I/F
DYO(8) DCO(4) Burst ADD Chroma Encoder Burst Emph

D/A

SELECTOR Y/C
WIPE OSD MIX TEST SG

A/D
IC5201 PB C

VTR I/F TBC

DYI(8) DCI(4)

ENC
NTSC/PAL /SECAM

Burst De-Emph

C-COMB

Decoder

ACC AMP

D I/F
N.L De-Emph Sub De-Emph Main De-Emph

SSG

DSC I/F

OSD I/F

D/A
C

D/A
Y

FM DEMO

A/D

DSY(8), DSC(4)

PB FM

OSD

SECAM
PB C

REC C REC FM

IC3101 VTR_ASP 6dB Clamp AD LPF G.EQ DA LPF DA LPF

DSC
SECAM 2M LPF C Out Buff GCTL BPF BLK FM AGC V Out Buff Buff. TRAP REC FM 4.2M Trap SECA M GCTL LPF TRAP REC C IC3501 P.EQ EQ HPF

VIDEO

Y Out S-OUT

PRE / REC
PB FM+C

HEAD

Buff

Fig. 3-4-1 Signal flow in recording mode In recording video signal output from the CCD is input into the CDS/AGC which eliminates noise components from the signal and adjusts the signal level, and then the signal is supplied to the A-D converter to be converted from analog signal into 10-bit digital signal before it is supplied to the CAMERA DSP. In the CAMERA DSP the Y/C separator separates the signal into Y signal and color difference signal, which are supplied to both the FMC/EIS block and the AUTO block in the next stage. The signals supplied to the AUTO block are used as factors to control the AE, AWB and AF. The FMC controls data write and read in/from the field memory in the model incorporating it or the SRAM (0.5M bits) built in the model without field memory. The EIS detects movement vector for compensation of camera shake. The FCNV in the next stage converts clock frequency of the video signal. That is to say, the frequency of the CCD data readout clock and the sampling frequency of the A-D converter are 9 MHz for the NTSC and PAL models incorporating the ordinary resolution CCD, but the FCNV converts the 9 MHz frequency into 14 MHz frequency for the PAL model incorporating the high resolution CCD, in which model the FCNV outputs the 14 MHz frequency as the CCD data read out clock and sampling frequency of the A-D converter. In the standard video tape recording mode, the video signals are supplied to the VTR DSP through the VTR I/F. The VTR I/F outputs image data whose digital component ratio is 4:1:1 to the VTR DSP in the following way. The Y signal is output from the VTR I/F by every 8 bits in the dot sequential system, while the Cr and Cb signals are output in order of the high-order 4 bits of Cr, low-order 4 bits of Cr, high-order 4 bits of Cb, low-order 4 bits of Cb, and repetition, namely, the Cr and Cb data are respectively divided into the highorder 4 bits and low-order 4 bits for output. At the same time, these signals are output to the VIDEO OUT terminal and CVF/MONI LCD of the E-E system. In the CAMERA DSP of this model, there are five D-A converters in total. In the model having the DSC function, image data is supplied to the DSC block in the
3-5

DSC recording mode. The 2000 model incorporates the newly developed VTR DSP. Differently from the previous models in which analog signals are processed for VHS recording/playback by the deck section, the 2000 model performs signal processing including frequency modulation for VHS recording/playback in the digital system. Therefore, image data from the CAMERA DSP is directly input in the memory as it is of the digital signal. Since other signal processing in recording is the same as usual, the REC FM and REC C signals output from the D-A converter in the final stage are recorded as analog signals on the tape through the VTR ASP and PRE/REC IC. 3.4.2 Signal flow in playback mode
IC4002 FIELD MEMORY

CVF / LCD MONI

TMY(8) TMC(4)

FMY(8) FMC(4)

R-Y

IC4001 CAM_DSP

B-Y

IC3001 VTR_DSP

CCD

CPU I/F

FMC/EIS

FCNV
9M to14M

D/A

D/A

D/A

Sync ADD

N.L Emph Sub Emph

Main Emph W/D Clip

FM MOD

D/A

AUTO
CDS AGC AD(10)

SRAM

CVF D I/F
Burst ADD Chroma Encoder Burst Emph

D/A

SELECTOR Y/C
WIPE OSD MIX TEST SG

DYO(8) DCO(4)

A/D
IC5201 PB C

VTR I/F TBC

DYI(8) DCI(4)

ENC
NTSC/PAL /SECAM

Burst De-Emph

C-COMB

Decoder

ACC AMP

D I/F
N.L De-Emph Sub De-Emph Main De-Emph

SSG

DSC I/F

OSD I/F

D/A
C

D/A
Y

FM DEMO

A/D

DSY(8), DSC(4)

PB FM

OSD

SECAM
PB C

REC C REC FM

IC3101 VTR_ASP 6dB Clamp AD LPF G.EQ DA LPF DA LPF

DSC
SECAM 2M LPF C Out Buff GCTL BPF BLK FM AGC V Out Buff Buff. TRAP REC FM 4.2M Trap SECA M GCTL LPF TRAP REC C IC3501 P.EQ EQ HPF

VIDEO

Y Out S-OUT

PRE / REC
PB FM+C

HEAD

Buff

Fig. 3-4-2 Signal flow in playback mode In playback, the PB FM and PB C signals are output from the PRE/REC IC as they are mixed with each other, and the mixed signal is separated into the PB FM and PB C signals by the VTR ASP block. The PB FM signal of analog signal is converted into digital signal by the A-D converter in the VTR DSP block, and then processed for VHS playback. For A-D conversion of the PB C signal, the A-D converter for the CCD is used, because this A-D converter is not used in the playback mode. Then, the PB C signal is supplied to the CAMERA DSP block, which performs nothing for the signal and outputs the signal to the VTR DSP block to be processed for playback. The processed PB C signal is again supplied to the CAMERA DSP together with the Y signal. In the CAMERA DSP the playback signal first undergoes the time base control (TBC). The built-in SRAM serves as the memory for the TBC. The model incorporating the field memory enables the user to have a digital effect on the playback picture. The playback signals are finally output to the CVF/MONI LCD and VIDEO OUT terminal through the respective D-A converters. Since the Encoder of the video output block is consistent with the NTSC, PAL and SECAM systems, the PAL model shipped for the Europe is capable of outputting PAL signal in the SECAM system.
3-6

3.5 EXPLANATION OF THE DSC SYSTEM

The DSC block is mainly composed of the DSC CPU (IC8002: M32R/D), DSC I/F (IC8001: JCY0076B) and 16-Mbit Flash Memory (IC8003). The other blocks are common to the model without the DSC function. The DSC block is configured to save the Y and C signals produced by the CAMERA DSP (IC4001: JCY0100) in the flash memory. Differently from the general one-chip CPU, the DSC CPU (IC8002) has neither built-in programmable ROM nor built-in interface of the peripheral circuit but it incorporates a large capacity (8M bits) DRAM that is the most suitable for fast image processing with application software. The Flash memory secures the program area to be executed by the DRAM and JPEG file storage area separately in it. When the camera is turned on, the program stored in the flash memory is executed first and then the DSC control program is copied down in the DRAM. After the program is completely copied, the execution address is shifted to the DRAM for starting actual processing. The DSC I/F (IC8001) of the peripheral circuit of the DSC CPU (IC8002) is controlled so that it serves as the interface for external communication and image data input. The DSC CPU (IC8002) operates according to the command from the MAIN CPU (IC101).
VRAM VF/MONI AV_OUT

CCD

CDS/AGC A/D

CAMERA_DSP (JCY0100) MAIN CPU

VTR

DSC BLOCK FLASH MEM. PROGRAM DATA

M32 R/D Parallel Bus

YUV 4:1:1 Y 8-bit C 4-bit

AVD, AHD FLD, VCLK

DSC_I/F (JCY0076B)

3-Line Serial Chip Select

DSC_CPU (M32_R/D)

Image processing with software in DRAM

File Transfer

DRAM

DMA Transfer

JPEG

File system

Fig. 3-5-1 DSC System configuration 3.5.1 In DSC recording The CCD output is first supplied to the CDS/AGC A-D (IC5201) block, in which the CDS circuit eliminates noise components from the CCD output signal, the AGC circuit compensates the CCD sensitivity, and the A-D converter digitizes the analog input signal. The resulting digital signal is input into the CAMERA DSP (IC4001) block, which processes the digital signal to produce Y and color difference signal whose component ratio is 4:1:1 so that it outputs Y signal by 8-bit unit and Cr and Cb signals by 4-bit unit each to the DSC block. Each time the user presses the shutter release button, the MAIN CPU (IC101) outputs a command to the DSC CPU (IC8002). Following the command the DSC CPU transmits the Y and C signals by line to the built-in DRAM through the DMA (Direct Memory Access) circuit of the DSC I/F (IC8001) to arrange image data for 1 field in the DRAM. The image data saved in the DRAM is compressed by the JPEG system and recorded in the flash memory as an image file. Number of recordable pictures is 30 in the fine picture mode or 60 in the standard mode.

3-7

3.5.2 In DSC playback According to the command output from the MAIN CPU (IC101), a JPEG file is read out of the flash memory and it is written in the DRAM of the DSC CPU (IC8002) to be expanded in the JPEG format by processing of a software. The resultingly produced Y and C data are transmitted line by line from the DSC I/F (IC8001) to the CAMERA DSP (IC4001) through the DMA circuit. Differently from the recording mode, the Y and C signals are repeatedly output in every vertical period (VD) to be converted into analog TV signal. In the CAMERA DSP (IC4001), the digital input signal is converted into analog signal to be output to the LCD monitor, VF and AV OUT terminal. In recording, the conventional video recording section fills the role of YC data preparation by its hardware, while the DSC block compresses the prepared data in the JPEG format with a software as explained previously. In playback, the DSC block functions to make a YC data from a JPEG file with a software, while the conventional video playback section converts the YC data into analog TV signal by its hardware. As mentioned above the new model makes the best use of the conventional videotaping hardware, therefore it additionally incorporates the DSC function in the compact body. 3.5.3 Picture Navigator The Picture Navigator is a software to transfer data on still pictures saved in the flash memory built in the digital video camera to a personal computer and vice versa. Besides the said function, the Picture Navigator can be used to delete saved data on still pictures from the flash memory and to look through still pictures saved in the flash memory. The Picture Navigator needs the RS-232C interface cable for connection and requires to use the image transfer protocol "IrTran-P" of the IrDA (Infrared Data Association) standard as the communication protocol. The Picture Navigator expands the transferred image data in the JPEG format once to resize it into the VGA size (640 480 dots), and then it again compresses the data in the component ratio of 4:2:0 to save it in the memory of a personal computer as a JPEG-compressed image file.
DSC BLOCK FLASH MEM. PROGRAM DATA
M32 R/D Parallel Bus

PC

DSC_I/F (JCY0076B)

UART RX, TX, GND

RS232C

DSC_CPU (M32_R/D)

DRAM

DMA Transfer

File Transfer

JPEG

File system

Fig. 3-5-2 Connection with Personal Computer

3-8

3.6 IC FUNCTIONS
3.6.1 CDS / AGC / AD (IC5201: HD49326AF) 1. CDS/AGC/AD (IC5201) block diagram & pin location
BLKSH BLKFB ADCIN CDSIN 26 AVDD AVSS BIAS VRM

VRB

VRT

NC

36

35

34

33

32

31

30

29

28

27

25

AVSS AVDD NC AVSS AVDD OEB CS SCK SDATA DVDD DVSS DVSS

37 38 39 40 41 42 43 44 45 46 47 48 Output Latch 10bit ADC Serial Interface CDS Bias DC offset compensation

NC

24 23 22 21 20 19 18 17 16 15 14 13

NC AVDD AVSS OADSW PBLK SPSIG SPBLK OBP ADCLK DVDD DVSS NC

Timing Gen. PGA

10

11

12

NC

Fig. 3-6-1 CDS/AGC/AD (IC5201) block diagram & pin location

3-9

NC

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

2. CDS/AGC/AD (IC5201) pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NC NC DVSS DVDD ADCLK OBP SPBLK SPSIG PBLK OADSW AVSS AVDD NC NC CDSIN ADCIN BLKSH BLKFB AVSS AVDD VRT VRB VRM BIAS NC AVSS AVDD NC AVSS AVDD OEB CS SCK SDATA DVDD DVSS DVSS In/Out Not used (LSB) Description

Out

Digital output (To CAMERA_DSP: IC4001)

In In In In In In In In In In In In -

(MSB) Not used Not used Ground Power supply (+3.0V) Clock input for ADC conversion Optical black pulse input Black level sampling clock input Signal level sampling clock input Pre-blanking input Enable input for OADCLK Ground Power supply (+3.0V) Not used Not used CDS input ADC input Black level sample and hold terminal Black level feedback terminal Ground Power supply (+3.0V) Reference voltage 3 Reference voltage 2 Reference voltage 1 Internal bias Not used Ground Power supply Not used Ground Power supply (+3.0V) L: fixed Serial interface control input (From CPU: IC101) Serial clock control input (From CPU: IC101) Serial data control input (From CPU: IC101) Power supply (+3.0V) Ground Ground

Table 3-6-1 CDS/AGC/AD (IC5201) pin functions

3-10

3.6.2 TG / V. DRIVER (IC5202: JCY0098) 1. TG / V. driver (IC5202) block diagram & pin location
SUB NC NC NC 26 NC 25 VH VH 27

VL

V3

V1

V4 29

36

35

34

33

32

31

30

28

NC NC SSK SSI SEN RST VSS4 VDD5 VGAT DSGAT AHD VHD

37 38
V driver

V2

24 23 22
Mode Set Serial/ Parallel SUB driver H driver

NC VSS4 H2 H1 VDD4 VDD3 RG NC XSHD XSHP VSS3 VDD2

39 40 41 42 43 44 45
VRST RST D Timing Generator XSHP XSHD driver XRS RG driver

21 20 19 18 17 16 15

46 47 48
HRST 1/2

SW

14
1/3 D

13
SW

10

11

12

NC

NC

NC

CKINH

VDD1

Fig. 3-6-2 TG / V. driver (IC5202) block diagram & pin location

3-11

CLDCLK

OBCLP

VSS1

PBLK

NC

CK

ID

2. TG / V. driver (IC5202) pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name CKINH NC ID OBCLP NC PBLK VSS1 CK VDD1 CLDCLK NC NC VDD2 VSS3 XSHP XSHD NC RG VDD3 VDD4 H1 H2 VSS4 NC NC NC VM V2 V4 V1 VH V3 SUB VL NC NC NC NC SSK SSI SEN RST VSS4 VDD5 VGAT DSGAT AHD VHD In/Out In Out Out Out In Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In Description Control input for CCDCKH terminal Not used Vertical direction line decision signal OB clamp pulse Not used Pulse output for signal cleaning of horizontal and vertical blanking Ground IC main clock input (NTSC: 1820fH, PAL: 1816fH) (From CPU: IC101) Power supply Master clock output for 510H (NTSC: (606+2/3) fH / PAL: (605+1/3) fH) Not used Not used Power supply Ground CCD pre-charge level S/H pulse output CCD data level S/H pulse output Not used Reset gate pulse output for CCD Power supply Power supply Clock output for CCD horizontal resistor Clock output for CCD horizontal resistor Ground Not used Not used Not used Ground Clock output for CCD vertical resistor (2 value output) Clock output for CCD vertical resistor (2 value output) Clock output for CCD vertical resistor (3 value output) Power supply 15V system Clock output for CCD vertical resistor (3 value output) Pulse output for CCD electrical shutter Power supply -9V system Not used Not used Not used Not used Clock input for various mode setting of IC's internal Data input for various mode setting of IC's internal Strobe input for various mode setting of IC's internal Reset input for IC internal Ground Power supply Vertical clock dropout control signal input for electrical zoom CCD drive pulse, S/H pulse generation stop control Phase advanced horizontal sync signal input ahead of sync signal Phase advanced vertical sync signal input ahead of sync signal

Table 3-6-2 TG / V. driver (IC5202) pin functions

3-12

3.6.3 CAMERA_DSP (IC4001: JCY0100) The IC4001 is a digital signal processor (DSP) LSI that processes signals of the camcorder by only one chip. Functions of this IC are mentioned below. Y/C signal processing for the line sequential color difference CCD Arithmetic processing for the auto system (AWB, AF, AE) Arithmetic processing for the EIS Field memory control 3-way (NTSC/PAL/SECAM) digital color encoding Hadamard cyclic NR Shutter sound generation (D-A converter is built in) SSG Built-in D-A converter with sync signal adding function for 5-channel video signal VHS interface DSC interface OSD mixture function Memory zoom function Interpolation type TBC 1. CAMERA_DSP (IC4001) block diagram
DSY[0-7] DSC[0-3] VDDSC CLKDSC HDDSC FLDDSC FMWR OMT FMRE IE F M W E MCLK RAE WAE R A D TMY[0-7] W A D TMC[0-3] FMY[0-7] FMC[0-3] HDOSD VDOSD CLKOSD VBLK VR VC1 BLK1 VG VC2 BLK2 VB

SCBLKO

CLR TVSELO LHFSEL[0-1] FSET MEMSEL NOVRAV BUS[0-15] ASTB R W DSTB LBEN UBEN DAO_FF[0-15] E2ABR RE FMC WE FMC FMCTHR KKMEY RST48[0-1] RST84[0-1]

CLKENC1 YO[0-8] CLKFMC CLK14

AVSSV1 AVDDV1 YOUT VREFY IREFY COMPY

YDAC
D/A Convertor

CPU I/F
CPU Interface

DAO_AT[0-15] LHFO DAO_OB[0-15]

EIS/FMC
VRAM Contol Vector Detect SRAM Control FMFC[0-15]

OSD I/F
OSD Interface OSV_V[0-7] VBLKO OSY_1[0-7] O S R _ V [ 0 - 7 ] B L K 1 O OSY_2[0-7] O S R _ V [ 0 - 7 ] B L K 2 O CO[0-7]

CLKENC2 AVDDV2 AVSSV2

LHFO ADIN[0-9]

SLFM[0-15]

CDAC
D/A Convertor

COUT VREFC IREFC COMPC

CLKYCA

CLKYCA

CLK14 SLDS[0-15] DSSL[0-15]

CLKFCV1

CLKFCV2 SLEN[0-15]

CLKENC1

CLKENC2 CLKCVF

ID

Y/C
Y/C signal process ADYC[0-9] SATO RBAW[0-13] YLC[0-9] HCLR VAPA[0-8] GAW[0-10] CLKYCA YCSL[8-15]

DSC I/F
DSC Interface

FCNV
Frequency converter FCSL[0-15]

ENC
NTSC/PAL/SECAM Color encoder

Y2DAC
D/A Convertor

Y2OUT VREFVF IREFVF COMPVF

RBSEL_SELN

CLKCVF CLK14 CLK14 CLKCVF Y2O[0-7] RYO[0-7] RYO[0-7] Color difference signal separation D/A Convertor

RYDAC

RYOUT

PWN BEND AFBEND

AUTO
Auto operation process

SSG2
YCSL[0-15] SSG2

SELCT
SLCV[0-15] Wipe/OSD mix Mix/Signal select SLVH[0-15] CSYNCI CRLKI

CVF

CLKCVF

HDCPU VDCPU FRP FLDCPU HDTG VDTG CLKSSG CLK1 VHSL[0-15] RBSEL_VHS L CLKREC

BYDAC
D/A Convertor

BYOUT

CLKPB

CLKGEN
BUSY Clock generate VFF VREFO

SSG1
SSG1

VTR I/F
VHS Intreface interpolation type TBC

CLKKSH KO[0-7]

AVSSA AVDDA

KASHA
Shutter sound occurrenc

KDAC
D/A Convertor

KOUT VREFLK VREFHK

N R Y B Y I DYI[0-7] D C K I DCI[0-3]

DYO[0-7] N R Y B Y O DCO[0-3] D C K O CBLKO CSYNCO

Fig. 3-6-3 CAMERA_DSP (IC4001) block diagram

3-13

2. CAMERA_DSP (IC4001) pin functions 1/5

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DSTB LBEN VSS UBEN RW ASTB BUSO BUS1 BUS2 VDD2 BUS3 BUS4 BUS5 BUS6 VSS BUS7 BUS8 BUS9 VDD1 BUS10 BUS11 BUS12 BUS13 BUS14 BUS15 VSS VDD1 HDCPU VDCPU FLDCPU FRP PWM AFBEND VDD1 BEND OMT BUSY VSS VPD VFF DSY0 DSY1 Out Out Out Out Out Out Out Out Out In In In/Out Ground (for digital) Power supply (for digital core) Horizontal reference signal for CPU Vertical reference signal for CPU Feild discriminate signal for CPU Frame reference signal PWM signal AF block end signal Power supply (for digital core) Block end signal Enable signal of EIS readout data Busy signal Ground (for digital) TEST Video flipflop signal input Luminance signal I/O for DSC (From/To DSC_IF: IC8001) In/Out CPU bus I/O (From/To CPU: IC101) Power supply (for digital core) In/Out CPU bus I/O (From/To CPU: IC101) Ground (for digital) In/Out CPU bus I/O (From/To CPU: IC101) Power supply (for digital I/O) In/Out CPU bus I/O (From/To CPU: IC101) Name In/Out In In In In In Data strobe Lower byte enable Ground (for digital) Upper byte enable Read/Write select Address strobe Description

Table 3-6-3 CAMERA_DSP (IC4001) pin functions 1/5

3-14

 CAMERA_DSP (IC4001) pin functions 2/5

Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VDD2 DSY2 DSY3 DSY4 DSY5 DSY6 DSY7 VSS DSC0 DSC1 DSC2 DSC3 CLKDSC FLDDSC VDDSC HDDSC SCBLKO VSS VDD2 DCO3 DCO2 DCO1 DCO0 DYO7 DYO6 DYO5 DYO4 DYO3 DYO2 VSS VDD1 DYO1 DYO0 DCKO NRYBYO CSYNCO VDD1 CBLKO DYI0 DYI1 DYI2 DYI3 In Luminance signal input for VHS (From VTR DSC: IC3001) Out Out Out Out Out Ground (for digital) Power supply (for digital core) Luminance signal output for VHS (To VTR DSC: IC3001) Clock output for VHS (To VTR DSC: IC3001) Color difference discriminate signal output Composite sync. signal Power supply (for digital) Composite blanking signal Out Luminance signal output for VHS (To VTR DSC: IC3001) Out Color difference signal output for VHS (To VTR_DSP: IC3001) Out Out Out Out Out Clock output for DSC (To DSC IF: IC8001) Field discriminate signal for DSC (To DSC IF: IC8001) Vertical reference signal for DSC (To DSC IF: IC8001) Horizontal reference signal for DSC (To DSC IF: IC8001) Sub carrier blanking signal Ground (for digital) Power supply (for digital I/O) In/Out Color difference signal I/O for DSC (From/To DSC IF: IC8001) Ground (for digital) In/Out Luminance signal I/O for DSC (From/To DSC IF: IC8001) Name In/Out Power supply (for digital I/O) Description

Table 3-6-3 CAMERA_DSP (IC4001) pin functions 2/5

3-15

 CAMERA_DSP (IC4001) pin functions 3/5

Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VSS VDD1 DYI4 DYI5 DYI6 DYI7 DCI0 DCI1 DCI2 DCI3 NRYBYI VSS VDD2 DCKI FMY0 FMY1 FMY2 FMY3 FMY4 FMY5 FMY6 FMY7 VSS FMC0 FMC1 FMC2 FMC3 TMY0 TMY1 VDD2 TMY2 TMY3 TMY4 TMY5 VSS TMY6 TMY7 TMC0 VDD1 TMC1 TMC2 TMC3 Out Digital color difference signal output for field memory (To FIELD MEMORY: IC4002) Out Out Ground (for digital) Digital luminance signal output for field memory (To FIELD MEMORY: IC4002) Digital color difference signal output for field memory (To FIELD MEMORY: IC4002) Power supply Out Digital luminance signal output for field memory (To FIELD MEMORY: IC4002) Out Digital luminance signal output for field memory (To FIELD MEMORY: IC4002) Power supply (for digital I/O) In Digital color difference signal input for field memory (From FIELD MEMORY: IC4002) Ground (for digital) In Digital luminance signal input for field memory (From FIELD MEMORY: IC4002) In In Clock input for color difference discriminate signal (From VTR DSC: IC3001) Ground (for digital) Power supply (for digital I/O) Clock input for VHS (From VTR DSC: IC3001) In Color difference signal input for VHS (From VTR DSC: IC3001) In Luminance signal input for VHS (From VTR DSC: IC3001) Name In/Out Ground (for digital) Power supply (for digital core) Description

Table 3-6-3 CAMERA_DSP (IC4001) pin functions 3/5

3-16

 CAMERA_DSP (IC4001) pin functions 4/5

Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 MCLK FMWR RAD VSS VDD1 WAD IE FMRE FMWE RAE WAE VDD1 LHFO ADIN9 ADIN8 VSS ADIN7 ADIN6 ADIN5 ADIN4 VDD2 ADIN3 ADIN2 ADIN1 ADIN0 ID CLKI VSS HDTG VDTG VSS VDD2 AVDDV1 VREFY IREFY YOUT AVSSV1 VREFC IREFC COUT RYOUT COMPY In In Out Out Out Out Out Line discriminate signal (From TG+V_DRIVER: IC5202) Clock input (From CPU: IC101) Ground (for digital) Horizontal reference signal for TG Vertical reference signal for TG Ground (for digital) Power supply (for digital I/O) Power supply (analog power supply 1 for video) Reference voltage input (for luminance signal) Reference resistor terminal (for luminance signal) Luminance signal output Ground (analog 1 for video) Reference voltage input (for color signal) Rference resistor terminal (for color signal) Modulation color signal output R-Y signal output Capacitor terminal for phase compensation (for luminance signal) In Digital sinal input from A/D (From CDS+AGC+A/D: IC5201) Power supply (for digital I/O) In Digital signal input from A/D (From CDS+AGC+A/D: IC5201) Name In/Out Out Out Out Out Out Out Out Out Out Out In Description Clock output for field memory (To FIELD MEMORY: IC4002) Memory write transfer (To FIELD MEMORY: IC4002) Read address (To FIELD MEMORY: IC4002) Ground (for digital) Power supply (for digital core) Write address (To FIELD MEMORY: IC4002) Input enable (To FIELD MEMORY: IC4002) Memory read enable (To FIELD MEMORY: IC4002) Memory write enable (To FIELD MEMORY: IC4002) Read address enable (To FIELD MEMORY: IC4002) Write address enable (To FIELD MEMORY: IC4002) Power supply (for digital core) Line hold flag output Digital signal input from A/D (From CDS+AGC+A/D: IC5201) Ground (for digital)

Table 3-6-3 CAMERA_DSP (IC4001) pin functions 4/5

3-17

 CAMERA_DSP (IC4001) pin functions 5/5

Pin No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Name AVDDV2 AVSSV2 COMPC VREFVF IREFVF COMPVF Y2OUT BYOUT AVDDA KOUT VREFLK VREFHK AVSSA DVDDM VDD1 VDD2 CLR DTEST TCK TMS VSS VDD1 TRST TDI TDO VDOSD HDOSD CLKOSD VC1 VC2 VR VSS VDD2 VG VB BLK1 BLK2 VBLK TVSELO VREFO In/Out Out Out Out In In In In In In Out Out Out Out In In In In In In In In In Out Ground (analog 2 for video) Capacitor terminal for phase compensation (for color signal) Reference voltage input (for VF signal) Reference resistor terminal (for VF signal) Capacitor terminal for phase compensation (for VF signal) Luminance signal output for VF B-Y signal output Power supply (analog power supply for audio) Shutter sound output Reference voltage input (-) (for shutter sound) Reference voltage input (+) (for shutter sound) Ground (analog for audio) TEST Power supply (for digital core) Power supply (for digital I/O) Master clear TEST JTAG JTAG Ground (for digital) Power supply (for digital core) JTAG JTAG JTAG Vertical reference signal for OSD Horizontal reference signal for OSD Clock output for OSD Character signal 1 Character signal 2 Character signal 3R Ground (for digital) Power supply (for digital I/O) Charactor signal 3G Charactor signal 3B Blank signal 1 Blank signal 2 Blank signal 3 TV system select Vertical reference signal for PB Description Power supply (analog power supply 2 for video)

Table 3-6-3 CAMERA_DSP (IC4001) pin functions 5/5

3-18

3.6.4 VTR_DSP (IC3001: JCY0130) function 1. VTR_DSP (IC3001) block diagram

DOOUT SVHSOUT SDPRD Main Emph W/D Clip Main De-Emph SW30 ADDV HDMASK DO_DET S_DET S-ET LPF N.L Emph Sub Emph N.L De-Emph Sub De-Emph REC PB PC1 HSW

PB-FM_IN

8bit A/D

HPF

FM_DEMO

FB CLAMP

FM_MOD

GC

10bit D/A

REC-FM_OUT

Y-LPF PB

REC YNR

D.E.

OSYNCB

REC

PB

REC

REC Chroma Logic

PB

FF CLAMP

LNC PB YNR

NC/ PC2

MUTE

GC

Digital I/F DOCK

PB-Y_OUT YPO [0-7]

REC-Y_IN YPI[0-7] PB-C_IN Digital I/F

REC-Y

SYNC ADD

Y-CLIP PB LPF REC PB REC

SYND_SEP MUTE GC 10bit D/A

CSYNC REC-C_OUT HDOUT VDOUT C-COMB Decoder NRB_OUT

PB-C

HPF

ACC AMP

HiFi TRAP

CBLK DICK NRBIN REC-C_IN CPI[0-3] PB-C_IN Digital I/F Burst Add Pilot Burst Add Chroma Encoder

ACC_DET Chroma Logic Burst Emph APC_DET

L_CNR

Burst De_Emph

MUTE Pilot Burst Erase

GC

Dightal I/F DOCK

PB-C_OUT CPO[0-3]

CK_GEN 8fsc 2FSC_OUT CAMCK 8fsc

PB REC DATA SET

DOCK NRBOUT

CAM_ADCK AD1_CK

SDCK SLD

STD

Fig. 3-6-4 VTR_DSP (IC3001) block diagram

3-19

2. VTR_DSP (IC3001) pin functions 1/3

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name NC NC NC VCC efmin7 efmin6 efmin5 efmin4 efmin3 efmin2 efmin1 efmin0 VCCAC Vcc (core) GNDACC SDET_CTL VCCDC xin xout GNDDC OVL_AI OVL_BI TRG_IN OVL_AO OVL_BO fade csync hdmask (sleep) addv sw30 sdck sld std NC NC NC NC NC NC cpi7 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 cpi0 ypi7 In/Out Not used Power supply (2.2V) Description

In

External FM input (Digital) L: fixed

In In Out In In In Out Out In Out In In In In In In

Power supply (3.3V) Power supply (2.2V) Ground SVHS detect period input Power supply (3.3V) X'tal input X'tal output Ground OVL_A OVL_B Trigger input OVL_A OVL_B Fade input Sync, output HD mask ADD V SW30 State data clock (From CPU: IC101) State data latch pulse (From CPU: IC101) State data input (From CPU: IC101)

Not used

Not used

In In In

REC C signal input (digital) (From CAMERA DSP: IC4001) REC C signal / PB C signal inputs (digital) (From CAMERA DSP: IC4001) REC Y signal / PB C signal inputs (digital) (From CAMERA DSP: IC4001)

Table 3-6-4 VTR_DSP (IC3001) pin functions 1/3

3-20

 VTR_DSP (IC3001) pin functions 2/3

Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name ypi6 ypi5 ypi4 ypi3 ypi2 ypi1 ypi0 cblk csyncb nrbin dick camck VCCDC ypo0 ypo1 ypo2 ypo3 ypo4 ypo5 ypo6 ypo7 VCC2 NC NC NC NC NC GNDDC cpo 0 cpo 1 cpo 2 cpo 3 NC NC NC NC nrbout dock hdout vdout doout ad1_ck camadck NC NC NC NC NC In/Out Description

In

REC Y signal / PB C signal inputs (digital) (From CAMERA DSP: IC4001)

In In In In Out -

blunking pulse (From CAMERA DSP: IC4001) SYNC input (From CAMERA DSP: IC4001) Color phase input (From CAMERA DSP: IC4001) Digital interface clock input (From CAMERA DSP: IC4001) Camera clock output (To CAMERA DSP: IC4001) Power supply (3.3V)

Out

PB Y output (digital) (To CAMERA DSP: IC4001)

Power supply (2.2V CORE)

Not used

Ground

Out

PB C output (digital) (To CAMERA DSP: IC4001)

Not used

Out Out Out Out Out Out In

Color phase output (To CAMERA DSP: IC4001) Digital interface clock output (To CAMERA DSP: IC4001) HD output VD output DO output CDS clock output Camera clock input

Not used

Table 3-6-4 VTR_DSP (IC3001) pin functions 2/3

3-21

 VTR_DSP (IC3001) pin functions 3/3

Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name NC NC NC NC NC NC GNDAC svhsout VCCAC NC NC NC NC NC NC selftest2 selftest1 VSSAA VDDAA reccout cbl2 rext2 cbu2 VSSAA NC cbl1 VDDAA VSSAA NC rext1 cbu1 VDDAI fmout bias VSSAA VDDAA pbfmi vrl vrt VDDAA vrb VDDAA VSSAA clear fscout NC NC NC In/Out Description

Not used

Out -

Ground SVHS output Power supply (3.3V)

Not used

In In Out In In Out In In Out Out In In Out In In In Out -

Self test 2 Self test 1 Ground Power supply (3.3V) REC C signal output (analog) DAC external DAC external DAC external Ground Not used DAC external Power supply (3.3V) Ground Not used DAC external DAC external Power supply (analog 2V) REC FM output (analog) ADC external Ground Power supply (3.3V) PB FM input (analog) ADC external ADC external Power supply (3.3V) ADC external Power supply (3.3V) Ground Clear 2Fsc output Not used

Table 3-6-4 VTR_DSP (IC3001) pin functions 3/3

3-22

3.6.5 VTR_ASP (IC3101: HA118219A) function 1. VTR_ASP (IC3101) block diagram & pin location
SECAM C IN VOUT-GND VOUT C IN VOUT Y IN REC C IN

2FSC IN

CR-DET

OPEN 2

OPEN 1

VHS HI

BLK IN

36

35

34

33

32

31

30

29

28

27

26

B. G. BG

25

6dB CLK

CR FREE ADJ.

1/2

37 38 39 40 41 42 43 44 45
ON SECAM SECAM

24
SERIAL I/O CLAMP D/A LPF LUG READ LPF LPF G. EQ A/D LPF 2M LPF FM AGC TRAP

FM-GND

DATA

23 22 21 20 19 18 17 16

REC FM IN

LOAD

PB FM OUT

C G CTL

LPF

G-EQ SB ADJ

Y G CTL

GCTL D/A LPF EQ

SECAM

HPF

P. EQ

PB C OUT

VOUT C OUT

BUFF

GCTL
SECAM

BPF

BLK
SECAM

TRAP

FM VCC

VOUT YC MIX OUT

BUFF

PB FM AGC

4.2M TRAP

SECAM

VOUT Y OUT

BUFF

REC C BUFF.

PB FM+C IN

SECAM TRAP

REC FM OUT

VOUT-VCC

46 47 48
VCA

PB + REC -

A. LINE OUT

REC MUTE
ON

OFF

LINE MUTE REC EQ

15 14
PBxEP TRIC ON
+ -

REC C OUT

A. GND

OFF + -

13

A. VEE

DET

REC ON

SP ON

10

11

12

A. SPK VCA CTL

A. PB EP SW

A. BYPASS

A. PB EQ OUT 1

Fig. 3-6-5 VTR_ASP (IC3101) block diagram & pin location

3-23

A. PB EQ OUT 2

A. PB IN (+)

A. MUTE

A. LINE IN 1

A. ACL FILTER

A. REC OUT

A. PB IN (-)

SH_MIX

2. VTR_ASP (IC3101) pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name A. SPK VCA CTL SH_MIX IN A. Line in 1 A. BYPASS A. ALC FILTER A. MUTE A. REC OUT A. PB EP SW A. PB IN (+) A. PB IN (-) A. PB EQ OUT 1 A. PB EQ OUT 2 A. Vee A. GND REC C OUT REC FM Out PB FM+C IN PB FM AGC FM Vcc PB C OUT G-EQ SB ADJ PB FM OUT REC FM IN FM-GND REC CIN B.G. 2FSC IN VHS HI CR-DET VOUT Y IN VOUT-GND VOUT C IN OPEN1 SECAM C IN OPEN2 BLK IN CLK Data LOAD C G CTL Y G CTL VOUT C OUT VOUT YC MIX OUT VOUT Y OUT SECAM Trap VOUT-VCC A. LINE OUT A. SPK OUT In/Out In In Out In Out Out Out Out In Out Out In In In In In In In In In In Out Out Out Out Out Description Audio speaker level control SH_MIX SIG IN Audio line input 1 Bypass capacitor terminal for audio ALC DC regeneration Filter for audio ALC Audio mute (H level: LINE+REC mute, L level: Mute off) Audio recording output Playback audio EQ changeover switch Playback audio EQ amp. input Playback audio EQ amp. feedback terminal Output 1 for playback audio EQ amp. feedback Output 2 for playback audio EQ amp. feedback Power supply (for audio) Ground (for audio) Recording color signal output Recording FM signal output Playback FM + color input Adjutment free filter of playback FM level Power supply (Vcc) Playback color signal output Low characteristics adjustment of FM signal (GND: Gain small, Vcc: Gain large) Playback FM signal output Recording FM signal input Ground (FM) Recording color signal input Reference bias filter 2FSC input S-VHS/VHS control (VHS=Hi, S-VHS=Lo VTh is 0.7V) Smoothing filter of CR adjustment free circuit V out Y signal input Ground (VOUT) V out Color signal input Open terminal 1 SECAM color input Open terminal 2 Blanking pulse input Serial control clock input (From CPU: IC101) Serial control data input (From CPU: IC101) Serial control load input (From CPU: IC101) Color gain control Luminance gain control V out color output V out YC MIX output (2.0Vp-p) V out luminance output (2.0Vp-p) SECAM Trap Power supply (VOUT) Audio line output Audio speaker output

Table 3-6-5 VTR_ASP (IC3101) pin functions

3-24

3.6.6 CPU (IC101: UPD703039-013) function 1. Camera system operation block diagram
IC101
IC5201 CDS/AGC A/D IC5202 TG V.DRIVER
10 SCK3 9 SO3 36 CCD_CS 21 DSGAT

CPU
Q110 TXD 3 RXD 2 35 CDS_CS RXD 94 D107

J503 JLIP

IC104
AL_CLK 1 AL_SO 176 AL_SI 175 EEPROM_CS 32

EEPROM

IC107
RTC_CS 28 RTC_INTR 56

Li +

IC105
HE_OFFSET

RTC

LITHIUM

EVR
HE_GAIN 37 EVR_LOAD

X102 IRIS DRV & HALL AMP IC4501 FOCUS/ ZOOM DRIVER
59 IRIS_PWM 16 IRIS_O/C 125 HOLE REG_3.2V PWR_LED ZOOM_SW 130 PHOTO 131 DIAL_MN 52 DIAL_AT 51 DIAL_OF 50 DIAL_PB 49 TRIG_SW 46

41 LENS_MDA_CS 26 LENS_MDA_CLK

ZOOM UNIT
EIS_SW

OPTICAL BLOCK
Q4501 Q4251

123 FOCUS_SENS 124 ZOOM_SENS 17 LENS_LED

EJECT_SW 93 KEY_A 126 KEY_C 128 B_PHASE 98 A_PHASE 102 DSC_LED 18

KEY_A STOP REW FF PLAY / PAUSE MENU / DISPLAY EFFECT SP/EP / COUNTOR_R/M KEY_C DIAL_PUSH P.AE E.STABILIZER VIDEO/DSC

OPERATION UNIT

Amp
IR_SENSOR

12 IR_FLICK 121 IR_A/D

SW503
LIGHT_SW 127 4 DSP_RST

LIGHT SW DC LIGHT

IC4001

16

145-152 155-162 138 139 140 141 142 170

AD0-15

LAMP_ON 20

REG

LBEN_L UBEN_L R/W_L DSTB_L ASTB WAIT_L

CAMERA DSP

96 VD 15 HD 103 FI 104 FRP 110 VDVHS 95 OMT

IC8001
73 V_FF 24 16 SCLK2 7 SO2 6 SI2 5 CS_CE1 24 OSD_DATA 25 OSD_CLK 31 OSD_CS IC8002 IC8003 16Mbits (2MB) FLASH ROM

IC4003 ON SCREEN

DSC_IF
M32_RX CPU

Fig. 3-6-6 Camera system operation block diagram

3-25

2. Deck system operation block diagram

IC101
CPU X101
71 X1 70 X2 UNREG OPEN_SW 48 REV_SW 47

MONI SW IC7601

IC102 3.2V REG RESET BATT CHECK IC106

120 BATT SI3 8 MON_CS 44 13, 39, 69, 81, 99, 135, 136, 153, SYS_3V 66 RESET(L)

MON_LOAD 43

MONI_LCD DRIVER IC7602 EEPROM

JIG CONN.

65 VPP7.8V BL_ON 144

BACK LIGHT IC7400

133 REG_3V

REG
116 D_PWR_ON 183 VF_CTL VF_LOAD 42

VF_LCD DRIVER IC105

REMOTE

101 REMOTE_IN

SCK3 10 SO3 9 EVR_LOAD 37

EVR

HE_GAIN HE_OFFSET Y_GAIN C_GAIN SPK_VOL FREQ_ADJ ENV_ADJ

IC3001 DEW SENSOR

Q103 87 CTL_ERASE 122 DEW_SENS V_DSP_CS 34 VTR_RST 173 S_DET_H 174 SDET_CTL 78 V_PULSE V_FF V_OVL_A V_OVL_B TBC_VD 79 73 74 75 77

VTR_DSP

A/C HEAD

CTL AMP IC1201

83 REC_CTL 112 PB_CTL

IC3501 PRE/REC
117 PB_FM_DET 171 V_REC_L 188 SP_L 84 V_RC_MUT

IC3101

V_ASP_CS 33

VTR_ASP
PB FM+C

A_MUTE 167 172 V_PB_H

FLY.E
86 FEH_ON

V_PLS_ON 88

92 REC_SAFE_SW 45 CAS_SW 132 SVHS_SW 106 CAM_SW_A 107 CAM_SW_B 108 CAM_SW_C

A_PB 186 A_BIAS_L 85 SH_L 185

AUDIO BIAS

IC1601

MECHA SENSOR

REG_4.8V MECHA_MDA_CS 38 90 REEL_LED 89 TAPE_LED DRUM_FG 109 DRUM_PG 113 DRUM_REF 58 CAP_FG 111 CAP_REF 57 CAP_SD 27 CAP_BRAKE 80

MDA

118 START_SENS 119 EN_SENS 54 SUPSENS 53 TUSENS

Fig. 3-6-7 Deck system operation block diagram

3-26

3. CPU (IC101) pin functions 1/4

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 RXD TXD DSP_RST SI2 SO2 SCLK2 SI3 SO3 SCK3 NC IR_FLICK SYS_3V GND HD IRIS_O/C LENS_LED DSC_LED NC LAMP_ON DSGAT NC NC OSD_DATA OSD_CLK LENS_MDA_CLK CAP_SD RTC_CS NC NC OSD_CS EEPROM_CS V_ASP_CS V_DSP_CS CDS_CS CCD_CS EVR_LOAD MECHA_MDA_CS SYS_3V GND LENS_MDA_CS VF_LOAD MON_LOAD MON_CS Name AL_CLK In/Out In/Out In Out Out In Out In/Out In Out In/Out In In Out Out Out Out Out Out In/Out Out In Out Out Out Out Out Out Out Out Out Out Out Out Out Serial data input (From JLIP) Serial dta output (To JLIP) Reset output (To IC4001, IC4003, IC4501) Serial data input (From DSC_IF: IC8001) Serial data output (To DSC_IF: IC8001) Serial clock I/O (From/To DSC_IF: IC8001) Serial data input (From EEPROM: IC7602) Serial data output Serial clock I/O Not used Infrared flicker component input Power supply (3.0V) Ground HD (horizontal drive) input IRIS manual control signal (Open: H, Close: L) LENS LED control DSC LED control Not used Video lamp ON/OFF control TG power save control signal Not used Not used On screen serial data output (To ON SCREEN: IC4003) On screen serial clock I/O (From/To ON SCREEN: IC4003) LENS MDA clock output Capstan short detect input RTC chip select output (To RTC IC: IC107) Not used Not used OSD IC chip select output (To ON SCREEN: IC4003) EEPROM chip select output (To EEPROM: IC104) VIDEO ASP chip select output (To VTR_ASP: IC3101) VIDEO DSP chip select output (To VTR_DSP: IC3001) CDS chip select output (To CDS/AGC+A/D: IC5201) TG chip select output (To TG+V_DRV: IC5202) EVR IC data load output (To EVR IC: IC105) MECHA MDA chip select output (To MECHA MDA: IC1601) Power supply (3.0V) Ground LENS MDA chip select output (To LENS MDA: IC4501) Data load pulse output (To LCD DRIVER: IC7400) Data load pulse output (To LCD DRIVER: IC7601) EEPROM chip select output (To EEPROM: IC7602) (From/To IC105, IC1601, IC3001, IC3101, IC4501, IC5201, IC5202, IC7400, IC7602) Description Serial clock I/O (From/To RTC IC: IC107, EEPROM: IC104)

Table 3-6-6 CPU (IC101) pin functions 1/4

3-27

 CPU (IC101) pin functions 2/4

Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Name CAS_SW TRIG_SW REV_SW OPEN_SW DIAL_PB DIAL_OF DIAL_AT DIAL_NM TUPSENS SUPSENS NC RTC_INTR CAP_REF DRUM_REF IRIS_PWM NC NC NC NC NC VPP7.8V RESET (L) XT1 XT2 SYS_3V X2 X1 GND V_FF V_VOL_A V_VOL_BCD NC TBC_VD SDET_CTL V_PULSE CAP_BRAKE SYS_3V GND REC_CTL V_RC_MUT A_BIAS_L FEH_ON CTL_ERASE V_PLS_ON In/Out In In In In In In In In In In In Out Out Out In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Cassette switch detect Trigger switch input LCD monitor reverse switch input LCD monitor open switch input Dial switch input (PLAY BACK) Dial switch input (OFF) Dial switch input (AUTO) Dial switch input (PRO) Take-up reel sensor input Supply reel sensor input Not used RTC (real-time clock) 1 sec. interrupt (From RTC IC: IC107) Capstan control signal (PWM output) Drum control signal (PWM output) Iris control signal (PWM output) Not used Not used Not used Not used Not used Power supply (7.8V) CPU reset signal input (Reset: L) OSC terminal for Sub clock (H: fixed) Not used Power supply (3.0V) X'tal terminal for main clock X'tal terminal for main clock Ground Video flip-flop signal output Video overlap signal for A ch Video overlap signal for B, C, D ch Not used Vertical reference pulse output SVHS detect period output V. sync pulse output for special playback Capstan brake controlsignal Power supply (3.0V) Ground Control pulse signal for recording Video REC mute (ON: H) Audio bias (ON: L) Flying erase head control (ON: H) Control pulse erase Dummy V pulse output for special playback Description

Table 3-6-6 CPU (IC101) pin functions 2/4

3-28

 CPU (IC101) pin functions 3/4

Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Name TAPE_LED REEL_LED NC REC_SAFE_SW EJECT_SW RXD OMT VD CS_CE1 B_PHASE SYS_3V GND REMOTE_IN A_PHASE FI FRP NC CAM_SW_A CAM_SW_B CAM_SW_C DRUM_FG VDVHS CAP_FG PB_CTL DRUM_PG OEM_REG5CTL NC D_PWR_ON PB_FM_DET START_SENS EN_SENS BATT IR_A/D DEW_SENS FOCUS_SENS ZOOM_SENS HOLE KEY_A LIGHT_SW KEY_C KEY_D ZOOM_SW PHOTO SVHS_SW In/Out Out Out In In In In In In In In In In In In In In In In In In In Out Out In In In In In In In In In In In In In In In In LED control signal for tape sensor LED control signal for reel sensor Not used REC safety switch input Eject switch input RS232C data input ESI data readout enable VD (vertical drive) input Chip select input for DSC serial communication Dial switch B ch input Power supply (3.0V) Ground Remote control pulse input Dial switch A ch input Feild index input Frame reference pulse input Not used Mechanism mode input A (rotary encoder switch) Mechanism mode input B (rotary encoder switch) Mechanism mode input C (rotary encoder switch) Drum FG signal input Vertical reference signal for playback Capstan FG signal input Control pulse signal input Drum PG signal input Pull-up signal for RAE control output Not used Deck poewr control signal (ON: H, OFF: L) Playback FM signal envelop input Tape start sensor input Tape end sensor input Battery voltage detect Infrared D/C component input Dew sensor detect Focus sensor input Zoom sensor input Iris hole element voltage detect Switch input (STOP, REW, FF, PLAY/PAUSE, EFFECT, COUNTOR_R/M) Light switch input Switch input for camera system (P. AE) TP102 Zoom switch input Photo swithc input S-VHS switch detect Description

Table 3-6-6 CPU (IC101) pin functions 3/4

3-29

 CPU (IC101) pin functions 4/4

Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 GND SYS_3V SYS_3V GND LBEN (L) UBEN (L) R/W (L) DSTB (L) ASTB NC BL_ON AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 SYS_3V GND AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 VF_CTL S_SPK_ON SH_L A_PB A_MUTE SP_L NC WAIT (L) V_REC_L V_PB_H VTR_RST S_DET_H AL_SI AL_SO Out Out Out Out Out In Out Out Out In In Out VF ON/OFF control signal Not used Shutter sound mute control signal Audio control signal (PB: H) Audio mute control signal Tape speed control signal (SP: L) Not used DSP bus access wait input (wait: L) Video recording control signal (Recording: L) Video playback control signal (Playback: H) Reset signal output for VTR DSP S-VHS detect Serial reception data input (From RTC IC: IC107, EEPROM: IC104) Serial transmission data output (To RTC IC: IC107, EEPROM: IC104) In/Out Multiplexed bus bit for DSP (From/To CAMERA DSP: IC4001) Power supply (3.0V) Ground In/Out Multiplexed bus bit for DSP (From/To CAMERA DSP: IC4001) Name REG_3V In/Out Out Out Out Out Out Out Power supply (3.0V) Ground Power supply (3.0V) Power supply (3.0V) Ground DSP bus access lower enable (To CAMERA DSP: IC4001) DSP bus access upper enable (To CAMERA DSP: IC4001) DSP bus access read/write select (To CAMERA DSP: IC4001) DSP bus access data latch enable (To CAMERA DSP: IC4001) DSP bus access address latch enable (To CAMERA DSP: IC4001) Not used LCD monitor back light on control (ON: H) Description

Table 3-6-6 CPU (IC101) pin functions 4/4

3-30

3.6.7 DSC_IF (IC8001: JCY0076B) function 1. DSC_IF (IC8001) block diagram

DMA controller TEST CCD image interface Y7-0 C3-0 FLD AVD AHD VCLK

DMACSJVC
SCLK

CCDIF2

CLKGEN
Clock generator
Y S

RST(L)

Interval timer

UART1 ITIME1
Y S

IrDASIR10

TXD1 RXD1

XIN XOUT

1/ 2 ITIME2 UART2

IrDA serial communication

TXD2 RXD2 SI SO SCK P_A9-0 P_D15-0 P_CE1(L) P_CE2(L) P_OE(L) P_WE(L) P_REG(L) P_IORD(L) P_IOWR(L) P_RST P_READY P_CD1(L) P_CD2(L) P_VS1(L) P_VS2(L) P_WAIT(L)

TIME
A8-30 D0-15 SID(L) BS(L) RW BCL(L) BCH(L) DC(L) HREQ(L) HACK(L) CS(L) INT(L)
Bus interface unit

CSIO
Clocked serial I/O

Configration

PCMCIA
PCMCIA interface Interrupt controller

BIU

Programmable port

ICU PORT_J

Selector

CONFIG

CE1 RY_BY PORT3 INT1 INT2 INT3 BUSY(L) CE(L) OE(L) WE(L) CE2(L)

Fig. 3-6-8 DSC_IF (IC8001) block diagram

3-31

2. DSC_IF (IC8001) pin functions 1/3

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name VDD A19 A18 A17 A16 A15 A14 DC BS P_CE1 P_CE2 P_OE P_A0 P_A1 P_A2 P_A3 P_A4 GND VDD SCLK XOUT XIN P_A5 P_A6 P_A7 P_A8 P_A9 P_WE CS A13 A12 A11 A10 A9 A8 VDD GND D0 D1 D2 D3 INT HACK HREQ TEST P_D0 P_D1 P_D2 In/Out Power supply (REG3.3V) Description

In/Out

CPU control address bus (From/To IC8002: M32_RX)

In/Out In In/Out In/Out In/Out

CPU control bus: Wait control (From/To IC8002: M32_RX) CPU control bus: Busy input (From IC8002: M32_RX) Not used Not used Not used

In/Out

Not used

In Out In

Ground Power supply (REG3.3V) System clock input 1/2 period clock output External clock input

In/Out

Not used

In/Out Out

Not used CPU control bus: Chip select

In/Out

CPU control address bus (From/To IC8002: M32_RX)

Power supply (REG3.3V) Ground

In/Out

CPU control data bus (From/To IC8002: M32_RX)

Out In Out In/Out In/Out

External interrupt request output (To IC8002: M32_RX) Bus hold acknowledge input (From IC8002: M32_RX) Bus hold request output (To IC8002: M32_RX) Test terminal (Normal: L) Not used

Table 3-6-7 DSC_IF (IC8001) pin functions 1/3

3-32

 DSC_IF (IC8001) pin functions 2/3

Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name P_D3 P_D4 P_D5 P_D6 P_D7 GND VDD P_D8 P_D9 P_D10 P_D11 P_D12 P_D13 P_D14 P_D15 P_REG P_IORD P_IOWR P_RST D4 D5 D6 D7 GND VDD A20 A21 A22 A23 A24 A25 RST P_READY P_CD1 P_CD2 P_VS1 M32R_RST P_WAIT CE2 BUSY INT1 INT2 INT3 PORT3 VDD GND TXD1 RXD1 In/Out Description

In/Out

Not used

Ground Power supply (+3.3V)

In/Out

Not used

In/Out In/Out In/Out In/Out

Not used Not used Not used Not used

In/Out

CPU control data bus (From/To IC8002: M32_RX)

Ground Power supply (REG3.3V)

In/Out

CPU control address bus (From/To IC8002: M32_RX)

In In/Out In/Out In/Out In/Out Out In/Out Out In In In In In/Out Out In

System reset input (From IC8002: M32_RX) Not used Not used Not used Not used System reset output (To IC8002: M32_RX) Not used Not used Not used Not used VD (vertical drive) interrupt input HD (horizontal drive) interrupt input Field index input port Power supply (REG3.3V) Ground RS232C TXD for IrDA RS232C RXD for IrDA

Table 3-6-7 DSC_IF (IC8001) pin functions 2/3

3-33

 DSC_IF (IC8001) pin functions 3/3

Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name TXD2 RXD2 RW SID BCL (L) BCH (L) A26 A27 A28 A29 A30 VDD GND D15 D14 D13 D12 SI SO SCK CE1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 GND VDD CE OE WE RY_BY C3 C2 C1 C0 FLD AHD AVD VCLK D11 D10 D9 D8 GND In/Out Out In In/Out In/Out In/Out In/Out Description RS232C TXD for PC RS232C RXD for PC CPU control read and write control bus (From/To IC8002: M32_RX) CPU control memory area select bus (From/To IC8002: M32_RX) CPU control lower byte access signal bus (From/To IC8002: M32_RX) CPU control upper byte access signal bus (From/To IC8002: M32_RX)

In/Out

CPU control address bus (From/To IC8002: M32_RX)

Power supply (REG3.3V) Ground

In/Out

CPU control bus data (From/To IC8002: M32_RX)

In Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out Out Out In

Clock sync. serial data input (From IC101: CPU) Clock sync. serial data output (To IC101: CPU) Clock sync. serial clock output (From/To IC101: CPU) Clock sync. serial communication chip select (From/To IC8002: M32_RX)

Digital luminance signal 8 bit inputs (From/To IC4001: CAMERA DSP)

Ground Power supply (REG3.3V) Chip enable (To IC8003: 16Mb FLASH) Output enable (To IC8003: 16Mb FLASH) Write enable (To IC8003: 16Mb FLASH) Ready / busy signal (To IC8003: 16Mb FLASH)

In/Out

Digital color difference signal inputs (From/To IC4001: CAMERA DSP)

In In In In

Feeld index input port (From IC4001: CAMERA DSP) HD (horizontal drive) input (From IC4001: CAMERA DSP) VD (vertical drive) input (From IC4001: CAMERA DSP) CCD pixel sync. clock input (From IC4001: CAMERA DSP)

In/Out

CPU control data bus (From/To IC8002: M32_RX)

Ground

Table 3-6-7 DSC_IF (IC8001) pin functions 3/3

3-34

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Printed in Japan 2000-07 (TM1)