Aaic Adc Casestudy Note

Analog-to-Digital Converter Case Study
Tai-Cheng Lee Spring 2006
Folding ADC Case Study

1. An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing A. G. W. Venes and R. J van de Plassche Page(s): 1846-1853, JSSC 1996 Dec 2. An 8-b 100-MSample/s CMOS Pipelined Folding ADC M-J Choe, B-S Song and K Bacrania Page(s): 184-194, JSSC 2001 Feb 3. An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm K. Bult and A Buchwald Page(s): 1887-1895, JSSC 1997 Dec
A Folding A/D with Distributed Track-and-Hold Preprocessing

Detection of the signal
Conventional and proposed architecture

Generation of the zero-crossing signal
Gain stage

The design spec for each block:
Single track-and-hold amplifier Linear region Linearity in entire input range (1.6Vpp) of A/D converter 8-bit accuracy Distributed track-andhold operation Linearity in 1/16 of the input range of the A/D converter 8-bit accuracy divided by the gain in the input gain stages
Dynamic accuracy Settling Hold mode feedthrough Clock switch charge injection Overall power dissipation
High power dissipation in buffer amplifier to ensure low distortion Single clock switch
No additional power dissipation apart of input gain stages Multiple clock switches
Clock distribution

Reference ladder feedthrough:
Equivalent circuit model to calculate the maximum allowable resistor

Interpolation nonlinearity:
Interpolation error due to different gate drive

ADC block diagram:
Input T/H circuit:

Implementation of a folder signal:
Active interpolation circuit:

Differential interpolation circuit:
Comparator:
10
An 8-b 100-MSample/s CMOS Pipelined Folding ADC

The concept of the two-stage and folding ADC:
11

Flash ADC:
12

Folding ADC:
13

Folding amplifier:
14

Conventional folding ADC:
15

Folder design: k=4 and k=3
16

Pipeline folding ADC
Timing
17

Top level block diagram
18

Second stage folder
19

INL due to gain mismatch
20

Effect of tail current source mismatch
21

comparator design
22

conventional digital error correction
23

generic digital error correction
24
An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Conventional preamplifier and resistor-averaging preamplifier
25

First resistor averaging in:
K.Kattmann and J.Barrow,A technique for reducing differential nonlinearity errors in ash A/D converters, in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1991, pp. 170171.
Effect of resistor averaging:
26

Improved resistor averaging:
Transconductor stage:
27

Analysis of the effect of resistor averaging:
Correlation between neighboring signal after averaging:
28

Simulated DNL and INL after resistor averaging:
Example of 3X folding signal:
29

Understanding the pipeline folding signal:
ADC floor plan
30
Digitally Calibrated Pipeline ADC

1. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC Karanicolas, A.N.; Hae-Seung Lee; Barcrania, K.L. Page(s): 1207-1215, JSSC 1993 Dec 2. A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter Opris, I.E.; Lewicki, L.D.; Wong, B.C. Page(s): 1898-1903, JSSC 1998 Dec
31
Digitally Calibrated Pipeline ADC -- I
Ideal pipeline ADC:
Transfer characteristics:
32
nonideality of transfer curve:
Gain is less than 2 per stage
33
Top level diagram of backward calibration:
Residue plot for gain <2 with

comparator offset
34
Actual implementation of non-radix-2 ADC:
35
Digitally Calibrated Pipeline ADC -- II
Over-range implementation:
Residue plot:
36
12-bit ADC with 3 over-range stage:
Code combine and requirement of over-range stage
37
Principle of digital error correction ADC and its implementation:
38
Differential-to-single ended converter
39
kT/C noise (I)

RMS voltage for kT/C noise:
40
kT/C noise (II)

The bottom line for a switched-cap circuit for different capacitance
41
kT/C Noise in Switched-Cap Circuit

kT/C noise in SC circuit
42
Noise in OP amp (I)

Single-stage op amp
43
Noise in OP amp (II)

Two-stage op amp
44
OP amp based SHA (I)

Different OP amp SHA
45
OP amp based SHA (II)

How to pick the optimal sampling capacitor
46
OP amp based SHA (III)

An optimal sampling capacitor can be obtained.
47
OP amp based SHA (V)

Other design considerations: (1) Gain error
Does it matter? (2) Slew rate:
48
OP amp based SHA (IV)

Other design considerations: (3) switch on resistance:
49
Multi-stage Offset Cancellation

What is the offset voltage after cancellation?
50
Auto-Zero Comparator
Charge injection due to S1:
51
High-Speed Pipelined ADC

ADC top level diagram:
52

feedback factor and load capacitance for different resolution
53

digital correction
54

subtractor implementation: R-DAC and C-DAC
55

The requirement of stage accuracy
56

The requirement of stage accuracy
57

The design algorithm of pipelined ADC:
58

The power dissipation vs. sampling frequency for various resolution ADCs:
59

Different resolutions for each stage:
60

Scaling for each stage:
61

Total power for scaling and non-scaling ADC:
62
Low-Power Low-Voltage Pipelined ADC

1.5 bits per stage:
63

Digital error correction:
64

First-stage SHA:
65

Timing for pipeline ADC
66
Dynamic Comparator
A dynamic comparator with built-in threshold generator:
67
Low-voltage OP
A 3.3-Volt OP amp
68
Low-voltage OP
Output CMFB circuit
69
Low Voltage Operation of SC Circuits

CMOS switch
70

Boosted circuit:
71

Floating well to prevent latch up:
72
Bias Circuits for OP amp

The bias of cascode op:
73
Clock Generator
Clock generator and line up the edge:
74

Aaic Adc Casestudy Note

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Analog-to-Digital Converter Case Study

Tai-Cheng Lee Spring 2006

Folding ADC Case Study

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Conventional and proposed architecture

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Equivalent circuit model to calculate the maximum allowable resistor

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Interpolation error due to different gate drive

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Input T/H circuit:

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Active interpolation circuit:

Tai-Cheng Lee Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

Tai-Cheng Lee Spring 2006

An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Tai-Cheng Lee Spring 2006

An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Effect of resistor averaging:

Tai-Cheng Lee Spring 2006

An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Tai-Cheng Lee Spring 2006

An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Correlation between neighboring signal after averaging:

Tai-Cheng Lee Spring 2006