Comparison of resistor matching performance of polysilicon films in a CMOS process

T.G. ODwyer
Analog Devices Inc. 804 Woburn St., Wilmington, MA., U.S.A.
Abstract Matched pairs or arrays of resistive elements are an important aspect of many analog and mixed signal semiconductor circuit designs. Such structures are often implemented using the polysilicon layers in a typical CMOS process. In many processes, there are two or more such layers at the disposal of the designer. These typically have differing resistivity characteristics and matching performance. This paper examines the resistance matching characteristics of the polysilicon layers on a commercial CMOS process. The study encompasses both wafer-to-wafer and die-to-die variations, and presents models to describe the behavior. Using these models, conclusions are drawn regarding the appropriate layer to use to minimize the silicon area for target values of resistance and matching.

M.P. Kennedy
Department of Microelectronic Engineering, University College Cork, and Tyndall National Institute, Cork, Ireland. II. POLYSILICON RESISTOR FABRICATION

I.

INTRODUCTION

The resistor construction consists of three mask steps: (i) a length and width definition layer which defines the geometry of the polysilicon layer, (ii) a contact definition layer which defines the placement and size of the interconnections between the polysilicon layer and a metal layer, and (iii) the metallization layer which completes the connections to the other circuit components. Fig. 1 shows a graphical representation of the geometry. Note that the contacts are usually fixed in size and of uniform spacing, and result in non-uniform current flow at the ends of the resistor. Nevertheless, their size and density are such that the resistor can be considered approximately rectangular in shape with a uniform current flow. The resistance of polysilicon resistors is subject to statistical variation caused by non-uniformities in the wafer fabrication process. This variation causes mismatch between pairs or arrays of resistors and degrades circuit performance. To correct the performance when the amount of degradation is unacceptable, the resistors must be re-designed and new fabrication masks generated, resulting in considerable delay and expense. The motivation for this work is to establish a model for the degree of polysilicon resistor mismatch for any chosen geometry for the process under investigation, in order that

The use of matched resistive elements is commonplace in analog and mixed signal circuit designs, particularly in applications which require signal amplification, attenuation or inversion. The ultimate performance, and hence the commercial success, of such circuits often depends on the resistor matching i.e. the stability and repeatability with which resistors can be manufactured. Indeed, this topic is particularly important in applications where matching of entire arrays of resistors is required, such as low power digital-to-analog converters. Circuit design techniques such as sigma delta methodologies and dynamic element matching have evolved to alleviate the dependence of a system on matching performance, but nonetheless it remains an important limitation in circuit design. In this paper, we characterize the matching performance of the polysilicon layers on a commercial 0.35m CMOS process. The process contains two polysilicon layers: (i) a transistor gate layer with a nominal resistivity of six ohms per square and a minimum width specification of 0.35m, and (ii) an interconnect layer with a nominal resistivity of forty five ohms per square and a minimum width of 0.65m. For convenience, we will refer to these layers as Poly 1 and Poly 2, respectively.

Polysilicon W

L Contacts Metal routing Figure 1. Polysilicon resistor construction.

978-1-4244-3732-0/09/$25.00 2009 IEEE

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in (1) and (2), the average resistance and standard deviation of resistance mismatch can be estimated.
W L

(a) Orthogonal

We introduced a methodology in [1] for producing two over-determined sets of linear equations based on the mean resistance value and the standard deviation of mismatch for a number of test geometries, and then estimating the six model parameters using least squares surface fitting. Although thin films were considered in [1], the method of analysis is based on random variable theory and is independent of the type of resistive film. Hence, the same model and parameter estimation technique can be applied to the two polysilicon films under investigation in this paper. Our goal here is to investigate the accuracy with which the model matches the measured results, and to identify from the estimated values of the model parameters which process parameters are most significant in affecting mismatch performance. We will show that, in contrast to the conclusions for thin film resistors in [1], the etching of the length and width are negligible sources of mismatch error in the case of the polysilicon layers under investigation, and the only significant factor is the uniformity of the polysilicon material. IV. POLYSILICON RESISTOR TEST MASK

W L (b) Parallel Figure 2. Resistor layout detail.

the circuit performance can be predicted a priori, thus avoiding costly repair work. We will examine two polysilicon layers in a commercial CMOS process and demonstrate that they vary considerably in terms of resistivity and resistance mismatch performance. We will show that the resistance mismatch model described in [1] can be successfully applied to the layers under examination. By estimating the model parameters, we will demonstrate that the effects of width and length etching can be neglected, and that the primary cause is the nonuniformity of the material in both cases. Finally, we will demonstrate that, regardless of the target resistance required, the use of the Poly 1 layer always gives a minimum area solution compared to Poly 2 on this process for a given mismatch standard deviation target. III. MATCHING MODEL ESTIMATION

To characterize the resistor matching, a test mask was used which included a wide range of rectangular geometries covering the limits of length and width which can occur in practical designs. For each geometry, two resistors were placed in parallel, and these were electrically connected in series, as shown in Fig. 2. Two dummy resistors were placed alongside the devices under test to minimize variations caused by etching. Electrical contact was made to one node of each resistor, and to the common node. To minimize contact resistance effects during measurement, double bond pads were used for each node to form a Kelvin connection. To examine possible resistor orientation dependence, two versions of each test structure were generated, one of which was oriented orthogonally to the wafer flat, and the other parallel to it, as shown in Figs. 2(a) and (b). To minimize possible voltage effects on resistance, the same voltage stimulus was applied to all geometries during the measurement process. V. SUMMARY OF RESULTS

In [1], a resistance mismatch model for thin film resistors is presented and a procedure for estimating the model parameters is described. The model can be summarized in the following two equations: R = [L + L] / [W + W], (1) where R is the average resistance value, is the average resistivity of the film, L is the drawn length of the resistor, L is a systematic error between the drawn length and the actual length of the manufactured resistor, W is the drawn width of the resistor, and W is the systematic width error, and [Rm]2 = 2[L/(L+ L)]2 + 2[W/(W + W)]2 + 2 (u/)2/[(L + L)(W + W)], (2) where Rm is the standard deviation of the resistor mismatch, L is the standard deviation of the length etching, W is the standard deviation of the width etching, and u is the standard deviation of the resistivity of a unit square of the resistor material. To model a particular process, the six unknown parameters , L, W, L, W, and u must be estimated. Then, by inserting the desired values of L and W

A total of thirty test sites for each geometry and orientation across each of five wafers were tested and the average resistances calculated. A summary of the geometries used and the average resistances across all measurements is shown in Table I. No statistically significant differences were seen in either the wafer to wafer or resistor orientation average values. The standard deviations of the resistance mismatch of each pair of resistors were calculated for each geometry and orientation, and the results are shown in Table II. To protect

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TABLE I. Length m 300 200 100 50 25 10 5 3 200 200 200 200 200 200

SUMMARY OF MEAN RESISTANCE RESULTS BY GEOMETRY. Width m 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 50.0 25.0 10.0 5.0 1.5 0.35 Poly 1
Mean(Ohms)

Poly 2
Mean(Ohms)

931.86 620.94 311.67 157.32 80.08 33.65 18.33 12.01 26.90 53.52 133.15 264.89 860.11 3435.01

7389.53 4917.70 2448.04 1240.93 629.39 260.56 138.15 88.31 182.64 366.92 932.34 1919.70 7298.22 N/A

The value of W for Poly 2 for the process can have an important implication for resistor layout. To conserve power, it is often desirable to make the resistance of a matched pair as large as possible and minimum width is used in order to minimize the overall silicon area required. If the effect of W is not taken into account, a significant error in the resistor value may occur, resulting in expensive mask iterations. Since this process is typical of others found in the industry, we suspect that this sensitivity to Poly 2 width may be a common phenomenon. B. Estimation of L, W, and u. Following the methodology described in [1], linear equations were derived from Table II and estimates for L, W, and u were found by least squares surface fitting. The resulting values for L and W are significantly smaller than u, and can be neglected. As a result, (2) reduces to a linear relationship, where the standard deviation of resistance mismatch, Rm, is linearly related to the inverse square root of the area i.e. (L + L) multiplied by (W + W). This simplified form corresponds to the classic mismatch model described in [2] for transistors, and is in general agreement with the results reported in [3]. For the normalized data in Table II, our estimates are as follows: u_Poly1 = 13.3 /, u_Poly2 = 148.5 /. (9) (10)

Minimum Poly 2 width is 0.65m. Hence the 200x0.35m geometry is not applicable.

intellectual property in relation to the process, the standard deviations have been normalized to the 3x2.1m Poly 1 geometry with orthogonal orientation. The data indicates that there is very good agreement between the results for orthogonal and parallel orientations for each geometry. This suggests that this error source can be discounted as insignificant when modeling the mismatches in both layers. A. Estimation of , L, and W. Applying the methodology from [1] to the data shown in Table I produced the following results for the Poly 1 layer: _Poly1 = 6.6 /, LPoly1 = 0.82 m, WPoly1 = 0.03 m. (3) (4) (5)

By substituting (9) and (10) into (2) and neglecting the terms containing L and W, the models reduce to the following for Poly 1 and Poly 2 respectively: Rm_Poly1 = 2.86 / [(L + 0.82)(W + 0.03)], Rm_Poly2= 4.73 / [(L + 0.55)(W - 0.34)]. (11) (12)

Note that the resistivity value, _Poly1, is in strong agreement with the nominal value of six ohms per square for the process. Note also that the systematic width error, W, is quite small. This is to be expected since the width etching of Poly 1 determines the minimum transistor geometry and this parameter is tightly controlled during the manufacturing process. We repeated the procedure for the Poly 2 film, yielding the following results: _Poly2 = 44.4 /, LPoly2 = 0.55 m, WPoly2 = - 0.34 m. (6) (7) (8)

The resulting fit of the model to the data is shown in Fig. 3. As can be seen, the models fit the data with good accuracy. One important point to note in Fig. 3 is the change in the
TABLE II. SUMMARY OF STANDARD DEVIATION OF RESISTANCE MISMATCH BY ORIENTATION AND GEOMETRY. Length m 300 200 100 50 25 10 5 3 200 200 200 200 200 200 Width Poly 1 Poly 2 m Orthogonal Parallel Orthogonal Parallel 2.1 0.113 0.122 0.212 0.221 2.1 0.145 0.150 0.253 0.275 2.1 0.190 0.212 0.367 0.392 2.1 0.309 0.245 0.492 0.553 2.1 0.365 0.368 0.685 0.769 2.1 0.545 0.618 1.078 1.184 2.1 0.847 0.792 1.470 1.459 2.1 1.000 1.005 1.905 1.911 50.0 0.065 0.062 0.048 0.048 25.0 0.045 0.050 0.072 0.073 10.0 0.069 0.068 0.115 0.119 5.0 0.091 0.098 0.145 0.167 1.5 0.154 0.176 0.303 0.300 0.35 0.323 0.330 N/A N/A
Values normalized to 3x2.1m orthogonal Poly 1 value.

Note from (6) that the resistivity closely matches the nominal value of forty five ohms per square for Poly 2. Note also that the systematic width, W, for this layer is quite large compared to the minimum design rule of 0.65 m. In addition, it is negative, indicating that the width is narrower than the drawn width on average. This result is not unexpectedthe Poly 2 layer is deposited at a later stage in the process and is located on an oxide layer which is less uniform than that of Poly 1. Hence, its edge definition is more difficult to control.

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1.2

1 0.9

M ismatch Standard Deviation (Normalized)

1 0.8 Orthogonal 0.6 0.4 0.2 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Parallel Model

Length (normalized)

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 Poly 1 Poly 2 R_Poly 1 R_Poly 2

Reciprocal Square Root of Area

(a) Poly 1
2.5

Width (normalized)

Figure 4. Normalized loci to achieve 0.1% mismatch.

Mismatch Standard Deviation (Normalized)
2

1.5

Orthogonal Parallel Model

the differing resistivities. For each layer, the optimum selection for minimum area is the width and length corresponding to the point where the resistance line and mismatch curve intersect. Fig. 4 shows an example for Poly 1 (dark rectangle) and Poly 2 (semi-transparent rectangle). Since the resistivity for Poly 2 is almost eight times greater than for Poly 1, while its mismatch slope is less than two times worse, one might speculate that there is an area advantage to using Poly 2. However, this is not the casethe area of a Poly 2 resistor is always 2.74 times the corresponding area for Poly 1, regardless of the desired resistance, because the mismatch depends on area alone. VII. CONCLUSION We have examined two polysilicon layers in a commercial CMOS process and have demonstrated that they vary considerably in terms of resistivity and resistance mismatch performance. We have shown that the resistance mismatch model described in [1] can be successfully applied to the layers under examination. By estimating the model parameters, we have demonstrated that the effects of width and length etching can be neglected, and that the primary cause is the non-uniformity of the material in both cases. Finally, we have demonstrated that, regardless of the target resistance required, the use of the Poly 1 layer always gives a minimum area solution compared to Poly 2 on this process for a given mismatch standard deviation target. ACKNOWLEDGMENT The authors wish to express their gratitude to Mr. Pat Mc Guinness and his team for providing the test mask and data used as the basis of the analysis. REFERENCES
[1] [2] T. G. ODwyer, M. P. Kennedy, An enhanced model for thin film resistor matching, in Proc. IEEE ICMTS, March 2009, in press. M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, Vol. 24, Issue 5, pp.14331439, Oct 1989. R. Thewes, R Brederlow, C. Dahl, U. Kollmer, C. Linnenbank, B. Holzapfl, J. Becker, J. Kissing, S. Kessel, W. Weber, Explanation and quantitative model for the matching behavior of poly-silicon resistors, International Electron Devices Meeting, pp.771-774, 6-9 Dec. 1998.

0.5

0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Reciprocal Square Root of Area

(b) Poly 2 Figure 3. Mismatch model versus measured data.

x-axis values caused by the L and W effects for Poly 1. For the 3x2.1m geometry, using the drawn dimension alone results in a value of 0.40m-1 for the reciprocal square root of the area. However, this value becomes 0.35m-1 when L and W are taken into account. Therefore, applying a simple model such as [2] which uses the reciprocal square root of the drawn area would result in a significant error. This demonstrates the importance of incorporating the systematic etching effects as described in [1]. The effect is less pronounced in the case of Poly 2 since the L and W effects tend to cancel due to opposite signs. A second point to note in Fig. 3 is the difference in slopes between the Poly 1 and Poly 2 layers: the values are 2.86m and 4.73m respectively. This means that the resistor area required to achieve a particular target mismatch with the Poly 2 layer is 2.74 times larger than the corresponding area using Poly 1, since the required areas are related to the squares of the slopes. VI. RESISTOR DESIGN CONSIDERATIONS

To aid the task of designing resistors, it is useful to plot the models (11) and (12) with the width and length as the respective axes. An example is shown in Fig. 4 for 0.1% standard deviation of the mismatch for Poly 1 (black curve) and Poly 2 (dashed curve). To protect proprietary information regarding the process, both axes have been normalized. On this graph, the target resistance can be represented as a line having a given positive slope and an intercept of zero. The graph shows two lines corresponding to the same resistance value for Poly 1 (continuous black line), and Poly 2 (dashed black line). The difference in slopes corresponds to

[3]

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