Sun SPOT Main Board Technical Datasheet

Rev 8.0
Revision 8 manufactured after October 2010

Sun Labs October 2010

Oracle America, Inc. 16 Network Circle Menlo Park, CA 94025 Document Revision 2.0.1

Copyright2010,SunMicrosystems,Inc.Allrightsreserved. Copyright2010,Oracleand/oritsaffiliates.Allrightsreserved. Thissoftwareandrelateddocumentationareprovidedunderalicenseagreementcontainingrestrictionsonuseanddisclosureandareprotectedbyintellectual propertylaws.Exceptasexpresslypermittedinyourlicenseagreementorallowedbylaw,youmaynotuse,copy,reproduce,translate,broadcast,modify, license,transmit,distribute,exhibit,perform,publish,ordisplayanypart,inanyform,orbyanymeans.Reverseengineering,disassembly,ordecompilationof thissoftware,unlessrequiredbylawforinteroperability,isprohibited. Theinformationcontainedhereinissubjecttochangewithoutnoticeandisnotwarrantedtobeerrorfree.Ifyoufindanyerrors,pleasereportthemtousin writing. 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Lesinformationsfourniesdanscedocumentsontsusceptiblesdemodificationsanspravis.Parailleurs,OracleCorporationnegarantitpasquellessoient exemptesderreursetvousinvite,lecaschant,luienfairepartparcrit. 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The Basestation and Free Range SPOT

Features
400 MHz ARM 926ej-S Processor AT91SAM9G20 8Mbytes Flash Memory (4M x 16) 1Mbytes SRAM Memory (512K x 16) 802.15.4 Radio Transceiver (CC2420) USB 2.0 Full Speed 770mAhr Li-Ion Rechargeable Battery

Description
The Sun SPOT platform is the main processor board, eSPOT, running the Java Squawk VM and is an IEEE 802.15.4 wireless network node. An application board can be attached to the eSPOT main board The eSPOT has flexible power management and can draw from the rechargeable battery or the USB host, or be externally powered. The Sun SPOT is designed to be a flexible development platform, capable of hosting widely differing application modules. The Sun SPOT development kit, as supplied, contains two different configurations. One of the configurations includes a demonstration application module, the eDemo board. The configurations supplied in the kit are: Basestation SPOT - The basestation has an eSPOT main board without a battery or an application board. Power is supplied by a USB connection to a host workstation. The basestation serves as a radio gateway between other Sun SPOTs (and theoretically other 802.15.4 devices) and the host workstation. Free Range SPOT - This unit contains the main board with a rechargeable LI-ION prismatic battery and an example of an eSPOT daughterboard, the eDEMO board.

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Block Diagram
3.0V 1.0V 32.000KHz SPI 1 Atmel ATmega168V Power Controller Power Indicator 16.000MHz Vstby Attention BALUN

IRQ1

TI TPS79730 3.0V LDO

Chipcon CC2420 2.4GHz Transceiver SPI 0 Top Connector

USB Control Power Control

TI REF3025 2.5V Ref

Linear LTC2487 16-bit ADC Battery Voltage Current Sense

I2C

18.432MHz

SPI 1 USB Host I2C

Atmel AT91SAM9G20 USB Device

I2S USART GPIO Status LED

Vext Vstby 3.0V

3.7V 770mAh Li-ion battery 0.1

Linear LTC3455 Charger/Reg Vusb ESD Protection

3.0V 1.0V Vstby 3.0V

Adr, Data, RW, CS

Vext USB Mini-B

Analog ADG819 Switch

Alliance Memory AS6C8016-55 512K x 16 SRAM

Numonyx M29W640GB70 4M x 16 Flash

Signal Description
J2 Hirose DF17 Receptacle Pin 1,2 3 4 5 6 7 8 9 10 11 12 Signal Name V_EXT MISO1 USB_HOST_ N SCLK1 I2C_CLK MOSI1 I2C_DATA EXT_INn VSTBY CS_A0 Signal Type Power Input Bidirectional Output Output Output Bidirectional Input Power Output Description +5V +/-5% at 500mA input power to the SPOT USB Host Data Differential Positive SPI MISO (Master In Slave Out) data Channel 1 USB Host Data Differential Negative SPI SCLK (Clock) Channel 1 I2C SCK (Clock) SPI MOSI (Master Out Slave In) data Channel 1 I2C SDA (Data) External Interrupt (Active low) +3V at 35ma output power from the SPOT (always on) SPI Address A0. Address range 0 to 7. Must be stable

USB_HOST_P Bidirectional

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Pin 13 14 15 16 17 18 19 20 21 22 23 24

Signal Name P13 CS_A1 P15 CS_A2 VCC BD_SEL1n P19 BD_SEL2n P21 P22 P23 P24

Signal Type Multifunction Output Multifunction Output Power Output Multifunction Output Multifunction Multifunction Multifunction Multifunction

Description prior to BD_SELx. Can be programmed as GPIO (PB4), UART (TXD0) or Ethernet (EMDIO). SPI Address A1. Address range 0 to 7. Must be stable prior to BD_SELx. Can be programmed as GPIO (PB5), UART (RXD0). SPI Address A2. Address range 0 to 7. Must be stable prior to BD_SELx. +3V at 400mA output power from the SPOT (on when running, pulled to 0V during deep sleep) SPI board select 1 active low. Can be programmed as GPIO (PB30), UART (PCK0), Ethernet (EMDC or SSC (PCK0). SPI board select 2 active low. Can be programmed as GPIO (PA18), UART (TXD2), Ethernet (ERXER) or Timer (TCLK0) Can be programmed as GPIO (PA19), UART (SCK0), Ethernet (ETXCK), Timer (TIOA0) or SSC (TF0) Can be programmed as GPIO (PA15), UART (RXD2), Ethernet (ERX1), SD Card (MCCK) or SSC (RF0) Can be programmed as GPIO (PA16), UART (SCK2), Ethernet (ETXEN), SD Card (MCCDA), Timer (TIOB0) or SSC (TK0) Can be programmed as GPIO (PA14), UART (TXD3), Ethernet (ERX0), SD Card (MCDA3) or SSC (RK0) Can be programmed as GPIO (PA12), UART (SCK3), Ethernet (ETX0), SD Card (MCDA0) or SSC (TD0) Can be programmed as GPIO (PA17), UART (RXD3), Ethernet (ERXDV) or SC Card (MCDA2) Can be programmed as GPIO (PA13), UART (PCK1), Ethernet (ETX1), SC Card (MCDA1) or SSC (RD0) Ground Return

25 26 27 28

P25 P26 P27 P28

Multifunction Multifunction Multifunction Multifunction Power

29,30 GND

Pin numbers are for the Hirose DF17 interboard connector on the SPOT main board and connects to an application board like the eDEMO. The pin numbering for the signals is mirrored from the main board to the bottom mating connector of the application board.

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Theory of Operation
The eSPOT main board is host to a 32bit 400MHz ARM9 processor running a Java VM, 2.4GHz network radio transceiver and power management circuitry. The PC board measures 1.5" wide and 2.5" high. It is an eight layer 47mil thick FR4 board built to RoHS-6 compliance. It contains 244 components, 91 on top and 153 on bottom. Main Processor The main processor is the Atmel AT91SAM9G20 in a 247 pin fine pitch ball grid array. The processor is an ARM926ej-s and its package is 10mm x 10mm with 0.5mm ball pitch. The ARM9 processor core voltage is 1V and I/O voltage is 3V. It has 64K internal ROM which is not used and two internal 16K SRAM that are used. Peripherals actively used are USB 2.0 device, dual USART, three timer/counters, dual SPI interface, TWI (I2C) interface, JTAG TAP controller and external bus interface (EBI). The 133MHz EBI connects over a 16 bit data bus to an 8 megabyte Flash memory (4M x 16) and a 1 megabyte SRAM (512K x 16). The Ethernet MAC, USB 2.0 host, 10 bit ADC (3 channels) and SD/MMC interface are connected but not used. The SDRAM controller, image sensor controller, and watchdog timer are not used nor are all GPIO, ADC, or UART pins used. Two GPIO lines control a user-definable bicolor LED nearest to the USB connector. Green LED is controlled by Port A bit 27 (PA27) and Red LED is controlled by Port C bit 7 (PC7). Power is removed from the ARM9 during deep sleep and does not use the battery back up/real time clock portion of the internal power management module. The 8Mbyte Flash memory is Numonyx M29W640GB70 organized as 4M x 16 bits with 70nsec access time and 30nsec page access time (4 word pages). It is in a 6mm x 8mm 48 pin fine pitch ball grid array package. It is powered with 3V and shut down during deep sleep mode. The first 64KBytes are write protected externally from the power controller. There are 128 bytes of customer lockable extended block (one time writable) which is programmed with the 64-bit IEEE extended unique identifier by the factory. The IEEE EUI is read-only and is a concatenation of a 24-bit company code (OUI) with a 40-bit extension unique for each SPOT. The 1Mbyte SRAM is an Alliance Memory AS6C8016 with 55nsec access time. The SRAM is in 6mm x 8mm 48 pin fine pitch ball grid array package. It is powered by 3V at all times and will retain all memory contents during deep sleep. The basic memory map for the ARM9 is : Start End Description

0x00200000 0x00203FFF 16Kbyte Internal SRAM1 0x00300000 0x00303FFF 16Kbyte Internal SRAM2 0x10000000 0x107FFFFF 8Mbyte External Flash (CS0) 0x20000000 0x200FFFFF 1Mbyte External SRAM (CS1) 0xF0000000 0xFFFFFFFF Internal Peripheral IO

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Power Circuitry The SPOT can be powered by a rechargeable battery, USB power or externally connected 5V supply. USB power and/or externally connected power can charge the battery and run the rest of the SPOT. Most of the circuitry can be shut down for long periods of time to preserve battery (deep sleep). During deep sleep, the SRAM is kept powered to retain state so the SPOT can be woken up quickly and resume where the program left off. The SPOT uses a Linear Technology LTC3455 integrated battery charger and dual switcher in a 4mm x 4mm 24 pin quad flat package(QFN). The current mode step down switchers run internally at 1.5MHz and output 3.0V at 500mA max current (USBHP enabled) and the 1V core voltage at 200mA max current. The 3V switching regulator is similar to the LTC3406 switcher and the 1V core voltage switcher similar to the LTC3405 switcher. The 3V switcher can be turned off with the ON2 signal and the 1V switcher can be turned off using an external MOSFET connected to the switcher 1 feedback line through a 43.2K resistor and Vstby. The SPOT can go into deep sleep shutting off the switchers while still powered through USB to charge the battery. A low quiescent current (1.2uA) low dropout regulator (LDO), TI TPS79730 regulates the battery voltage to 3V for the always-on standby power, Vstby. An Analog Devices ADG819 SPDT solid state SPDT switch switches between the high current 3V switcher during run time and the 3V low current standby power from the LDO during deep sleep. The LDO has a power good line which goes low if the output voltage drops below 2.7V. Power good deasserted will hold the power controller in reset to prevent it from malfunctioning at low voltages. The SPOT battery is an external prismatic lithium-ion Sanyo LP523436D battery with 770mAh capacity and a nominal voltage output of 3.7V. It measures 38.5mm wide x 41.5mm high and 6.9mm thick. The battery is equipped with a Nexcon RPOPJ800 protection circuit and protects for over voltage (4.275V), over current (3A), and under voltage (2.3V). The battery connects through a Molex 51021-0200 two pin inline connector to a pigtail. The battery positive terminal is the red wire and negative terminal is the black wire. The black wire is not ground rather passes through a low side current sense resistor to ground. The mating battery connector is Molex 51047-0200. The power is managed by the power controller, an 8-bit 8MHz Atmel ATmega168 microcomputer powered by 3V standby voltage (Vstby). The power controller has a 32KHz crystal for real time clock providing date and time at millisecond accuracy (64bit Java millisecond time). The power controller communicates with the ARM9 over a SPI interface, SPI1 which is shared with the external SPI connection. This SPI interface is buffered by 74LVC3G34 which isolates the ARM9 from the active circuitry during deep sleep. The interrupt button connects to the power controller and is used to shutdown, wake-up and interrupt the ARM9. A bicolor LED (red/green) indicates power state of the ARM9. The power controller internal analog to digital converter (ADC) monitors switcher voltages, external voltage and USB voltage. It indicates a fault condition if they are more than 5% out of range. A Linear Technology LTC2487, an external 16-bit 4 channel ADC, is used to monitor battery voltage, current and ambient temperature. The ADC has a TI REF3025 as an external 2.5V reference with 0.2% accuracy. The reference and battery voltage divider can be switched off 10/30/10

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(REF_EN) by the power controller to minimize current. The LTC2487 interfaces to the power controller over I2C (TWI) and sleeps when I2C is inactive. The ADC uses a low side current sense resistor to measure the current into and out of the battery. The power controller monitors the health and state of the battery using this ADC. The battery ADC is read every 200ms cycling between current, voltage and temperature measurements. Voltage and temperature measurements are taken every 1.6 seconds and current measurements taken for all other 200ms intervals. The power controller sets the USB suspend (USB_ENn) and USB high power (USBHP) on the LTC3455 through instructions from the ARM9. The power controller must sequence power for the ARM9 on wake-up and shutdown. During deep sleep state, the power controller goes to sleep except for the real time clock counter. It is waken up by external interrupts like the pushbutton and every 256 milliseconds for updating the real time clock. On wake-up, the power controller temporarily delays external interrupts, turns on the switchers and watches 3V switcher (VCC) to become stable. Once VCC is stable, it enables back up voltage to the ARM9 and that causes the ARM9 to issue a power on internal reset. The external reset on the ARM9 is not used. Once power is stable and the internal ARM9 reset is active, the power controller enables its own SPI channel and external interrupts. On power off, the power controller notifies the ARM and waits a period of time so it can tear down any peripheral before shutting down. The tear-down time can be extended up to 32 seconds or terminated immediately. There is no tear-down for deep sleep. After tear-down, the backup voltage and switchers are shut off, and signals which might cause sneak paths, like FIQ, are shut down. The power controller manages a 32bit watchdog counter with 256ms ticks. The watchdog can be set between 256ms and about 34 years. If the watchdog is not reset at a regular interval from the ARM9, it will shutdown the ARM9, wait 150ms and restart it as a cold boot. The power controller does self test and fault analysis. While running, it continually scans voltage and current for out of range values.

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Symbol VCC Vcore Vusb Vext Idischarge Vbatt Vbatt Icharge

Target 3.0V 10% 1.8V 10% 5.0V 10% 5.0V 10% < 500ma > 3.25V > 3.05V < 5ma

Error states < 2.7V or > 3.3V power fault < 1.62V or > 1.98V power fault < 4.5V or > 5.5V power fault < 4.5V or > 5.5V power fault > 500ma power fault < 3.25V indicates low battery < 3.05V indicates dead battery > 5ma indicates charging

Network Radio The wireless network communications uses an integrated radio transceiver, the TI CC2420 (formerly ChipCon). The CC2420 is IEEE 802.15.4 compliant and operates in the 2.4GHz to 2.4835GHz ISM unlicensed bands. Regulations for these bands are covered by FCC CFR47 part 15 (USA), ETSI EN 300 328 and EN 300 440 class 2 device (Europe) and ARIB STD-T66 (Japan). Please check with country statutes for appropriate operation. The IC contains a 2.4GHz RF transmitter/receiver with digital direct sequence spread spectrum (DSSS) baseband modem with MAC support. Other features include separate TX and RX 128 byte FIFOs, AES encryption (currently not supported), received signal strength indication (RSSI) with 100dB sensitivity and transmit output power setting from -24dBm to 0dBm. Effective bit rate is 250kbps and chip rate is 2000kChips/s. Receive sensitivity is -90dBm. The digital control and data communications with the CC2420 use PIO port bits and the SPI channel. The CC2420 is a slave SPI bidirectional device addressed when RF_CS (PCS2) is asserted active low. PIO ports reset the CC2420 (RF_RST), power it down (RF_PWDOWN), or check the status of the receive FIFO (FIFO and FIFOP), clear channel assessment (CCA) and start of frame (SFD). There are 33 configuration and status registers, 15 command registers and two 8-bit registers for the separate transmit and receive FIFOs. The first byte sent to the CC2420 is the address made up of 6-bit address, RAM/Register select (Bit 7) and Read/Write select (Bit 6). Following bytes are data read from or written to the CC2420. The CC2420 is housed in a 7mm x 7mm 48pin quad leadless package (QLP or QFN). It is powered with +3.0V VCC supply. The CC2420 has an internal 1.8V low drop out regulator for powering the internal RF and analog circuitry. It consumes 20ma during receive operation and 18ma for 0dBm transmit. The frequency generation uses an accurate 16MHz crystal with 10ppm accuracy, 10ppm stability and 1ppm aging. The entire RF section is enclosed in an upper and lower RF shield and has modular FCC approval. 802.15.4 channel assignments are shown in the tables below. 10/30/10

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Channel 11 12 13 14 15 16 17 18

Center Frequency 2405MHz 2410MHz 2415MHz 2420MHz 2425MHz 2430MHz 2435MHz 2440MHz

Channel 19 20 21 22 23 24 25 26

Center Frequency 2445MHz 2450MHz 2455MHz 2460MHz 2465MHz 2470MHz 2475MHz 2480MHz

The output power can be adjusted by the PA_LEVEL register, a 6 bit field. PA_Level and output power are shown in the tables below. PA_LEVEL 31 27 23 19 Output Power 0dBm -1dBm -3dBm -5dBm PA_LEVEL 15 11 7 3 Output Power -7dBm -10dBm -15dBm -25dBm

For more information, see the CC2420 data sheet on the www.ti.com (RF/IF Components) The 802.15.4 standard can be retrieved from standards.ieee.org. Antenna The antenna is an inverted-F antenna printed on the top layer of the printed circuit board. It is tuned to 2450MHz and has a characteristic input impedance of 115 unbalanced. This is a folded monopole 1/4 wave with reasonable omnidirectional radiation. The antenna is matched to the balanced RF output of the CC2420 using a lumped-LC network. The RF output is also biased by the TXRX_SWITCH output of the CC2420 through a RF blocking filter. The antenna section of the eSPOT should be kept away from all metal objects. If mounted on a motherboard, there should be no PCB traces or power planes under or around the antenna section. If possible, the eSPOT should be mounted so that the antenna is located on the edge of the board. The FCC certification does not allow an external antenna to be connected to the eSPOT.

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Mechanical

eSPOT main board 1.50 wide x 2.50 length x 0.325 depth eSPOT basestation 1.67 wide x 2.80 length x 0.71 depth eSPOT freerange 1.67 wide x 2.80 length x 0.92 depth eSPOT basestation weight: 30g eSPOT freerange weight: 62g

Operating Characteristics
Absolute Maximum Ratings
Operating Temperature with battery charging 0C to 45C Operating Temperature with battery discharging -20C to 60C Operating Temperature without battery -20C to +75C Storage Temperature with battery -20C to +35C Storage Temperature without battery -40C to +85C eSPOT DC Current per I/O pin 8.0ma Maximum External/USB voltage 6.0V

DC Characteristics
Symbol Vext Vbatt Vusb Iusb Iext Ibatt Description External Voltage Battery Voltage USB Voltage USB Current Limit External Current Battery Current - no attached board Charge Current Vusb = 5.0V, USBHP = '1' Vusb = 5.0V, USBHP = '0 Vext = 5.0V, no eDemo Vext = 5.0V, with eDemo Deep Sleep Idle Normal Vusb = 5.0V, USBHP = '1' Vusb = 5.0V, USBHP = '0' Vext = 5.0V 55 20 65 TBD 50 400 50 500 Condition Min 4.5 3.1 4.5 440 60 Typ 5.0 3.7 5.0 475 80 Max 5.5 4.2 5.5 500 100 300 500 75 144 470 90 575 3.25 J2-11 Vstby = 3.0V VCC = 3.0V IOL= 0 to 8ma IOH= 0 to 8ma 0.2 2.6 0.3 2.7 25 380 0.4 2.8 Units V V V mA mA mA mA A mA mA mA mA mA V mA mA V V

Icharge

425

Vlow_batt Istby_max ICC VOL VOH

Low battery indication Externally available standby current Attached board current Output low level voltage Output high level voltage

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Symbol VIL VIH

Description Input low level voltage Input high level voltage

Condition

Min -0.3 2.0

Typ

Max 0.8 2.7

Units V V

AC Characteristics
Module SPI0 SPI1 to LED Controller SPI1 to external/power controller TWI USART Flash Memory (tcycle) SRAM (tcycle) USB Min Nom 1000 500 263 100 127 115200 75 60 4.09 8332800 Max Units Kbps Kbps Kbps Kbps Baud nsec nsec Mbps

The AC characteristics are measured values from the SPOT running default software. For specific AC characteristics, please consult the individual component datasheets.

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BATTERY WARNING

Do not short-circuit battery. A short-circuit may cause fire, explosion, and/or severe damage to the battery. Do not drop, hit or otherwise abuse the battery as this may result in the exposure of the cell contents, which are corrosive. Do not expose the battery to moisture or rain. Keep battery away from fire or other sources of extreme heat. Do not incinerate. Exposure of battery to extreme heat may result in an explosion. No other battery substitutions or different chemistry batteries should be used. Do not bypass the battery protection circuit. Dispose of batteries properly. Do NOT throw these batteries in the trash. Recycle your batteries, if possible.

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Federal Communications Commission Compliance

NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try and correct the interference by one or more of the following measures: Reorient or locate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. The Sun SPOTs are supplied with a shielded USB cable. Operation with a nonshielded cable could cause the Sun SPOTs to not be in compliance with the FCC approval for this equipment. The antenna used with this transmitter must not be colocated or operated in conjunction with any other antenna or transmitter; to do so could cause the Sun SPOTs to not be in compliance with the FCC approval for this equipment. Any modifications to the Sun SPOTs themselves, unless expressly approved, could void your authority to operate this equipment. FCC Declaration of Compliance: Responsible Party: Oracle America, Inc., 500 Oracle Parkway, Redwood Shores, CA 94065; Phone: US +1.650.506.7000; International +1.650.506.7000 FCC IDENTIFIER: UDM3011 This device complies with Part 15 of the FCC Rules. Operation is subject to the following conditions: this device may not cause harmful interference and this device must accept any interference received, including interference that may cause undesired operation. This device can be used as is (stand-alone) or as a module (part of a final host product). If the device will be used a module these rules must be followed: Caution: Exposure to Radio Frequency Radiation. To comply with FCC RF exposure compliance requirements, a separation distance of at least 20 cm must be maintained between the antenna of this device and all persons. This device must not be co-located or operating in conjunction with any other antenna or transmitter. Module 3011 and antenna tested with must be integrated in the end product in such a way that the end user cannot access the either the module, cables or antennas. The installer of this radio equipment must ensure that the antenna is located or pointed such that it does not emit RF field in excess of Health Canada limits for the general population; consult Safety Code 6, obtainable from Health Canada's website www.hc-sc.gc.ca/rpb.

Integrator must place a label outside their product similar to the example show below: OEM Manufacturer name
Contains transmitter module FCC ID: UDM3011 UPN: 1894B-3011 Model: 3011

10/30/10

Oracle SPOT Datasheet

-15-

eSPOT Rev 8.2.2

B B

Micro / Memory

Radio Chip

Power Supply

I/O Connector

USB

ATMega

Micro / Power

Micro_Memory.SchDoc C

Radio.SchDoc

Power_Supply.SchDoc

IO_Connector.SchDoc

USB.SchDoc

ATMega.SchDoc

Micro_Power.SchDoc C

Title Sunspot Wireless Network Processor Project Size: B Number: Revision: 8.2.2 Sheet 1 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:41 PM
5

2 U7A G3 B1 F2 C3 D3 B4
USB_DEV_P USB_DEV_N USB_HOST_P USB_HOST_N

3 SDCKE SDCK SDWE CAS RAS SDA10 DDP DDM HDPA HDMA HDPB HDMB TRST TMS TCK TDO TDI RTCK JTAGSEL RST PB31 / PCK1 PB30 / PCK0 PB29 / CTS1 PB28 / RTS1 PB27 / CTS0 PB26 / RTS0 PB25 / RI0 PB24 / DTR0 PB23 / DCD0 PB22 / DSR0 PB21 / RF0 PB20 / RK0 PB19 / RD0 PB18 / TD0 PB17 / TF0 PB16 / TK0 PB15 / DTXD PB14 / DRXD PB13 / RXD5 PB12 / TXD5 PB11 / RXD3 PB10 / TXD3 PB9 / RXD2 PB8 / TXD2 PB7 / RXD1 PB6 / TXD1 PB5 / RXD0 PB4 / TXD0 PB3 / SPI_CS0 PB2 / SPI1_SCLK PB1 / SPI1_MOSI PB0 / SPI1_MISO PC7 PC6 PC3 / SPI_CS3 / AD3 PC2 / AD2 PC1 / AD1 PC0 / AD0 CFIOW / BS3 / WR3 CFIOR / BS1 / WR1 CFWE / WE / WR0 CFOE / RD NANDWE NANDOE PC15 / IRQ1 / WAIT PC12 / IRQ0 / CS7 PC13 / FIQ / CS6 PC9 / CFCS1/ CS5 PC8 / CFCS0 / CS4 PC14 / NANDCS / CS3 PC11 / CS2 SDCS / CS1 CS0 CFW / PC10/ A25 SPI1_CS1 / PC5 / A24 SPI1_CS2 / PC4 / A23 A22 A21 A20 A19 A18 BA1 / A17 BA0 / A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 WR2 / BS2 / A1 BS0 / A0 B11 A16 U4 U3 T4 T3 A1 B2 A12 A13 B10 C10 G1 C12 B13 C11 B16 B15 B14 B3 A14 B12 A15 A17 A11 A10 B9 C9 A9 C8 A8 B8 C7 A7 B7 A6 D7 C6 A5 B6 A4 D5 C5 B5 C4 A3 A2 M2 P3 R3 P4 N4 L2 L3 K1 N3 M4 K4 K2 J1 H1 J2 J4 K3 H2 F1 H3 H4 E1 D1 C1 G2 F3 E2 E4 E3 D2 C2 D4 B17 C17
LED2

4 R36 U8
P28 P19 P26 CS_ROM OE WE BS1 WE OE WP VDDBU_EN

5 10K VCC FB8 VCC BYTE G4 F6 C39 0.1uF VCC_FLASH C117 1.0uF

VCC C40 1.0uF A

F1 G1 A4 B3 B4

CE OE WE VPP / WP RESET

R68 10K VCC R39 10K VCC A R40 10K VCC R41 10K VCC R42 10K VCC R43 10K

TRST TMS TCK TDO TDI JTAGSEL TRST TMS TCK TDO TDI RTCK TP JTAGSEL ARM_RST

600 1000mA

C13 D13 E14 E15 D14 C14 H16 G17 H15 J14 J16 G16 F16 G15 P10 P9 T8 R9 U8 R8 U7 P7 R6 T6 U6 U5 J15 H17 K15 J17 K17 L17 P6 R5 P5 T5 L15 L16 M17 N17 P17 K14 M16 M15 M14 N16 N14 N15 R17 L14 T17 P15 P16 R16 R15 T16 R14 T14 U13 U16 U14 U15 U12 U11 U10 U9 T12 R13 P14 T11 P13 T10 R12 R11 P12 T9 P11 R10

VSS VSS

H1 H6

(IRQ0) R71 100K

(RESET) VCC C4 D3 D4 C3 B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1 VSRAM VCC 5

ARM_FIQ P24

R61 0 R38 NL R74 NL R75 NL

BD_REV3 BD_REV2 BD_REV1 BD_REV0

TP

CS_RAM CS_ROM

LED2 G B VCC A R C1 RED/GRN LED C2 R49 270 R50 270

LED2 LED1

CCA FIFO RF_PDOWN RF_RST CS_A2 CS_A1 CS_A0 FIFOP SPARE1 P25 P27 P28 P26 P22 P24 BD_REV2 BD_REV3

R52 10K VCC R53 10K VCC C81 0.1uF SCLK1 C

SCLK1

RF_CS RF_PDOWN

U13A SN74LVC3G34 7 1
ARM_SCLK

P27 P25 P23 P21 RXD1 TXD1 P15 P13 AVR_CS ARM_SCLK ARM_MOSI ARM_MISO P22 P24

A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 BS0

A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

READY / BUSY A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 4M x 16 FLASH

A3

BUSY

BUSY

R48 VCC 10K

WP

R65 10K

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 M29W640GB70

G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U11
VDDBU_EN

(RESET) 1

IN2

CS_RAM

IN1

GND

C112 0.1uF

VDDBU_EN = LOW -> Y = HIGH VDDBU_EN = HIGH -> Y = CS_RAM

IN0 74AUP1G57
BS1 BS0 OE WE

4 U12 B5 B2 A1 A2 G5 CE UB LB OE WE VSS VSS E6 D1 512K x 16 SRAM VCC VCC E1 D6

U13B SN74LVC3G34 MOSI1

MOSI1

ARM_MOSI

U13C SN74LVC3G34 MISO1

MISO1

SFD LED1 P22 P23 I2C_CLK I2C_DATA P13 P19 P22 P21 P27 P24 P23 P25 P28 P26 P25 P27 P28 P23 P24 P26 BD_REV1 BD_REV0 RF_CS SCLK0 MOSI0 MISO0

ARM_MISO

R56 10K VCC R57 10K VCC R58 10K VCC D

BD_SEL2 BD_SEL1 MISO1

PC31 / D31 PC30 / D30 PC29 / D29 PC28 / D28 PC27 / D27 PA31 / TXD4 / SCK0 PC26 / D26 PA30 / RXD4 / SCK2 PC25 / D25 PA29 / SCK1 PC24 / D24 PA28 / TIOA2 PC23 / D23 PA27 / TIOA1 PC22 / D22 PA26 / TIOA0 PC21 / D21 PA25 / TCLK0 SPI1_CS3 / PC20 / D20 PA24 / TWCK SPI1_CS2 / PC19 / D19 PA23 / TWD SPI1_CS1 / PC18 / D18 PA22 / ETXER / ADTRG SPI0_CS3 / PC17 / D17 PA21 / EMDIO SPI0_CS2 / PC16 / D16 PA20 / EMDC PA19 / ETXCK D15 PA18 / ERXER D14 PA17 / ERXDV D13 PA16 / ETXEN D12 PA15 / ERX1 D11 PA14 / ERX0 D10 PA13 / ETX1 D9 PA12 / ETX0 D8 PA11 / ETX3 / MCDA3 D7 PA10 / ETX2 / MCDA2 D6 PA9 / MCDA1 D5 PA8 / MCCK D4 PA7 / MCCDA D3 PA6 / MCDA0 D2 PA5 / CTS2 D1 PA4 / RTS2 D0 PA3 / SPI0_CS0 PA2 / SPI0_SCLK WKUP PA1 / SPI0_MOSI SHDN PA0 / SPI0_MISO AT91SAM9G20 3

C118 1.0uF FB9 VCC_SRAM C41 0.1uF C109 0.1uF 600 1000mA

VSRAM C42 1.0uF C

BD_SEL2 BD_SEL1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

H1 D3 E4 F4 F3 G4 G3 H5 H4 H3 H2 D4 C4 C3 B4 B3 A5 A4 A3

A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 AS6C8016 55ns

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

G1 F1 F2 E2 D2 C2 C1 B1 G6 F6 F5 E5 D5 C6 C5 B6

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Title Micro / Memory Size: B Number: Revision: 8.2.2 Sheet 2 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
4

Time: 1:41:41 PM
5

U1 CC2420 C1 RF_RST RF_CS RF_PDOWN MISO0 MOSI0 SCLK0 FIFO FIFOP CCA SFD
RF_RST RF_CS RF_PDOWN MISO0 MOSI0 SCLK0 FIFO FIFOP CCA SFD

ANT1

21 31 41 34 33 32 30 29 28 27 47 46 R1 43.2K 1% 45 5 9 19 22 23 24 49

RESET CS VREG_EN SO SI SCLK FIFO FIFOP CCA SFD

TXRX_SWITCH

7 5.6pF L1 5.6nH C2 C3 GND 0.5pF L2 7.5nH 5.6pF B L3 C4 0.5pF 7.5nH

RF_P

RF_N ATEST1 ATEST2 R_BIAS GND GND DGND_GUARD DGND DSUB_PADS DSUB_CORE XOSC16_Q2 DIE_PAD VCO_GUARD AVDD_VCO AVDD_PRE AVDD_RF1 AVDD_XOSC DVDD_RAM AVDD_ADC DVDD_ADC DGUARD VREG_OUT AVDD_CHP AVDD_SW AVDD_RF2 AVDD_IF2 AVDD_IF1 VREG_IN DVDD3.3 DVDD1.8

F ANT C5 22pF Y1 16 MHz +/- 10 ppm TSX-3225 38 C6 22pF

XOSC16_Q1

39

25

43

42

26

35

17 18 20

10 14 15

1 2 3 4

48

44

FB1 VCC 600 100mA R2 2 1% C18 10uF FB3 600 100mA C7 0.01uF 0.01uF C8 0.01uF C9

FB2 600 100mA C10 0.01uF C11 0.01uF C12 0.01uF C13 0.01uF C14 0.01uF

C15 0.01uF

C16 10uF

C17

0.01uF

37

Title Chipcon CC2420 Transceiver Size: B Number: Revision: 8.2.2 Sheet 3 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:41 PM
5

USB_PWR_MON

USB_PWR_MON

R66 3.32K R67 1% 3.32K 1%

V_USB

C88 10uF B U9 USB_DEV_N

USB_DEV_N

R55 1 C89 B J3 1 2 3 4 5

5 6 4 STF202

2 1 3

0.1uF

USB_DEV_P

USB_DEV_P

USB Mini Type B

Title USB Device Size: B Number: Revision: 8.2.2 Sheet 4 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:41 PM
5

V_EXT TS1 SMF5.0

J2 V_EXT USB_HOST_P USB_HOST_N I2C_CLK I2C_DATA

USB_HOST_P USB_HOST_N I2C_CLK I2C_DATA

1 3 5 7 9 11 13 15

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 DF17-30-R

V_EXT
MISO1 SCLK1 MOSI1 EXT_INT CS_A0 CS_A1 CS_A2 BD_SEL1 BD_SEL2 P22 P24 P26 P28

MISO1 SCLK1 MOSI1 EXT_INT CS_A0 CS_A1 CS_A2 BD_SEL1 BD_SEL2 P22 P24 P26 P28

TDI TDO TMS TCK TRST

TDI TDO TMS TCK TRST

PAD1 PAD2 PAD3 PAD4 PAD5

VSTBY P13 B P15

P13 P15

MISO1 MOSI1 SCLK1 RXD1 TXD1

MISO1 MOSI1 SCLK1 RXD1 TXD1

B PAD6 PAD7 PAD8 PAD9 PAD10

VCC P19 P21 P23 P25 P27

P19 P21 P23 P25 P27

17 19 21 23 25 27 29

SPARE_PAD1 VCC AVR_RES

AVR_RES

PAD11 PAD12 PAD13

SPARE_PAD2

TOP CONNECTOR

PAD14

C PAD15

V_EXT V_USB
FID1

PAD16 PAD17

FID1 Fiducial SDA

SDA SCL

PAD18 PAD19

FID2

FID2 Fiducial FID3 Fiducial FID4 Fiducial

SCL

FID3

FID4

Title USB Size: B Number: Revision: 8,2.2 Sheet 5 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:41 PM
5

LED1 G C2 A VSTBY A R C1 RED/GRN LED R51 NL VSTBY AVR_CS MOSI1 MISO1 SCLK1
AVR_CS MOSI1 MISO1 SCLK1

R22 270 R25 270 U5 12 13 14 15 16 17 PB0 / ICP1 PB1 / OC1A PB2 / SS PB3 / MOSI / ISP_SDI PB4 / MISO / ISP_SDO PB5 / SCK / ISP_CLK RXD / PD0 (BATT_MON_EN) TXD / PD1 INT0 / PD2 INT1 / PD3 T0 / XCK / PD4 T1 / PD5 AIN0 / PD6 7 Y2 32.000 KHz PB6 / XTAL1 AIN1 / PD7 AREF PB7 / XTAL2 30 31 32 1 2 9 10 11 20 0.1uF 8 VCC 8 S2 VDD
EN_SWITCHERS VDDBU_EN PWRON WP ARM_FIQ REF_EN EXT_INT

VSTBY A R45 VSTBY 10K ARM_FIQ REF_EN EXT_INT SW1 EVQ-P7C01K R23 10K

EN_SWITCHERS VDDBU_EN PWRON WP

Active High Active High Active High Normally Low VSTBY 2 U10 S1 D 1 4 3 C91 0.1uF C98 10uF C33 10uF VSRAM B HIGH = ON LOW = OFF

C30

22pF

C31 B C32 22pF

EXT_PWR_MON USB_PWR_MON USB_EN VCC USB_HP SDA R32 1.00K 1% V = 0.7685*Vcc (3V = 2.306V) C R34 3.32K 1% SCL AVR_RES

EXT_PWR_MON USB_PWR_MON USB_EN USB_HP

23 24 25 26 27 28 29 19

PC0 / ADC0 (TEMP) PC1 / ADC1

AVCC GND

18 21 C34 0.1uF FB6 600 100mA

VDDBU_EN R26 100K

IN ADG819 IN=0: S1 -> D IN=1: S2 -> D

GND

PC2 / ADC2 PC3 / ADC3

(I_CHRG) (I_DSCHRG) VCC VCC 4 6 3 5 0 C35 0.1uF C36 0.1uF

SDA SCL
AVR_RES VCC_MON

PC4 / ADC4 / SDA(V_BATT) PC5 / ADC5 / SCL PC6 / RESET ADC6 ADC7 ATmega168V GND GND (SLUG) GND

FB7 600 100mA V_MAX VSTBY C90 0.1uF BATT

D3
LDO_PWR

R28 1K VCORE

BAT43W D2 4 BAT43W C37 0.1uF 2 U6 V_IN V_OUT 5 C38 1.0uF GND TPS79730 3.0V 10mA VSTBY 100K C82 1000pF PG 1 VSTBY (3.0V) C

22

R29 AVR_RES

AT91SAM9G20 Startup Sequence:

Set PWRON = High Set EN_SWITCHERS = High Wait for 1.0V and 3.0V to stabilize Set VDDBU_EN = High Wait 150 us for RC clock to start

Title ATmega Size: B Number: Revision: 8.2.2 Sheet 6 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:42 PM
5

VCC

FB10 600 VDD_IOM 1000mA C48 0.1uF C51 10uF C52 0.1uF C55 0.1uF C58 0.1uF D11 G4 J3

U7B VDD_IOM VDD_IOM VDD_IOM

AT91SAM9G20 VDD_CORE VDD_CORE VDD_CORE VDD_CORE D9 H14 M1 T13 FB14 600 VCORE C66 0.1uF C69 0.1uF C72 0.1uF C76 0.1uF VDD_CORE

FB16 600 1000mA C77 10uF

VCORE

C80 0.1uF

VCC

FB11 600 VDD_IOP 1000mA C49 0.1uF C53 10uF C56 0.1uF C59 0.1uF P8 U17 VDD_IOP VDD_IOP GND_PLL T2 VDD_PLL N2 C63 0.1uF C70 0.01uF VDD_PLL

100mA R70 1 C73 4.7uF C78 0.1uF

VCORE

Q4 BSS138

D16 C61 0.1uF E16

VDD_BU

VDD_PLL

P2 C64 0.1uF

R63 VDDBU_EN 10K B VCC FB12 600

GND_BU

GND_PLL

U1 FB15 600 B VCC

R4 100mA R62 1 C57 0.01uF C60 0.1uF U2 C62 0.1uF R2

VDD_ANA AD_VREF

VDD_OSC

L4 100mA R76 1 C67 0.1uF C71 0.01uF C74 4.7uF C79 0.1uF

C50 0.1uF

C54 4.7uF

GND_ANA

NC NC NC NC

C15 D15 R1 T1

FB13 600 D6 D8 F4 G14 H8 H9 H10 J8 J9 J10 K8 K9 K10 K16 L1 M3 R7 T7 T15 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XOUT XIN VDD_USB C16 1000mA C65 0.1uF GND_USB GND_USB D10 D12 C68 10uF

VCC

C75 0.1uF

OSCSEL

F14

R64 10K

BMS XOUT32

F15 BMS

R54 10K

XIN32

TST

F17

R69 10K

E17

P1

N1

XOUT32

Y3 18.432 MHz

C86 33pF

C87 33pF

XIN32

D17

D TP TP

Title AT91RM9200 Power Size: B Number: Revision: 8.2.2 Sheet 7 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010
1 2 3 4

Time: 1:41:42 PM
5

V_EXT V_EXT R3 3.32K 1% 11 C19 10uF R6 1.24K 1% MODE V_USB V_USB R8 1 VCC C21 10uF CHRG USB_EN B Q2 IRLML6402 BATT 1 R33 100K C43 0.1uF U3 V_IN V_OUT 2 PWRON R10 10K R44 NL R72 10K 22 24 PWRON ON HSI HSO HSON 13 14 15 R11 10K R12 R47 3.4K 1% 10.2K/3.4K is 4:1 ratio (0.25*Vbatt) FS = 1.25V FS Battery = 5V 2.49K 1% C23 3 PAD20 V_REF C Battery + J1 1 BATT VSTBY AO C44 1.0uF 14 13 PAD21 Differential Input Range: (Vref / Gain) * 0.5 Vref = 2.5 Gain = 16 Input Range = 0.07813V Ima = ADC_value * 781.3 / 65535 VBATT R24 1K R16 0.1 1% 100ppm R27 1K R30 1K R31 1K C45 0.1uF 12 C46 10uF C47 0.1uF R59 10K U4 LTC2487 5 4 SDA SCL R60 10K C26 10uF R20 10K 25 16 AI FB1 1 R35 43.2K SW1 17 7 L5 4.7uH C27 10pF R18 25.5K 1% R21 102K 1% FB5 600 1000mA C28 10uF C29 10uF R17 1K VCORE 1.0V 200mA BATT 9 VBAT 3.0V = 512mA 0.1uF TIMER FB2 18 2 USB_HP
USB_HP USB_EN

R5 1 A

D1 MBR130 U2 WALLFB V_MAX 10 V_MAX C20 10uF 21 19

R4 3.32K 1% EXT_PWR_MON R7 3.32K 1% A

USB

ON2

EN_SWITCHERS

R9 10K 4 20 B 5 USBHP PBSTAT 23 CHRG

SUSPEND

RST

R46 10.2K 1%

GND REF3025 2.5V 0.15%

REF_EN R37 100K

Q3 2N7002

VBATT PROG SW2 12 L4 4.7uH C22 10pF R14 226K 1% R15 80.6K 1% FB4 600 1000mA C24 10uF C25 10uF C VCC 3.0V 500mA

eSPOT PWR Battery 3 BATT_RET

REF+

REF-

Vcc

8 9 10 11

CH0
IN+

SDA
4 Ch Mux IN-

SDA SCL

GND (SLUG) LTC3455 VSTBY

Q1 IRLML6402

CH1 CH2 CH3

SCL
16 BIT ADC

VBATT

CA0
Temp Sensor

2 3 1 EN_SWITCHERS HIGH = ON LOW = OFF D

COM

GND

SLUG

CA1 Fo

15

LOGO1 ORACLE PCB LOGO

Title Power Supply / Battery Charger Size: B Number: Revision: 8.2.2 Sheet 8 of 8 16 Network Circle Menlo Park, CA 94025
(C) 2010 Oracle Corporation

Date: 9/16/2010

Time: 1:41:42 PM
5