MOS inverters charateristic curve.

To:
Dr : Rania Fouad Ahmed

Mohammed Gomaa Abd-Elbasier 4th Comm. Dept.

Assignment 1: CMOS Inverter

A CMOS inverter circuit consists of two opposite polarity MOSFETs the NMOS and the PMOS with their gates connected together at the input ,a common gate is called a complementary pair, which gives us the C in CMOS., The inverter output voltage is taken from the common drain terminals. The transistors are connected in a manner that ensures that only one of the MOSFETs conducts when the input is stable at a low or high voltage.

M2 Mbreak P VOU T M1 Mbreak N 5 V2

V3 5

Codes:
there are 4 nodes: Vin, Vout, Vdd, and GND. Vout will be node 3

Vin will be node 2 Vdd will be node 1 GND will be node 0.

-------------------------------------------------.model NTRAN NMOS (VTo=0.5, KP=50u) .model PTRAN PMOS (VTo=-0.5, KP=20u) M2 3 2 1 1 PTRAN W=10u L=2u M1 3 2 0 0 NTRAN W=4u L=2u Vdd 1 0 5 Vin 2 0 0 .dc Vin 0 5 .1 .op .probe .end

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Simulation

Assignment 2: Resistive Load Inverter

The resistive load is straight forward but unattractive. Circuit resistances in integrated circuits must be implemented using the resistivity of the various conducting regions. This resistivity is usually too low for this to be an economic solution. The inverter consists of a single inverting transistor, together with a load to convert the change in transistor current into the voltage change suitable for the following gates. This arrangement is not often used because of the large space requirements of resistors produced in a silicon substrate.

Codes:
there are 4 nodes in this circuit: Vin, Vout, Vdd, and GND. Vout will be node 3 Vin will be node 2 Vdd will be node 1 GND will be node 0.
----------------------------------------.model NTRAN NMOS (VTo=0.5, KP=50u) M1 3 2 0 0 NTRAN W=4u L=2u Vdd 1 0 5 Vin 2 0 0 R1 1 3 1k .dc Vin 0 5 .01 .op .probe .end --------------------------------------------------------------

Simulation:

If (W=10u and L=2u)

Assignment 3: Enhancement MOS Inverter

with one voltage supply

enhancement inverter circuit consists of two NMOS The inverter output voltage is taken from the common terminal. we connet the drain of the load nmos and its gate with the supply voltage vdd to ensure that the load nmos stay in the saturation region at any value of supply voltage as: Vgs=Vdd-Vout && Vds=Vdd-Vout Then Vds > Vgs-Vt0

Codes:
there are 4 nodes in this circuit: Vin, Vout, Vdd, and GND. For this circuit, Vout will be node 3, Vin will be node 2, Vdd will be node 1, and GND (by default in PSPICE) is node 0. ---------------------------------------------.model NTRAN NMOS (VTo=0.8, KP=45u) M2 1 1 3 3 NTRAN W=2u L=2u M1 3 2 0 0 NTRAN W=16u L=2u Vdd 1 0 5 Vin 2 0 0 .dc Vin 0 5 .01 .op .probe .end

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Simulation:

Assignment 4: Enhancement MOS Inverter with two voltage supply

enhancement inverter circuit consists of two NMOS The inverter output voltage is taken from the common terminal. we connet the drain of the load nmos with the supply voltage vdd and connect the gate of the load with Vgg which is larger than Vdd to ensure that the load nmos stay in LINEAR region at any value of supply voltages as: Vgs=Vgg-Vout && Vds=Vdd-Vout && Vgg >Vdd Then Vds < Vgs-Vt0

Codes:
there are 5 nodes in this circuit: Vin, Vout, Vdd, Vgg and GND. Vout will be node 3 Vin will be node 2 Vdd will be node 1 Vgg will be node 4 GND will be node 0. ----------------------------------------------.model NTRAN NMOS (VTo=0.8, KP=45u) M2 1 4 3 3 NTRAN W=2u L=2u M1 3 2 0 0 NTRAN W=16u L=2u Vdd 1 0 5 Vin 2 0 0 Vgg 4 0 8 .dc Vin 0 5 .01 .op .probe .end

Simulation:

Assignment 5: deplation load MOS Inverter

Deplation load mos inverter circuit consists of two MOSFETs the driver is nmos and the load is deplation mos The inverter output voltage is taken from the common terminal. we connet the source of the load dmos and its gate connected with the vout to ensure that Vgs of the load equal zero

Codes:
there are 4 nodes in this circuit: Vin, Vout, Vdd and GND. Vout will be node 3 Vin will be node 2 Vdd will be node 1 GND will be node 0.

-------------------------------------------.model dTRAN NMOS (VTo=-1, KP=25u) .model NTRAN NMOS (VTo=0.8, KP=25u) M2 1 3 3 0 dTRAN W=1u L=3u M1 3 2 0 0 NTRAN W=4u L=2u Vdd 1 0 5 Vin 2 0 0 .dc Vin 0 5 .1 .op .probe .end

Simulation: