Xilinx EDK Tutorials and Notes12 by Jonathon W.

Donaldson Sandia National Laboratories

1 Website: 2 This

https://rm-rfroot.net/les/edk tut/edk tut.pdf A A A A document was typeset with L TEX 2 . L TEX 2 is an extension of L TEX. L TEXis a collection of macros for TEX.

Contents

List of Tables List of Figures List of Acronyms 1 2 3 4 Introduction Creating an EDK Project from Scratch Simulating Your EDK Design

3 4 6 7 8 23

Adding Custom IP To Your EDK Design 27 4.1 Manually Changing the Number of S/W Accessible User-Registers . . . . . . . . . . . . . . 27 4.2 Creating your own MUI Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

List of Tables

List of Figures

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10

Creating a New XPS Project . . . . Adding the Required IP . . . . . . . Bus Interface List . . . . . . . . . . JTAG and System Bus Connections DCM Port Connections . . . . . . . Reset Controller Port Connections . PPC 405 Port Connections . . . . . PLB and OPB Port Connections . . System Address Mapping . . . . . . Add Software Application Dialog .

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9 10 12 13 14 15 16 17 18 19

List of Acronyms

BRAM BSB DCM DCR DDR DPLB EDK

Block Random Access Memory, 11, 18, 19 Base System Builder, 22 Digital Clock Manager, 10, 1215, 23 Device Control Register, 11, 15 Double Data Rate, 11 Data Processor Local Bus, 11 Embedded Development Kit, 711, 15, 1720, 2325, 28 Field Programmable Gate Array, 7, 8, 10, 12, 13, 15, 1921 Field Programmable Gate Arrays, 7, 8 Graphical User Interface, 9, 15 International Business Machines, 10 Interface, 11, 18 Intellectual Property, 811, 28 Instruction Processor Local Bus, 11 Integrated Software Environment, 23 Joint Test Action Group, 7, 10, 11, 19, 20 Multi-Gigabit Transceiver, 23 Microprocessor Hardware Specication, 8, 9, 13, 15, 23, 25 Microprocessor Peripheral Description, 28 Microprocessor Software Specication, 9 On-Chip Memory, 21

FPGA FPGAs GUI IBM IF IP IPLB ISE JTAG MGT MHS MPD MSS OCM

OPB OS PAO PLB PPC PPC440 PPC405 PPM SDK UART UCF USB XMP XPS XST XUPV2P

On-Chip Peripheral Bus, 10, 11, 13, 15, 20 Operating System, 20 Peripheral Analyze Order, 24, 25, 28 Processor Local Bus, 10, 11, 13, 15, 18 PowerPC, 711, 13, 14, 1719 Power PC 440, 10 Power PC 405, 810, 13, 14, 18 Parts Per Million, 23 Software Development Kit, 18 Universal Asynchronous Receiver-Transmitter, 7, 11, 15, 1720, 26 User Constraints File, 15 Universal Serial Bus, 7 Xilinx Microprocessor Project, 8 Xilinx Platform Studio, 7, 18 Xilinx Synthesis Tool, 15 Xilinx University Program Virtex-II Pro Development Board, 7, 8, 13, 20

CHAPTER

Introduction

This document will teach you a bit about the Xilinx Platform Studio (XPS) and Embedded Development Kit (EDK) tools and how to get a project up and running from scratch without using the Base System Builder wizard. This tutorial is based on the Xilinx University Program Virtex-II Pro Development Board (XUPV2P) which can be purchased at http://www.digilentinc.com. The board only costs $300 for students, but is $1600 for commercial use. If you dont have this board available dont worry. The actual board doesnt matter just so long as you have a board with a Xilinx Field Programmable Gate Array (FPGA) and a Universal Asynchronous Receiver-Transmitter (UART) port. In my experience working with development boards from various vendors, the XUPV2P is quite possibly the best one I have ever had the privilege of using. In my opinion, it is the most versatile and accessible learning tool you could ask for when beginning to work with Field Programmable Gate Arrays (FPGAs). Additionally, you dont need to buy one of the $125+ dollar Xilinx Joint Test Action Group (JTAG) Programming cables because they provide the Universal Serial Bus (USB) JTAG programming cable chip embedded directly onboard. You can simply plug in a standard USB device cable from your PC to the board. The only other development board Ive worked with that outranks the XUPV2P is the Xilinx ML310, which is essentially a 100% customizable dual-core PowerPC (PPC) processor motherboard. Unfortunately, the board is prohibitively expensive, therefore it lacks the accessibility aspect of the XUPV2P. Fortunately, however, I own two of them, so if you happen to be lucky enough to own an ML310 be sure to look for another tutorial on that board in the coming months. And I neglected to mention that the ML310 has also been discontinued by Xilinx. But no worries, they have replaced it with an even better (albeit more expensive) board named the ML410. The ML410 is essentially the exact same board as the ML310 except that it has a Virtex-4 FX in place of the ML310s Virtex-II Pro. This tutorial was created using EDK 8.2i, but I have successfully followed the same steps (with very minor differences) using Xilinx EDK 9.2i. It is necessary to learn how to create an EDK project from scratch since Xilinx removed Virtex-II Pro (and some Spartan) support from the BSB wizard in version 9.2i. Therefore, if you are planning on using any Virtex-II pro board at all you will be without any wizard help. The process of creating an EDK project from scratch is extremely tedious (you will get an appreciation for Xilinxs BSB wizard very quickly), but I promise by the end of this tutorial you will have learned a lot more about the inner workings of EDK and hopefully put EDK to some more advanced use. If you have any comments/questions/requests regarding this tutorial feel free to contact me at webmaster [a t] rm-rfroot [d o t] net.

CHAPTER

Creating an EDK Project from Scratch

The project we create in this chapter will ultimately be congured to display Hello World! over the boards standard RS-232 serial port using a very simple C application. Yes, the resulting output of the project is trivial, but I promise you will learn a lot if youre new to EDK. If at anytime you would like to view my source code for the design you can get them from the following links. I have also created a basic EDK project layout for the Xilinx ML325 board as well (i.e. not for the XUPV2P). rm-rfroot.net/les/edk tut/from scratch 8 2i.zip rm-rfroot.net/les/edk tut/from scratch 9 2i.zip rm-rfroot.net/les/edk tut/from scratch ml325.zip 1. When EDK opens select Blank XPS Project. No wizard for us! ;-) Click OK. 2. Pick a location for your Xilinx Microprocessor Project (XMP) (be sure the path does NOT contain spaces!) in the new dialog that opens. 3. Choose the correct Target device options for the FPGA youre using. 4. Leave the Microprocessor Hardware Specication (MHS) le and Repository paths blank. Some Xilinx boards (e.g. XUPV2P/ML310/ML410) will come with there own additional Intellectual Property (IP) core libraries. These libraries contain IP cores that are not available in the Xilinx standard library that comes with the EDK installation. For example, the XUPV2P board comes with an AC97 codec, a PS/2 driver, etc. for special hardware specic to that board. We are not going to use them here because we wont need them to get a simple design up and running. Click OK. See image 2.1 below. 5. You will then be presented with the default EDK interface. Your initial setup might come up with an extra EDK design ow window and/or a block diagram window but you can just close them. Lets follow EDKs instructions presented in the console log window and start adding some useful IPs to our design. 6. Expand the Processor list under the IP Catalog tab in the left panel, right click on the ppc405 and select Add IP.1 This is shown in image 2.2. Since the xc2vp30-ff896 FPGA contains two Power
1 If

youre using a Virtex-5 then the processor selection will be ppc440.

Figure 2.1: Creating a New XPS Project PC 405 (PPC405) processors, EDK will require that we add IP cores2 for both of them even if we do not intend on using both in our design. EDK wont complain if you dont add a second IP for the other PPC405 just yet, but it will be sure to error out if you dont add it before you try to implement the design. So just repeat this step now and save yourself the trouble. 7. Our fancy new processor isnt going to be much use unless we connect it to some components so lets do that now. Add the following IP cores in the same fashion as you did for the PPC405: proc sys reset - This is a reset control block which is very useful (and necessary). It has a port for an external reset input which, when toggled, will perform resets to the internal PPC components, the processor bus structures, and the peripherals in a very specic order. It also has internal reset ports which connect to the processor itself. The PPC has its own set of reset request signals which can tell the reset control block to reset the system as well.3 Also note that the method of adding this IP is one of the difference for EDK versions prior to 9.2i. If you are using EDK 9.2i or later this core will not be readily available in the IP Catalog list. But never fear, the IP can still be added manually using the MHS le.4 To do this, double-click on MHS
2 Note that the PPC IP we are adding here is not the actual netlist data for the PPC core. The PPC cores in Xilinx FPGAs are hard cores and are immersed directly in the FPGA fabric. The IP we are adding are merely wrappers that allow us to interface with the processor. 3 For more information on the reset control block right-click on it in the IP Catalog list and select View PDF Datasheet. See Xilinx document DS406 for more information on the reset block. See the Reset Interface section of Xilinx document UG018 for more information on the PPC reset signals. 4 In fact, when you add IP using the Graphical User Interface (GUI) method the only thing EDK is doing is updating the MHS and/or the Microprocessor Software Specication (MSS) les.

Figure 2.2: Adding the Required IP File under the Project tab in the left panel and add the following lines. BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a END jtagppc cntlr - This block is a wrapper that activates the FPGAs built-in JTAGPPC primitive. It allows us to interface to the PPC for debugging (e.g. single-stepping the process, etc) via the chips JTAG port. Even if you do not plan on debugging your design (yeah, right) EDK requires that you add this IP. Note that you can connect up to two PPC primitives to this controller block so we only need one. dcm module - regardless of whether or not you have the exact oscillator frequency you plan on using in your design you will still need a Digital Clock Manager (DCM) module for two reasons: (a) the proc sys reset module requires a DCM Locked output signal for its logic and (b) its good design practice to buffer your external input clock and running your external clock through a DCM automatically does this for you and makes your design more versatile if different clock rates are required in the future. plb v34 - The Processor Local Bus (PLB) is part of the International Business Machines (IBM) CoreConnect Bus Architecture specication and is the high-speed data interface to the PPC core. All of our peripherals and system memory will communicate with the processor using this bus. If you are using a Virtex-5 device you may want to consider adding two PLB cores - one for data fetching and one for instruction fetching. Having two PLB interfaces only really makes sense in the Virtex-5 devices because the Power PC 440 (PPC440) is capable of out-of-order execution and has a longer 5-stage pipeline than the PPC405.5
5 If

you are using a Virtex-4/5 the IP Catalog will reference the newer PLB v4.6 instead of v3.4.

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 opb v20 - The On-Chip Peripheral Bus (OPB) is another piece of the IBM CoreConnect Bus Architecture specication, but has been deprecated for use by Xilinx.6 However, I want to use it in this tutorial because in my next tutorial I will teach you how to add a custom IP core to your design, and the OPB has a very simplistic interface and is a good learning segway when just starting to learn about the IBM CoreConect Bus Architecture. plb2opb bridge - The PLB2OPB bridge will allow low-speed peripherals to interact with the processor over the PLB (remember, the PLB is the only physical interface to the PPCfor our peripherals). This bridge will act as a slave on the PLB and a master on the OPB. bram block - We will use Block Random Access Memory (BRAM) as the processors main memory in this design just to keep things simple. However, in a larger design with larger applications you will most likely want to use Double Data Rate (DDR) memory (if your board has a DDR slot available). Xilinx provides DDR controller cores as well. plb bram if cntrl - This module will be our interface to the BRAM. If you are using BRAM as main system memory or cache space you will need one of these controllers. opb uartlite - This is an RS-232 UART core that we will use to transfer characters to a standard VT100 terminal (e.g. HyperTerminal, TeraTerm Pro, etc.). Compared to the Xilinx 16550 compliant UART the UARTlite is very simplistic and only has a few congurable registers/parameters - when Xilinx says lite they mean it!7 Please see image 2.3 to see what the Bus Interface list should now look like. I changed some of my core instance names but you dont have to. Just make sure you dont try to name them the same as the actual IP name or EDK will thrown the following warning: WARNING:MDT - Could not rename instance: New instance name for (plb bram if cntlr 0) must be different from IP name (plb bram if cntlr).8 Thats it! Weve got all the cores we need (at least for this little demonstration anyway). Now we just have to connect them together so they can communicate properly. 8. First, connect the JTAG PPC Controller to both of the PPC cores. Note that we are still only going to use one PPC core, but EDK will throw an error if we dont connect the JTAG controller to the one that is not being used. Nothing else will have to be connected to the second PPC core. Do this by connecting the respective JTAG controller ports under the bus connection column to each processor. See image 2.4. 9. Now lets connect up our main system buses. In this design both data and instructions will pass over the same Processor Local Bus (PLB) bus (i.e. we wont have one for instruction and one for data). So select the PLB instance name under the Bus Connection column for the Data Processor Local Bus (DPLB) and Instruction Processor Local Bus (IPLB) bus interfaces for ppc405 0.9 See image 2.4. 10. Now, connect the PLB2OPB bridge as a slave on the PLB and a master on the On-Chip Peripheral Bus (OPB). See image 2.4.
6 The OPB bus was deprecated because Xilinx has corrected many of the arbitration issues that existed between high- and lowspeed devices that were ghting for access to the processor. Now that those issues are xed, most devices can share the same PLB without much concern. 7 Xilinx actually gives you all of the VHDL source code for this little core. If youre interested just look in the EDK install directory. 8 This warning doesnt actually have anything to do directly with EDK at all, VHDL syntax does not allow you to have instance names identical to that of the module (unlike Verilog). 9 We will not be using the Device Control Register (DCR) bus at all in this design.

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Figure 2.3: Bus Interface List 11. Now attach the RS232 UARTlite as a slave on the OPB. See image 2.4. 12. Connect the PLB Block Random Access Memory (BRAM) Interface (IF) Controller as a slave on the PLB. And also connect the BRAM block itself up to the BRAM IF controller on PORTA (we will only have one memory block in this design so we wont use PORTB of the BRAM IF controller at all). While youre at it, also right-click on the PLB BRAM IF controller, select Congure IP. . . , select the System tab, select PLB from the conguration list, and change PLB clock period to match the period of whatever speed clock you connected it to (in my case it was 10000ps or 100MHz). See image 2.4. 13. Check image 2.4 below and make sure your design has the same bus interfaces as mine. 14. Now lets get down to the nitty gritty parts. Change the tab near the top of the window from Bus Interface to Ports. There are a ton of signals to connect here so lets get started. First, lets get some clock connections in place. Expand the Digital Clock Manager (DCM) instance block and attach the RST input to net gnd.10 . Now, for the CLKIN port select Make External for the connection this will be the input from the onboard oscillator. For the CLK0 output choose New Connection from the drop down list. For the DCMs clock feedback input (CLKFB) select the signal name that is being used for the CLK0 output.11 Finally, make a new connection for the LOCKED output as well. The DCM port list should look like image 2.5. While we are here, right-click on the DCM instance and choose Congure IP.... In the DCM section, change the Conguration Startup Wait option to True. This will cause the design to be held in reset until the DCM has locked (as I mentioned earlier). Additionally, change the Input Clock Period parameter to match your input clock period (in nanoseconds) - for my board this was 10.0.
may seem strange but its a perfectly valid conguration because we are going to congure our entire system to wait for all DCMs to lock before releasing the FPGAs Global Set/Reset signal - I will show you how to do this later 11 We want the CLK0 output of the DCM to feed right back into itself to allow the DCM to correctly adjust for clock skew (this is recommended by Xilinx).
10 This

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Figure 2.4: JTAG and System Bus Connections !WARNING!: Make sure that the value you enter here has at least one decimal place because the DCM wrapper requires a oating point data type for this parameter, and if the number does not contain at least one decimal place the synthesis tool will error out when it tries to synthesize the DCM. In the Buffers section, change the BUFG option for the CLK0 output to True. Do not place a BUFG on the CLKIN or CLKFB inputs to the DCM because it needlessly uses up a BUFGP and will result in poor routing inside the FPGA. We do, however, need to insert an IBUFG between the external oscillator port and the DCM CLKIN input, but we cant do that here. Click OK, and open up the MHS le under the Project tab in the left panel. Near the very top of the le locate your DCMs CLKIN port and add/change the parameter SIGIS to SIGIS=DCMCLK. Doing so will prevent the mapping tool from wasting the BUFGP. 15. Next, lets connect up the system reset block to the PPC. For the Slowest sync clk port just choose the slowest clock frequency that will actually be used by any device in the entire system. For this design, that frequency will be the CLK0 output of the DCM. For Ext Reset In port select 13

Figure 2.5: DCM Port Connections Make External - later on we will connect this signal to one of FPGAs reset inputs that is controlled by a Triple Supply Monitor (LTC1326CS8) chip (component U23 on the XUPV2Pboard schematic).12 The LTC1326CS8 asserts its reset outputs to the FPGA when one of the input supply voltages drops below a certain threshhold or when an optional push button input is asserted. Now connect the Dcm locked input port to the dcm 0 locked output signal of the DCM module that we created earlier. Then, select New Connection for the Rstc405resetcore/chip/sys ports from the drop-down list which will be used to connect to the PPC405 later. The 3 inputs named Core/Chip/System Reset Req will be driven by the PPC core itself when it needs to reset due to some fatal error condition.13 Finally, create a new connection for the Bus Struct Reset output - this will be attached to the PLB and OPB later. Normally, we would also use the Peripheral Reset output port, but our only peripheral (the OPB UARTlite) was originally designed to connect to the OPB bus directly so its reset port is connected to the OPBs reset signal by default. Finally, and ONLY if your external reset input is active low (like it is on the XUPV2P), right-click on the reset control block and change the External Reset Active High input to 0 (i.e. false). 16. Under the PPC instance, create new connections for the three C405RSTCHIP/CORE/SYSRESETREQ ports and connect them to the reset controllers Core/Chip/System Reset Req input ports as mentioned earlier. Finally, connect the RSTC405RESETCHIP/CORE/SYS input ports of the PPC to the Rstc405resetcore/chip/sys output ports of the reset block. Also, connect CPMC405CLOCK (i.e. the PPCs main clock) to the DCMs CLK0 output signal. In case youre curious, the CPM port name prex stands for Clock and Power Management and is just one of the many port groupings on the PPC405. 17. Check to make sure that the connections for the reset control block and the PPC405 look like those in
12 You 13 The

external reset input could be whatever you like or have available. connection names to these signals will not exist until we create them under the PPC405 port list.

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images 2.6 and 2.6 below. Note that your instance and signal names could be different from mine.

Figure 2.6: Reset Controller Port Connections 18. Now, connect the PLB and OPB clock inputs to the DCMs CLK0 output. Additionally, connect the PLB and OPBs SYS Rst input port to the Bus Struct Reset output of the system reset controller. It should look like image 2.8. Also, right-click on the PLB instance and uncheck the box for Include DCR Interface and Error Registers. Since we wont be using the CoreConnects Device Control Register (DCR) bus in this design, deselecting this option will reduce the amount of logic needing to be synthesized by Xilinx Synthesis Tool (XST). While were at it, also right-click on the PLB2OPB bridge instance, select the System tab, select DCR from the list, and nally change Include DCR Slave Interface to 0 (i.e. false). 19. Finally, lets nish things off with the UART ports. Select Make External for both the TX and RX lines of the UART. We wont use the interrupt output for this design but in the future I would highly suggest using the Interrupt port. For any device as slow as a UART an interrupt is really the only efcient way for information exchange between it and the processor. But for now just leave it and well deal with the inefciences (which you wont even notice in this design anyway since we only have the one peripheral that needs bus access). Finally, right-click on the UART to congure it, and change the baud rate to 115200, and change Use Parity to False. 20. Phew! Were done with the port connections! Now, open up the system.mhs le by changing tabs in the left panel of the EDK window from IP Catalog to Project and double-click on MHS File to open it. Inside this le you will see the fruits of your labor from attaching all of those Bus Interfaces and Ports. And, yes, you can create this le prior to even creating an EDK project, add the le to a new design, and it will update the Graphical User Interface (GUI) port and bus interface display appropriately. In other words, instead of using the GUI to generate the MHS le we could have used the MHS le to generate the GUI connections. I showed you the GUI method rst because its easier to understand what were trying to accomplish. In any case, we need to look at a few things in this le. First, locate the opb uartlite instance and change the C CLK FREQ parameter to whatever the OPBs clockrate is (in my case it was 100000000).14
some reason this parameter does not show up in the Congure IP... window for this core in EDK v8.2i. It does, however, show up in the congure panel in v9.2i (select the System tab, then select OPB from the left column.)
14 For

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Figure 2.7: PPC 405 Port Connections 21. Were not done with the MHS le just yet. Scroll to the very top and you will see the external ports that you dened for this design when you selected the Make External option. In this example you should only have 4: the external clock input, the external reset input, and the TX/RX data lines for the UART. You dont need to change anything in the MHS le but you will need to know the auto-generated external port names that EDK created (i.e. the ones with the pin sufx - but you can rename them too if you like). With the MHS le open, also open up the system.ucf User Constraints File (UCF) le which can also be found under the Project tab in the left panel. Constrain the 4 external ports to pins on the FPGA and add the ever-important clock period constraint to your input system clock. Below are the constraints that I used.

# System Clock Input # TNM_NET = Timing Name for Nets Net dcm_0_CLKIN_pin LOC=AJ15 | IOSTANDARD = LVCMOS25 | TNM_NET = dcm_0_CLKIN_pi TIMESPEC TS_sys_clk_pin = PERIOD dcm_0_CLKIN_pin 10 ns; # System Reset Input 16

Figure 2.8: PLB and OPB Port Connections # TIG = Timing IGnore Net tsm_pb_rst_Ext_In_pin LOC=AH5 | IOSTANDARD = LVTTL | TIG; # PPC Core Usage Constraints INST ppc405_0 LOC=PPC405_X1Y0; INST ppc405_1 LOC=PPC405_X0Y0;

# Module RS232_UART constraints Net RS232_UART_RX_pin LOC=AJ8 | IOSTANDARD = LVCMOS25; Net RS232_UART_TX_pin LOC=AE7 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 1 In addition to the external port constraints notice the PPC Core Usage Constraints. The purpose of these constraints is to tell EDK that we want ppc405 0 to be associated with the right (i.e. physical location) PPC core rather than the left. This is the recommended by Xilinx when a design is using only one of the PPCs in -7 speed grade, Virtex-II Pro, dual-core devices. For more information on these constraints you can read Xilinx document XAPP755. 22. With that complete lets move on to dening our address space. Navigate back to the System Assembly View window and change lters from Ports to Addresses. You will see a list of buses, controllers, and peripeherals. What we need to do here is section out some of the PPCs 4GB of address space for our systems devices. Just for fun, hit the Generate Addresses button at the top of the window and EDK will automagi17

cally generate the addresses it thinks is best for the design.15 My gripe with the auto-generate tool is that it way overcommits address space for every component.16 We only need a tiny bit of address space for our design. Change the address size of the UART 256 locations. Since we only have this one peripheral you can also reduce the size of the PLB2OPB bridge from 64K to 256 as well. We can also reduce the size of the PLB BRAM IF controller to give us just enough space for a tiny little application that will print out some characters to the UART. So lets size our BRAM to 16KB* which should be plenty of room.17 NOTE 1!: Ensure that the High Address of the PLB BRAM ends on 0xFFFFFFFF. This condition must be met, otherwise the compiler cant place any instructions at the PPCs reset vector and EDK will throw an error! Please see image 2.9 below and make sure your address mapping is similar to mine (the only addresess that need to match exactly are those for the PLB BRAM IF controller). *NOTE 2!: In EDK v9.2i Xilinx has changed the requirement for the memory mapping and system memory must now be on 64KB boundaries! Which means that your BRAM address range should be from 0xFFFF0000 - 0xFFFFFFFF.

Figure 2.9: System Address Mapping 23. Were almost ready to test our design! But rst, we need a small application to test the UART. To do this, select the Applications tab in the left EDK panel. Double-click on Add Software Application Project..., name your project and be sure it is set to be executed on ppc405 0.18 See image 2.10
you get a warning about the Auto-Generate Address function not supporting dual-core designs just ignore it. This problem is xed in v9.2i. 16 There is actually a good reason for doing this because creating smaller address space requires more address decode logic. 17 We could actually pick 8KB and it would still be almost twice the space that are little program will need, but 16KB is the minimum memory size conguration for the Virtex-II pro using the PPC405in 64-bit data width mode. If you dont choose at least 16KB EDK will certainly let you know with an ERROR message when you try to implement the design. 18 You can check the Project is an ELF-only Project box if any of your future applications are being maintained by the XPS Software Development Kit (SDK).
15 If

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below. Say OK to that window and then right-click on the new project name in the left panel and click Mark to Initialize BRAMs. This tells the Xilinx EDK ow tools to embed this project compiled application binary code into the FPGAs conguration bitstream (using the data2mem program) so that it can be loaded into the BRAM along with the FPGA physical design itself.19 Now, right-click on Sources under the project name, select Add New File..., and select a location for the programs main le.

Figure 2.10: Add Software Application Dialog 24. Double click on your new source le to open it and lets add some code. For our UART test app we arent going to have much of any code at all. In fact, its only one function call! Create the standard C main function and then call the following function: print(Hello World!);. There is actually one VERY important thing to note here and that is the fact that we are calling print() and not the C standard library printf() function. It seems like a very small difference but it is actually a HUGE difference. The print() function is a Xilinx function and it uses the bare minimum number of instructions to write characters out to the UART. The standard C printf() function on the other hand, generates huge libraries (e.g. one library is used for printing oating point numbers) that wont t in our small BRAM - your program will very easily bloat to well over twice the size if you mistakenly use printf() instead of print(). Now, dont think that you cant use printf() if you dont want to, be my guest, but youll have to more than double the size of your BRAM (32KB should cover it if youre interested), and youll also have to include the customary stdio.h library. Below is the code for the program: int main(void) { print("Hello World!");
default bootloop application already provided for you is simply an unconditional branch-to-self assembly instruction that will keep the processor in a known state. You can verify this by right-clicking on it and selecting View Source. This little app needs to be used when debugging your PPC design with the JTAG debugger.
19 The

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} 25. You may have asked yourself how does the print() (or printf() for that matter) function know where to send the characters (i.e. memory address of the UART)? Well, its the same in EDK as it is in most other Operating System (OS)s, we have to dene what are referred to as STDIN and STDOUT. To do this, click on the Software menu and select Software Platform Settings.... In the OS and Libraries section, change the stdin and stdout options to the OPB UARTlite! While youre in this window, lets also go ahead and take care of one other small matter of business which is located in the Software Platform section. Change the CORE CLOCK FREQ HZ parameter from 400MHz to 100MHz (or whatever your system is running at). There are LOTS of other goodies in here, including many of the controls required for successfully porting Linux to most of the Xilinx development boards (you can check out my Linux port study/tutorial here at https://rmrfroot.net/xupv2p/). 26. With that out of the way lets see if we can build our UART test application. Before we can compile and link our application we will need to create a linker script. Fortunately, Xilinxs automatic linker script generator is quite good and we wont have to do anything by hand. Right-click on your project name again and select Generate Linker Script..., then click on the Generate button in the bottom right-hand corner of the window. The console window at the bottom of EDK should say Linker Script generated successfully. Finally, right-click on your project one more time and click Build Project. There shouldnt be any errors and the console output should end with Done!. 27. Great! All we have to do is synthesize our hardware and were done! BUT, before that we should create a Xilinx iMPACT tool batch le so EDK can automatically target and program the FPGA when its done generating the bitstream. This le is called download.cmd and it should be created and saved in the etc directory where your EDK project is located. If youre using the XUPV2P board you can just copy the code below. If youre not using the XUPV2P board you should at least make sure that the -p 3 option for the assignle and program commands is correct for your board. The -p option refers to the position of the device you are trying to program in the boards JTAG chain. In my case I want to program the FPGA which is third in line in the JTAG chain on the XUPV2P board. setMode -bscan setCable -p auto identify assignfile -p 3 -file implementation/download.bit program -p 3 quit 28. We might as well also open HyperTerminal, TeraTerm Pro, or whatever serial application youre using on your PC/Linux box and congure it to the same settings as the OPB UARTlite. Connect the serial cable from the board to your PC/Linux box as well. And also connect up the Xilinx programming cable to the board and power on the board. 29. If you like, you can also edit the default fast runtime.opt script located in the etc folder of your project area. You can open this le from the Project tab in the left window pane. You can edit the

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options to your liking. Personally, I like to add the -timing option to MAP and also change the MAP and PAR optimization levels from standard to high.20 30. Also, remembering that we congured the DCM module with the STARTUP WAIT=TRUE option we must properly congure the bitgen options le so that the FPGA programming sequence is setup for the proper order of operations.21 To do this open the etc bitgen.ut le and add the following lines: -g -g -g -g GTS_cycle:1 GWE_cycle:1 LCK_cycle:2 DONE_cycle:4

IMPORTANT: Make sure that there arent duplicates of the above options anywhere else in the le. 31. Okey-dokey! Lets synthesize, translate, map, and place-and-route our hardware! Click on the Hardware menu at the top of the EDK window and select Generate Bitstream. The output from bitgen will present you with the following strange WARNINGs: WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMISOCMCLK for the comp ppc405_0/ppc405_0/PPC405_i is not connected to the output of a DCM driven clock buffer. WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMDSOCMCLK for the comp ppc405_0/ppc405_0/PPC405_i is not connected to the output of a DCM driven clock buffer. WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin CPMC405CLOCK for the comp ppc405_1/ppc405_1/PPC405_i is not connected to the output of a DCM driven clock buffer. WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin PLBCLK for the comp ppc405_1/ppc405_1/PPC405_i is not connected to the output of a DCM driven clock buffer. WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMISOCMCLK for the comp ppc405_1/ppc405_1/PPC405_i is not connected to the output of a DCM driven clock buffer. WARNING:PhysDesignRules:1009 - Blockcheck: The clock pin BRAMDSOCMCLK for the comp ppc405_1/ppc405_1/PPC405_i is not connected to the output of a DCM driven clock buffer. There is no need to worry about these warnings. First off, note that the last 4 warnings in that list relate to ppc405 1 which we are not using. The rst 2 warnings are referring to the clock ports of the instruction and data side On-Chip Memory (OCM) blocks. Since we are not using any OCM for this design you can completely disregard them. 32. Assuming the previous step was successful lets integrate our test applications binary into the hardware designs bitstream. Do this by clicking the Device Conguration menu and selecting Update Bitstream.
20 These 21 If

changes are already the default in EDK v9.2i. we dont do this then the STARTUP WAIT=TRUE option will do nothing!

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33. If the previous step went well then click the Device Conguration menu again and select Download Bitstream. This will target the board and download your design to the FPGA. With a bit of luck you should see Hello World! displayed in your serial port applications terminal window. 34. So what have we learned from all these steps. . . ? Answer: That we should thank Xilinx for the Base System Builder (BSB) wizard! ;-)

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CHAPTER

Simulating Your EDK Design

First off, the following steps assume that you have already compiled the ISE and EDK libraries for ModelSim and have updated the modelsim.ini le with the library locations as necessary. 1. First, we need to tell EDK where to locate the Integrated Software Environment (ISE) and EDK simulation libraries. To do this click on the Project menu at the top and select Project Options. . . . Click the HDL and Simulation tab, then ll in the EDK and ISE library paths. You can also change the simulator application you are using here as well. 2. Next, we need to make a few minor modications to our Microprocessor Hardware Specication (MHS) le. At the very top where we dened our external clock and reset inputs we need to add the following parameters1 : <external rst pin name here> = <internal rst sig name here>, SIGIS = RST, RST POLARITY = 0 <external clk pin name here> = <internal clk pin name here>, SIGIS = DCMCLK2 , CLK FREQ = 100000000 Of course, you should change the CLK FREQ and RST POLARITY parameters as appropriate. These 4 parameters do some really neat things that Ill talk about later. If you look online there isnt much info about these parameters and many people are very confused about what they are actually used for. This is mostly because if you dont have them specied the design can still function perfectly without them either in hardware or simulation. You should also note that as of EDK v10.1 sp2 there is * no * support for a CLK POLARITY parameter. Apparently, it did not occur to Xilinx that this parameter would also be useful. When would this be useful you ask? Well, when using differential clocks of course. I recently ran into this issue when I was testing a custom IP that utilized a few Multi-Gigabit Transceiver (MGT) ports. In case you dont know MGT ports require a differential clock input in order to transmit/receive a reasonable
that these parameters do not in any way change your hardware design and are only used by EDKs simulation environment generator tool. 2 If youre clock input is not being routed to a Digital Clock Manager (DCM) then you should just use CLK instead of DCMCLK.
1 Note

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signal on each positive and negative differential port. Differential oscillators will also usually have a very low Parts Per Million (PPM) jitter specication (as is the case with the Xilinx ML325 board). A differential clock has two outputs of the exact same frequency except that the clocks are exactly 180 degress out of phase. On a Xilinx device these two inputs are usually routes to an IBUFGDS component as soon as it enters the FPGA. The IBUFGDS block then generates a single output, very clean, reference clock which all of you other internal modules may use. So what am I getting at? Without a CLK POLARITY parameter EDK will emulate both input clocks as two identical, phase aligned frequencies. If you input two identical clocks into an IBUFGDS the output reference clock is X in simulation (this is actually specied in the Xilinx datasheets as well). I spent over an hour trying to gure out why my design was not simulating properly only to nd out that the auto-generated clock inputs were incorrect and none of my logic was receiving a clock! I have since requested that Xilinx include this parameter as an option to the user and they have agreed that it was a good idea. The Xilinx Enhancement Request number is 474572. They could not tell me at the time in which revision this enhancement would be integrated but if you want to ask them you have the number to reference. In the meantime I gured out a way to manually x the incorrect clock inputs to your design if you are using a differential clock. Here is an example from my design: The Xilinx EDK auto-generated system setup.do script created the following Modelsim commands for me: force -freeze $tbpath${ps}SYS_CLKN_pin 0, 1 {3 ns} -rep 6 ns force -freeze $tbpath${ps}SYS_CLKP_pin 0, 1 {3 ns} -rep 6 ns I had to change the command for SYS CLKN pin to: force -freeze $tbpath${ps}SYS_CLKN_pin 1, 0 {3 ns} -rep 6 ns 3. Next, if you are simulating a custom IP core, you will likely want to generate a structural HDL simulation netlist of your IP. This makes design maintenance much easier because instead of having to list every single source le in the Xilinx Peripheral Analyze Order (PAO) le for simulation you only need to include the top-level structural netlist le of your entire core. To generate a simulation netlist run the following command: netgen -ofmt <vhdl|verilog> -w <your_toplevel>.ngc The output of the above command will be a .vhd le which you can then add to your PAO le like so: simlib <your_ip_library_name> <relative_path>/<your_toplevel>.vhd Notice that we use simlib instead of just lib this tells EDK to ignore this le when it is actually implementing the design to be target to the FPGA. However, when it is generating the simulation scripts it will include this le properly. 4. Now, click on the Simulation menu at the top of the EDK window and select Generate Simulation HDL Files.

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5. If step 3 was successful, EDK just generated an entire test bench environment for your design complete with simulation script macros right at your immediate disposal. To exploit all of the hard work EDK just did click on the Simulation menu again and select Launch HDL Simulator.... In my case this opens ModelSim. I have noticed that this sometimes does not open ModelSim on certain computers. I havent been able to gure out why yet, but if it happens, you can exactly replicate the actions of the Launch HDL Simulator... command by performing the following 3 steps: Start ModelSim Navigate the simulators working directory to <your project dir>/simulation/behavioral/ Run command: do system setup.do 6. Before moving on I would like to note a few changes that may be required to the EDK auto-generated simulation les. First, navigate to <your project dir>/simulation/behavioral/ and open the simulate.do le. This is the script that is called when you compile your design. It compiles each of the les that you listed in the Xilinx PAO le in your IP repositories pcores/core name/data directory. The only reason you may need to change this is if you are simulating your design using the glbl.v module provided by Xilinx. If so, you should add the following line to the le: vlog -work work vlog $env(XILINX)/verilog/src/glbl.v 7. In addition, if you are using any Xilinx core components you will also need to modify the system setup.do le in order to tell modelsim to include the Xilinx simulation libraries. To do this change le as follows: Original auto-generated system setup.do: alias s "vsim -t ps system conf; set xcmds 1" Add the Xilinx simulation libraries like this: alias s "vsim -t ps -L unisims ver -L simprims ver -L xilinxcorelib ver system conf; set xcmds 1" Since most of my designs also use the glbl.v module (in order to emulate the GTS/GSR signals within the FPGA) I also modied the line as follows: alias s "vsim -t ps -L unisims ver -L simprims ver -L xilinxcorelib ver system conf glbl; set xcmds 1" 8. The simulators console window should now have a help menu displayed (which was created by the system setup.do script). You should see 7 possible commands: c, s, l, w, clk, rst, and h. If you dont see both the clk and rst commands in the help menu then you did not congure the SIGIS, CLK FREQ, and/or RST POLARITY parameters in the MHS le properly. The clk command was automatically generated by EDK to generate stimulus to your external clock input with the specied frequency provided by the CLK FREQ parameter. It knew which input was your clock because of the SIGIS = [DCM]CLK parameter. Similarly, EDK created a rst stimulus to your designs external reset input based on the RST POLARITY parameter. However, the rst command not only strobes the reset input, but it also runs the clk stimulus command for you as well. Pretty cool!

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9. Now that you have an idea of what the commands do, execute command c to compile the design. Then run s to load the simulation. Then run w to load the waveforms into the waveform window. Next, run rst which will generate the clock and strobe the top-level reset input that you dened in the MHS le. 10. The rst command only runs the simulation just long enough to strobe the reset input, so you have to execute one more command to continue your simulation for however long you want. For ModelSim, I just like to use run -all, which will run the simulation indenitely until you tell it to stop. 11. Try simulating our simple UART design in ModelSim and look at the external TX line from the UART. Try to analyze the data and pick out each character from Hello World! as it is sent to the terminal.

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CHAPTER

Adding Custom IP To Your EDK Design

This chapter is a work in progress. I have already successfully added custom IP to my design using the Xilinx Custom IP wizard, but I dont have the time to write a detailed tutorial just yet. However, I have added some other sections that provide some very useful techniques for which Xilinx does provide any documentation (or support for that matter).

4.1

Manually Changing the Number of S/W Accessible User-Registers

This section will instruct you on how to manually change the number of available user register in your design if you nd that you need to change them after youve already completed the Custom IP Wizard ow.1 Very recently I found myself needing more S/W addressable user registers for my custom IP than I had originally thought when I rst ran the Xilinx custom IP wizard. At rst I thought the only way to add more would be to run through the entire IP wizard again from scratch - which is ridiculous. I knew there had to be a better way and it is actually quite easy. Follow the steps below and you shouldnt have any problems.2

1. Open the very top-level template le that the custom IP wizard generated. This is usually pcores/<ip name>/hdl/vhdl/ Locate the USER NUM CE parameter and change the number to the number of registers you would like. 2. Open the user logic.vhd le in the same directory. Change the slv reg write/read select signal vector sizes to match that which you specied with USER NUM CE in the top-level le. For example, if you originally had 3 S/W registers and you added just one more you would change the vector widths from (0 to 2) to (0 to 3). In fact, you can get rid of the static constant vector and replace it with a more maintenance friendly generic from the entity declaration. Change the vector to this instead so you dont ever have to worry about it in the future: (0 to C NUM CE-1). This will pull the USER NUM CE from the top-level and use it to size the vector automatically.
1 You should know that Xilinx does not support the manual edits to the custom IP templates that the IP wizard provides you if said edits are outside of the specically stated edit here sections in the templates. 2 DISCLAIMER: I have tested these steps with various custom IP and havent yet had a problem, but that does not in any way mean that this method is 100% correct and wont lead to problems with future designs. In other words, use these steps at your own risk!

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3. Add new internal registers to the user logic module to match the new number of user registers (e.g. if you originally had 3 S/W registers and you added just one more you would add the following register: slv reg3 : std logic vector(0 to C DWIDTH-1); 4. Update the slv wrte/read ack signal assignments to reect each of your additional registers. Following the examples above: slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2); slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2); would change to... slv_write_ack <= Bus2IP_WrCE(0) Bus2IP_WrCE(2) slv_read_ack <= Bus2IP_RdCE(0) Bus2IP_RdCE(2) or or or or Bus2IP_WrCE(1) or Bus2IP_WrCE(3); Bus2IP_RdCE(1) or Bus2IP_RdCE(3);

5. Now, update the SLAVE REG WRITE/READ PROC register selection decoders to reect your new registers. Dont forget to update the sensitivity list for SLAVE REG READ PROC! 6. Next, make sure you have enough memory space allocated to your IP within EDK so that you can access the new registers. You may not need to perform this step. 7. Finally, you will obviously need to update the template software driver les that Xilinx provided you when you intially created the Custom IP core (but only if you intend to continue using them). This should be pretty straight forward. The changes required are similar to those for the hardware templates. Just follow the pattern of function denitons and addresses they provide you. (a) Add additional slave register offsets as necessary to the header le. (b) Add additional mWrite/ReadSlaveReg functions as necessary to the header le. (c) Add additional register read/write tests to the IP self-test function as necessary.

4.2

Creating your own MUI Files

One other useful bit of information I can give you for your adventure into EDK custom IP integration is for creating your own customized conguration window (i.e. the EDK window that pops up when you rightclick on an instance in your EDK design and select Congure IP. . . ) for your custom Intellectual Property (IP). The conguration windows are dynamically generated with a very simple XML-syntax le with the extension .mui. This le should be stored in the pcores/<ip name here>/data/ directory along with the Peripheral Analyze Order (PAO) and Microprocessor Peripheral Description (MPD) les. I will not explain how to edit them but you can learn very easily by looking at some of the MUI les for any of Xilinxs IP cores in the EDK install directory. Here are a couple examples: A simple MUI <EDK install dir>/hw/XilinxProcessorIPLib/pcores/opb uartlite v1 00 b/data A complex MUI <EDK install dir>/hw/XilinxProcessorIPLib/pcores/opb emc v2 00 a/data

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