BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI FIRST SEMESTER 2007-2008 IS C351 COMPUTER ORGANISATION & ARCHITECTURE COMPREHENSIVE

EXAMINATION
Date: 13/12/07 (AN) Time: 3 Hrs MM: 70

Note: This question paper contains PART-A (Close Book) and PART-B (Open Book). Use separate answer sheets for each one. Collect a separate answer sheet for answering PART-B after submitting PART-A answer sheet. There is no time bound for individual parts. Manage 3 hrs according to your need. PART-A (Closed Book) MM: 36 Q.1 1.a Answer the following questions. (Each question carries 3 marks). [6x3 = 18M]

Consider a 32- bit microprocessor with a 16-bit external data bus, driven by an 8 MHz input clock. Assume that this processor has a bus cycle whose minimum duration equals four clock cycles. What is the maximum data rate across the bus that this microprocessor can sustain in bytes/second? Consider a microinstruction format having one address field and a control portion field. The size of microinstruction is of 24 bits. The control portion of the micro instruction is divided into two fields: a micro operations field of 13 bits specifies the micro operation to be performed and an address selection field specifies a condition based on the eight flags that will cause a microinstruction branch. Find the number of bits in address field and the size of the control memory. (i) Convert the given IEEE single-precision floating point number into a decimal number? 10000010001100000000000000000000 (ii) Express the following numbers in IEEE single-precision floating point format? -2-126 A block set associative cache consists of a total of 64 blocks divided into 4 block sets. The main memory contains 4096 blocks, each consisting of 128 words. How many bits are there in each of the TAG, SET and WORD fields? Describe static multi-issue (VLIW) and dynamic multi-issue (superscalar) in terms of how and when decisions about which instructions can be issued into the pipeline are made. The processor must have a process for handling exceptions. Describe four things that the processor must be able to do to identify and/or take care of. Please Turn Over

1.b

1.c

1.d

1.e

1.f

Q.2 2.a

Answer the following questions. (Each question carries 3 marks). [6x3 = 18M] Assume that two processors P1 and P2 in an SMP configuration, over time require access to the same line of data X from main memory. Both processors have a cache and use the MESI protocol. Initially both processors caches have invalid copy of the line. Show the change of state of cache line in both processors for the following sequence of operations. (i) P2 reads X (ii) P1 reads X (ii) P2 writes to X With dynamic relocation the hardware has a base register and a bound register which is use to support multiprogramming. What functionality do you loss when you have only one either base register or bound register? The IBM 370 does not provide indirect addressing mode. Assume that the address of the operand is in main memory. How would you access the operand? Consider the given set of instructions for IA-64 architecture. Rewrite the optimized set of instructions after using data speculation technique. st8 [r1] = r5 ld8 [r2] = [r3] add r5 = r2, r6 st8 [r9] = r5 What is the difference between branch prediction used in scalar pipe line processor and predication technique used in IA-64 architecture? Let the address stored in the program counter be represented by the symbol P. The instruction stored in the P has an address part (operand reference) Q. The operand needed to execute the instruction is stored in the memory word with address R. What is the relationship between these three quantities if the addressing mode of the instruction is? (i) Direct, (ii) Indirect (iii) PC relative

2.b

2.c

2.d

2.e

2.f

Please Turn Over

PART-B (Open Book) MM: 34 Q.3 Consider a five staged pipeline along with the time requires for each stage to take given below. Stage Operation Time Required Instruction Fetch (F) Fetch the new instruction 40 ns Instruction Decode (D) Read registers and decode instruction 10 ns Access Memory (M) Access operand in memory 40 ns Execute (E) Executes operation 10 ns Write Back (WB) Write results into a register 30 ns Assume that every instruction in the instruction set requires the use of all stages of the pipeline. Also assume that the stages of the pipeline are clocked with a common clock. What is the latency of the instruction flowing through the pipeline? What is the idealized throughput of the pipeline? Assume that the sequence of instructions (I1, I2, I3, I4, I5) is executed by the processor has the following data hazards: Type RAW WAR Instruction pair(s) (i) I1, I2 (ii) I3, I5 I3, I4

3.a 3.b 3.c

Using the table format given below, show the instruction that resides in each stage of the pipeline for each clock period. Put X wherever needed, to show pipeline stalls. Clock Period F D M E W 1 3.d Repeat (3.c) by assuming that there is an operand forwarding capability is provided in the hardware. [1+1+4+4=10M] 4.a 4.b 4.c A central processing unit (CPU) has the following hardware components: 4 general purpose registers A program counter (PC) An arithmetic and logic unit (ALU) that can perform 10 logical and 10 arithmetic functions A memory data register (MDR) and a memory address register (MAR) An instructor register (IR) A register P to temporarily hold one operand for the ALU A register Q to temporarily hold the result from the ALU A single CPU bus is to be used to interconnect the hardware resources. Draw a block diagram of the data path of this CPU. List all of the control signals that are needed in your data path. If three buses are used in place of a single bus then how it will affect the performance of the system? Explain [4+3+1=8M] Please Turn Over

Q.4

Q.5

5.a

An 8 byte, 2-way set associative cache memory (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary): 0110, 0000, 0010, 0001, 0011, 0100, 1001, 0000, 1010, 1111, 0111, 1110 Show the tag entries of each cache line and hit or miss information for each request given above in the following format. Here each set considered as one cache line. Assume that initially all cache lines are empty. One example entry is given for two cache lines and two tag values for each cache line: Address Cache line-0 tags Cache line-1 tags Hit or Miss 0101 00/01 11/01 Hit

Note: Example entry is given just to show how to fill the table. Number of cache lines and corresponding tag entries can vary for your solution. 5.b Show the list of addresses for each cache line for which data is available in the cache. [6+2=8M] A computer has one delay slot. The instruction in this slot is always executed, but only on a speculative basis. If a branch doesnt take place, the results of that instruction are discarded. Suggest a way to implement program loops efficiently on this computer. [4M] Can a direct mapped cache some times have higher hit rate than a fully associative cache with an LRU replacement policy on the same reference pattern and the same cache size? If so explain with an example. If not explain, why not? [4M]

Q.6

Q.7

------------------------------------------