Memory Tshooting

23
MEMORY TROUBLESHOOTING
CONTENTS AT A GLANCE Essential Memory Concepts
Memory organization Memory signals Circumventing parity Abuse and detection of fake memory Alternative error correction
Memory Package Styles and Structures

Add-on memory devices Megabytes and memory layout
Memory Installation and Options

Getting the right amount Filling banks Bank requirements
Memory Organization
Conventional memory Extended memory Expanded memory Upper memory area (UMA) High memory
Recycling Older Memory Devices

Memory speed Memory type SIMM stackers Mixing composite and non-composite SIMMS Remounting and rebuilding memory
Memory Considerations
Memory speed and wait states Determining memory speed Presence detect (PD) Understanding memory refresh Memory types Memory techniques
Memory Troubleshooting
Memory test equipment Repairing SIMM sockets Contact corrosion Parity errors Troubleshooting classic XT memory Troubleshooting classic at memory Troubleshooting contemporary memory errors
The Issue of Parity

The parity principle Even vs. odd The problems with parity
Further Study
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ESSENTIAL MEMORY CONCEPTS
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Memory is a cornerstone of the modern PC.
Memory that holds the program code and data that is processed by the CPUand it is this intimate relationship between memory and the CPU that forms the basis of computer performance. With larger and faster CPUs constantly being introduced, and more complex software is developed to take advantage of the processing power. In turn, the more complex software demands larger amounts of faster memory. With the explosive growth of Windows (and more recently, Windows 95) the demands made on memory performance are more acute than ever. These demands have resulted in a proliferation of memory types that go far beyond the simple, traditional DRAM. Cache (SRAM), fast page-mode (FPM) memory, extended data output (EDO) memory, video memory (VRAM), synchronous DRAM (SDRAM), flash BIOS, and other exotic memory types (such as RAMBUS) now compete for the attention of PC technicians. These new forms of memory also present some new problems. This chapter will provide you an understanding of memory types, configurations, installation concerns, and troubleshooting options.
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SYSTEM DATA AND TROUBLESHOOTING
Essential Memory Concepts

The first step in any discussion of memory is to understand basically how memory works. If you already have a good grasp of memory basics, feel free to skip this part of the chapter.
MEMORY ORGANIZATION
All memory is basically an array organized as rows and columns (Fig. 23-1). Each row is known as an addressone million or more addresses might be on a single memory IC. The columns represent data bitsa typical high-density memory IC has 1 bit, but might have 2 or 4 bits, depending on the overall amount of memory required.
M data bits (8-bit data word) D0 Address 0 Address 1 Columns D7
Rows
Address N Cell matrix array FIGURE 23-1 Simplified diagram of a memory array.
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As you probably see in Fig. 23-1, the intersection of each column and row is an individual memory bit (known as a cell). This is important because the number of components in a celland the way those components are fabricated onto the memory ICwill have a profound impact on memory performance. For example, a classic DRAM cell is a single MOS transistor, and static RAM (or SRAM) cells often pack several transistors and other components onto the IC die. Although you do not have to be an expert on IC design, you should realize that the internal fabrication of a memory IC has more to do with its performance than just the way it is soldered into your computer.
MEMORY SIGNALS
A memory IC communicates with the outside world through three sets of signals: address lines, data lines, and control lines. Figure 23-2 illustrates these signal types. Address lines define which row of the memory array will be active. In actuality, the address is specified as a binary number, and conversion circuitry inside the memory IC translates the binary number into a specific row signal. Data lines pass binary values back and forth to the defined address. Control lines are used to operate the memory IC. A Read/Write (R/W) line defines whether data is being read from the specified address or written to it. A Chip Select (CS) signal makes a memory IC active or inactive (this ability to disconnect from a circuit is what allows a myriad of memory ICs to all share common address and data signals in the computer). Some memory types require additional signals, such as Row Address-Select (RAS) and Column Address-Select (CAS), for refresh operations. More exotic memory types might require additional control signals.
Vcc Gnd
Address row select Address Address buffer
Storage cell array
Address column select
Cell I/O circuitry
CS Control circuit R/W
Bi-directional data buffer Data FIGURE 23-2 Diagram of a typical memory IC.
MEMORY PACKAGE STYLES AND STRUCTURES
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Memory Package Styles and Structures

Ultimately, the memory die is mounted in a package just like any other IC. The completed memory packages can then be soldered to your motherboard or attached to plug-in structures, such as SIMMs, DIMMs, and memory cards. Only four package styles are normally used for memory devices:
s DIP (Dual In-line Package) This classic IC package is used for through-hole mounting
(prior to surface-mount technology). The advantage of DIP ICs is their compatibility with IC sockets, which allows ICs to be inserted or removed as required. Unfortunately, the long metal pins can bend and break if the IC is inserted or removed incorrectly. Also, the overall size of the package demands extra space. DIP ICs were used in older PCs (286 and earlier systems) and older VGA/SVGA video boards. DIPs are still sometimes used on motherboards to provide cache RAM. s SIP (Single In-line Package) This type of IC package is rarely used todaythere are simply not enough pins. However, they did make a short appearance with memory devices in late-model 286 and early 386 systems, which flirted with proprietary memory expansions. I remember NEC using such devices in a 2MB add-on for their 386SX/20 and you needed to add that module before you added even more memory in the form of proprietary SIMMs. SIPs can be troublesome because they are difficult to find replacements for, so expect replacement memory modules using them to cost a premium. s SOJ (Small-Outline J Lead) This is the contemporary package style for surfacemount circuits. The leads protrude from the package like a DIP, but are bent around just under the package in the form of a j. Sockets for SOJ packages are often used for replaceable memory ICs, such as the BIOS ROM, but most RAM devices are soldered directly to the motherboard as system memory (or a video board as video RAM). SIMMs often use SOJ memory components. s TSOP (Thin, Small-Outline Package) Like the SOJ, a TSOP is also a surface-mount package style. However, its small, thin body makes TSOP memory ideal for narrow spaces. Expect to find such devices serving as memory in notebook/sub-notebook systems or PCMCIA cards (a.k.a., PC Cards).
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ADD-ON MEMORY DEVICES

Memory has always pushed the envelope of IC design. This trend has given us tremendous amounts of memory in very small packages, but it also has kept memory relatively expensive. Manufacturers responded by providing a minimum amount of memory with the system, then selling more memory as an add-on optionthis keeps the cost of a basic machine down and increases profit through add-on sales. As a technician, you should understand the three basic types of add-on memory.
Proprietary add-on modules Once the Intel i286 opened the door for more than
1MB of memory, PC makers scrambled to fill the void. However, the rush to more memory resulted in a proliferation of non-standard (and incompatible) memory modules. Each new motherboard came with a new add-on memory schemethis invariably led to a great deal of confusion among PC users and makers alike. You will likely find proprietary memory modules in 286 and early 386 systems.
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SIMMs and DIMMs By the time 386 systems took hold in the PC industry, proprietary
memory modules had been largely abandoned in favor of the Memory Module (Fig. 23-3). A SIMM (Single In-line Memory Module) is light, small, and contains a relatively large block of memory, but perhaps the greatest advantage of a SIMM is standardization. Using a standard pin layout, a SIMM from one PC can be installed in any other PC. The 30-pin SIMM (Table 23-1) provides 8 data bits, and generally holds up to 4MB of RAM. The 30A 72-pin SIMM
A 168-pin DIMM
FIGURE 23-3
Comparison of SIMMs and DIMMs.
TABLE 23-1 PINOUT OF A STANDARD 30-PIN SIMM PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VCC CAS DQ0 A0 A1 DQ1 A2 A3 GND DQ2 A4 A5 DQ3 A6 A7 DQ4 A8 A9 A10 DQ5 WE DESCRIPTION +5 VDC Column address strobe Data 0 Address 0 Address 1 Data 1 Address 2 Address 3 Ground Data 2 Address 4 Address 5 Data 3 Address 6 Address 7 Data 4 Address 8 Address 9 Address 10 Data 5 W it bl
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TABLE 23-1 PINOUT OF A STANDARD 30-PIN SIMM (CONTINUED) PIN NAME 21 1 22 23 24 25 26 27 28 29 30 VCC WE GND DQ6 n/c DQ7 QP RAS CASP DP VCC DESCRIPTION Write enable 5 VDC Ground Data 6 Not connected Data 7 Data parity out Row address strobe Parity control Data parity in +5 Vdc
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pin SIMM proved its worth in 386 and early 486 systems, but fell short when providing more memory to later-model PCs. The 72-pin SIMM (Table 23-2) supplanted the 30-pin version by providing 32 data bits, and it could hold up to 32MB (or more). Table 23-3 outlines a variation of the standard 72-pin SIMM highlighting the use of Error-Correction Code (ECC) instead of parity. You might also find such structures referred to as DIMMs (Dual In-Line Memory Modules). DIMMs appear virtually identical to SIMMs, but they are larger. And where each electrical contact on the SIMM is tied together between the front and back, the DIMM keeps front and back contacts separateeffectively doubling the number of contacts available on the device. For example, if you look at a 72-pin SIMM, you will see 72 electrical contacts on both sides of the device (144 contacts total)but these are tied together, so there are only 72 signals (even with 144 contacts). On the other hand, a DIMM keeps the front and back contacts electrically separate (and usually adds some additional pins to keep SIMMs and DIMMs from accidentally being mixed). Table 23-4 outlines a 144-pin DIMM. Today, virtually all DIMM versions provide 168 pins (84 pins on each side). DIMMs are appearing in high-end 64-bit data-bus PCs (such as Pentiums and PowerPC RISC workstations). As PCs move from 64 to 128 bits over the next few years, DIMMs will likely replace SIMMs as the preferred memory-expansion device. Table 23-5 lists the pinout for an unbuffered DRAM DIMM and Table 23-6 presents the pinout for an unbuffered SDRAM DIMM. Finally, you might see SIMMs and DIMMs referred to as composite or non-composite modules. These terms are used infrequently to describe the technology level of the memory module. For example, a composite module uses older, lower-density memory, so more ICs are required to achieve the required storage capacity. Conversely, a non-composite module uses newer memory technology, so fewer ICs are needed to reach the same storage capacity. In other words, if you encounter a high-density SIMM with only a few ICs on it, chances are that the SIMM is non-composite.
MEGABYTES AND MEMORY LAYOUT

Now is a good time to explain the idea of bytes and megabytes. Very simply, a byte is 8 bits (binary 1s and 0s), and a megabyte is one million of those bytes (1,048,576 bytes
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TABLE 23-2 PINOUT OF A STANDARD 72-PIN SIMM PIN NON-PARITY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC n/c A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 VCC A8 A9 RAS3 RAS2 n/c n/c n/c n/c VSS CAS0 CAS2 CAS3 CAS1 PARITY VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC n/c A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 VCC A8 A9 RAS3 RAS2 PQ26 PQ8 PQ17 PQ35 VSS CAS0 CAS2 CAS3 CAS1 DESCRIPTION Ground Data 0 Data 18 Data 1 Data 19 Data 2 Data 20 Data 3 Data 21 +5 Vdc Not connected Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 10 Data 4 Data 22 Data 5 Data 23 Data 6 Data 24 Data 7 Data 25 Address 7 Address 11 +5 VDC Address 8 Address 9 Row address strobe 3 Row address strobe 2 Parity 26 (3rd) Parity 8 (1st) Parity 26 (3rd) Parity 35 (4th) Ground Column address strobe 0 Column address strobe 2 Column address strobe 3 Column address strobe 1
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TABLE 23-2 PINOUT OF A STANDARD 72-PIN SIMM (CONTINUED) PIN NON-PARITY 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 RAS0 RAS1 n/c WE n/c DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 n/c PD1 PD2 PD3 PD4 n/c VSS PARITY RAS0 RAS1 n/c WE n/c DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 n/c PD1 PD2 PD3 PD4 n/c VSS DESCRIPTION Row address strobe 0 Row address strobe 1 Not connected Read/-write Not connected Data 9 Data 27 Data 10 Data 28 Data 11 Data 29 Data 12 Data 30 Data 13 Data 31 +5 Vdc Data 32 Data 14 Data 33 Data 15 Data 34 Data 16 Not connected Presence detect 1 Presence detect 2 Presence detect 3 Presence detect 4 Not connected Ground
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SIZE: (PRESENCE DETECT LINES) PD2 GND GND NC NC PD1 GND NC GND NC SIZE 4 or 64MB 2 or 32MB 1 or 16MB 8 MB
ACCESSTIME: (PRESENCE DETECT LINES)

PD4 GND GND NC NC PD3 GND NC GND NC ACCESSTIME 50, 100 ns 80 ns 70 ns 60 ns
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TABLE 23-3 PINOUT OF A 72-PIN ECC SIMM PIN ECC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3 A4 A5 A6 n/c DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 n/c RAS1 DQ17 DQ18 DQ19 DQ20 VSS CAS0 A10 A11 CAS1 RAS0 OPTIMIZED VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3 A4 A5 A6 n/c DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 n/c RAS1 DQ17 DQ18 DQ19 DQ20 VSS CAS0 A10 A11 CAS1 RAS0 DESCRIPTION Ground Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 +5 Vdc Presence detect 5 Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Not connected Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Address 7 Data 16 +5 Vdc Address 8 Address 9 Not connected Row address strobe 1 Data 17 Data 18 Data 19 Data 20 Ground Column address strobe 0 Address 10 Address 11 Column address strobe 1 Row Address Strobe 0
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TABLE 23-3 PINOUT OF A 72-PIN ECC SIMM (CONTINUED) PIN ECC 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 RAS1 DQ21 WE ECC DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 n/c n/c n/c PD1 PD2 PD3 PD4 n/c VSS OPTIMIZED RAS1 DQ21 WE ECC DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 PD1 PD2 PD3 PD4 DQ39 VSS DESCRIPTION Row address strobe 1 Data 21 Read/-write Error-correction control Data 22 Data 23 Data 24 Data 25 Data 26 Data 27 Data 28 Data 29 Data 30 Data 31 +5 Vdc Data 32 Data 33 Data 34 Data 35 Data 36 Data 37 Data 38 Presence detect 1 Presence detect 2 Presence detect 3 Presence detect 4 Data 39 Ground
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TABLE 23-4 PINOUT FOR AN OLDER 144-PIN SMALL-OUTLINE (SO) DIMM PIN 1 2 3 4 5 6 7 8 9 10 NORMAL VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 ECC VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 DESCRIPTION Ground Ground Data 0 Data 32 Data 1 Data 33 Data 2 Data 34 Data 3 Data 35
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TABLE 23-4 PINOUT FOR AN OLDER 144-PIN SMALL-OUTLINE (SO) DIMM (CONTINUED) PIN 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 NORMAL VCC VCC DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS CAS0 CAS4 CAS1 CAS5 VCC VCC A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VCC VCC DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 ECC VCC VCC DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS CAS0 CAS4 CAS1 CAS5 VCC VCC A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VCC VCC DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 DESCRIPTION +5 Vdc +5 Vdc Data 4 Data 36 Data 5 Data 37 Data 6 Data 38 Data 7 Data 39 Ground Ground Column address strobe 0 Column address strobe 4 Column address strobe 1 Column address strobe 5 +5 Vdc +5 Vdc Address 0 Address 3 Address 1 Address 4 Address 2 Address 5 Ground Ground Data 8 Data 40 Data 9 Data 41 Data 10 Data 42 Data 11 Data 43 +5 Vdc +5 Vdc Data 12 Data 44 Data 13 Data 45 Data 14 Data 46 Data 15 Data 47
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TABLE 23-4 PINOUT FOR AN OLDER 144-PIN SMALL-OUTLINE (SO) DIMM (CONTINUED) PIN 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 NORMAL VSS VSS n/c n/c n/c n/c DU DU VCC VCC DU DU WE n/c RAS0 n/c RAS1 n/c OE n/c VSS VSS n/c n/c n/c n/c VCC VCC DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 ECC VSS VSS CB0 CB4 CB1 CB5 DU DU VCC VCC DU DU WE n/c RAS0 n/c RAS1 n/c OE n/c VSS VSS CB2 CB6 CB3 CB7 VCC VCC DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DESCRIPTION Ground Ground
Dont use Dont use +5 Vdc +5 Vdc Dont use Dont use Read/-write Not connected Row address strobe 0 Not connected Row address strobe 1 Not connected Output enable Not connected Ground Ground
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+5 Vdc +5 Vdc Data 16 Data 48 Data 17 Data 49 Data 18 Data 50 Data 19 Data 51 Ground Ground Data 20 Data 52 Data 21 Data 53 Data 22 Data 54 Data 23
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TABLE 23-4 PINOUT FOR AN OLDER 144-PIN SMALL-OUTLINE (SO) DIMM (CONTINUED) PIN 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NORMAL DQ55 VCC VCC A6 A7 A8 A11 VSS VSS A9 A12 A10 A13 VCC VCC CAS2 CAS6 CAS3 CAS7 VSS VSS DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VCC VCC DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VCC VCC ECC DQ55 VCC VCC A6 A7 A8 A11 VSS VSS A9 A12 A10 A13 VCC VCC CAS2 CAS6 CAS3 CAS7 VSS VSS DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VCC VCC DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VCC VCC DESCRIPTION Data 55 +5 Vdc +5 Vdc Address 6 Address 7 Address 8 Address 11 Ground Ground Address 9 Address 12 Address 10 Address 13 +5 Vdc +5 Vdc Column address strobe 2 Column address strobe 6 Column address strobe 3 Column address strobe 7 Ground Ground Data 24 Data 56 Data 25 Data 57 Data 26 Data 58 Data 27 Data 59 +5 Vdc +5 Vdc Data 28 Data 60 Data 29 Data 61 Data 30 Data 62 Data 31 Data 63 Ground Ground
+5 Vdc +5 Vdc
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TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NON-PARITY VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 n/c n/c VSS n/c n/c VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 PARITY VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS n/c n/c VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 72 ECC VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS n/c n/c VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 80 ECC VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 DESCRIPTION Ground Data 0 Data 1 Data 2 Data 3 +5 Vdc or +3.3 Vdc Data 4 Data 5 Data 6 Data 7 Data 8 Ground Data 9 Data 10 Data 11 Data 12 Data 13 +5 Vdc or +3.3 Vdc Data 14 Data 15 Parity/check-bit input/output 0 Parity/check-bit input/output 1 Ground Parity/check-bit input/output 8 Parity/check-bit input/output 9 +5 Vdc or +3.3 Vdc Read/write input Column address strobe 0 Column address strobe 1 Row address strobe 0 Output enable Ground Address 0 Address 2 Address 4 Address 6 Address 8 Address 10 Address 12 +5 Vdc or +3.3 Vdc +5 Vdc or +3.3 Vdc Dont use Ground Output enable 2
2
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TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM (CONTINUED) PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 NON-PARITY RAS2 CAS2 CAS3 WE2 VCC n/c n/c n/c n/c VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 n/c DU n/c VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS n/c n/c n/c SDA SCL VCC VSS DQ32 DQ33 DQ34 PARITY RAS2 CAS2 CAS3 WE2 VCC n/c n/c CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 n/c DU n/c VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS n/c n/c n/c SDA SCL VCC VSS DQ32 DQ33 DQ34 72 ECC RAS2 CAS2 CAS3 WE2 VCC n/c n/c CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 n/c DU n/c VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS n/c n/c n/c SDA SCL VCC VSS DQ32 DQ33 DQ34 80 ECC RAS2 CAS2 CAS3 WE2 VCC CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 n/c DU n/c VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS n/c n/c n/c SDA SCL VCC VSS DQ32 DQ33 DQ34 DESCRIPTION Row address strobe 2 Column address strobe 2 Column address strobe 3 Read/write Input 2 +5 Vdc or +3.3 Vdc Parity/check bit input/output 10 Parity/check bit input/output 11 Parity/check bit input/output 2 Parity/check bit input/output 3 Ground Data 16 Data 17 Data 18 Data 19 +5 Vdc or +3.3 Vdc Data 20 Not connected Dont use Not connected Ground Data 21 Data 22 Data 23 Ground Data 24 Data 25 Data 26 Data 27 +5 Vdc or +3.3 Vdc Data 28 Data 29 Data 30 Data 31 Ground Not connected Not connected Not connected Serial data Serial clock +5 Vdc or +3.3 Vdc Ground Data 32 Data 33 Data 34
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TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM (CONTINUED) PIN 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 NON-PARITY DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 n/c n/c VSS n/c n/c VCC DU CAS4 CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU PARITY DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS n/c n/c VCC DU CAS4 CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU 72 ECC DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS n/c n/c VCC DU CAS4 CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU 80 ECC DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VCC DU CAS4 CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU DESCRIPTION Data 35 +5 Vdc or +3.3 Vdc Data 36 Data 37 Data 38 Data 39 Data 40 Ground Data 41 Data 42 Data 43 Data 44 Data 45 +5 Vdc or +3.3 Vdc Data 46 Data 47 Parity/check bit input/output 4 Parity/check bit input/output 5 Ground Parity/check bit input/output 12 Parity/check bit input/output 13 +5 Vdc or +3.3 Vdc Dont use Column address strobe 4 Column address strobe 5 Row address strobe 1 Dont use Ground Address 1 Address 3 Address 5 Address 7 Address 9 Address 11 Address 13 +5 Vdc or +3.3 Vdc Dont use Dont use Ground Dont use Column address strobe 3 Column address strobe 6 Column address strobe 7 Dont use
2
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TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM (CONTINUED) PIN 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 NON-PARITY VCC n/c n/c n/c n/c VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 n/c DU n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC PARITY VCC n/c n/c CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 n/c DU n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC 72 ECC VCC n/c n/c CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 n/c DU n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC 80 ECC VCC CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 n/c DU n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC DESCRIPTION +5 Vdc or +3.3 Vdc Parity/check bit input/output 14 Parity/check bit input/output 15 Parity/check bit input/output 6 Parity/check bit input/output 7 Ground Data 48 Data 49 Data 50 Data 51 +5 Vdc or +3.3 Vdc Data 52 Not connected Dont use Not connected Ground Data 53 Data 54 Data 55 Ground Data 56 Data 57 Data 58 Data 59 +5 Vdc or +3.3 Vdc Data 60 Data 61 Data 62 Data 63 Ground Not connected Serial address 0 Serial address 1 Serial address 2 +5 Vdc or +3.3 Vdc
TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM PIN 1 2 3 4 NON-PARITY VSS DQ0 DQ1 DQ2 72 ECC VSS DQ0 DQ1 DQ2 80 ECC VSS DQ0 DQ1 DQ2 DESCRIPTION Ground Data 0 Data 1 Data 2
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TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM (CONTINUED) PIN 4 48 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 NON-PARITY DQ2 DU DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 n/c n/c VSS n/c n/c VDD WE DQMB0 DQMB1 S0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CK0 VSS DU S2 DQMB2 DQMB3 72 ECC DQ2 DU DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS n/c n/c VDD WE DQMB0 DQMB1 S0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CK0 VSS DU S2 DQMB2 DQMB3 80 ECC DQ2 DU DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VDD WE DQMB0 DQMB1 S0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CK0 VSS DU S2 DQMB2 DQMB3 DESCRIPTION Data 2 Dont use Data 3 +5 Vdc or +3.3 Vdc Data 4 Data 5 Data 6 Data 7 Data 8 Ground Data 9 Data 10 Data 11 Data 12 Data 13 +5 Vdc or +3.3 Vdc Data 14 Data 15 Parity/check-bit input/output 0 Parity/check-bit input/output 1 Ground Parity/check-bit input/output 8 Parity/check-bit input/output 9 +5 Vdc or +3.3 Vdc Read/-write Byte mask signal 0 Byte mask signal 1 Chip select Dont use Ground Address 0 Address 2 Address 4 Address 6 Address 8 Address 10 Bank address 1 +5 Vdc or +3.3 Vdc +5 Vdc or +3.3 Vdc Clock signal 0 Ground Dont use Chip select 2 Byte mask signal 2 Byte mask signal 3
2
762
TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM (CONTINUED) PIN 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82S 83S 84 85 86 87 88 89 90 91 92 NON-PARITY DU VDD n/c n/c n/c n/c VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 n/c Vref,NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 n/c n/c DAS CLS VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 72 ECC DU VDD n/c n/c CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 n/c Vref,NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 n/c n/c DAS CLS VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 80 ECC DU VDD CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 n/c Vref,NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 n/c n/c DAS CLS VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DESCRIPTION Dont use +5 Vdc or +3.3 Vdc Parity/check-bit input/output 10 Parity/check-bit input/output 11 Parity/check-bit input/output 2 Parity/check-bit input/output 3 Ground Data 16 Data 17 Data 18 Data 19 +5 Vdc or +3.3 Vdc Data 20 Not connected Clock enable signal 1 Ground Data 21 Data 22 Data 23 Ground Data 24 Data 25 Data 26 Data 27 +5 Vdc or +3.3 Vdc Data 28 Data 29 Data 30 Data 31 Ground Clock signal 2 Not connected Not connected Serial data Serial clock +5 Vdc or +3.3 Vdc Ground Data 32 Data 33 Data 34 Data 35 +5 Vdc or +3.3 Vdc Data 36 Data 37
763
TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM (CONTINUED) PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 NON-PARITY DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 n/c n/c VSS n/c n/c VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 VSS CKE0 S3 DQMB6 DQMB7 A13 VDD n/c n/c n/c n/c 72 ECC DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS n/c n/c VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 VSS CKE0 S3 DQMB6 DQMB7 A13 VDD n/c n/c CB6 CB7 80 ECC DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 VSS CKE0 S3 DQMB6 DQMB7 A13 VDD CB14 CB15 CB6 CB7 DESCRIPTION Data 38 Data 39 Data 40 Ground Data 41 Data 42 Data 43 Data 44 Data 45 +5 Vdc or +3.3 Vdc Data 46 Data 47 Parity/check-bit input/output 4 Parity/check-bit input/output 5 Ground Parity/check-bit input/output 12 Parity/check-bit input/output 13 +5 Vdc or +3.3 Vdc Column address strobe Byte mask signal 4 Byte mask signal 5 Chip select 1 Row address strobe Ground Address 1 Address 3 Address 5 Address 7 Address 9 Bank address 0 Address 11 +5 Vdc or +3.3 Vdc Clock signal 1 Address 12 Ground Clock enable signal 0 Chip Select 3 Byte mask signal 6 Byte mask signal 7 Address 13 +5 Vdc or +3.3 Vdc Parity/check-bit input/output 14 Parity/check-bit input/output 15 Parity/check-bit input/output 6 Parity/check-bit input/output 7
2
764
TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM (CONTINUED) PIN 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 NON-PARITY VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 n/c Vref,NC n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD 72 ECC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 n/c Vref,NC n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD 80 ECC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 n/c Vref,NC n/c VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD DESCRIPTION Ground Data 48 Data 49 Data 50 Data 51 +5 Vdc or +3.3 Vdc Data 52 Not connected Not connected Ground Data 53 Data 54 Data 55 Ground Data 56 Data 57 Data 58 Data 59 +5 Vdc or +3.3 Vdc Data 60 Data 61 Data 62 Data 63 Ground Clock signal 3 Not connected Serial address 0 Serial address 1 Serial address 2 +5 Vdc or +3.3 Vdc
to be exactbut manufacturers often round down to the nearest million or so). The idea of megabytes (MB) is important when measuring memory in your PC. For example, if a SIMM is laid out as 1M by 8 bits, it has 1MB. If the SIMM is laid out as 4M by 8 bits, it has 4MB. Unfortunately, memory has not been laid out as 8 bits since the IBM XT. More practical memory layouts involve 32-bit memory (for 486 and OverDrive processors) or 64-bit memory (for Pentium processors). When memory is wider than one byte, it is still measured in MB. For example, a 1M 32-bit (4 bytes) SIMM would be 4MB (that is, the capacity of the device is 4MB), and a 4M 32-bit SIMM would be 16MB. So when you go shopping for an 8MB 72-pin SIMM, chances are that youre getting a 2M 32-bit memory module. Table 23-7 provides you with an index to help identify common 72-pin SIMMs. You can see the relationship between memory layout and overall capacity.
MEMORY ORGANIZATION
765
TABLE 23-7 72-PIN SIMM IDENTIFICATION GUIDELINES CONFIGURATION 36 chips: (36) 16 1 SOJs or 12 chips: (8) 16 4, (4) 16 1 SOJs 24 chips: (16) 4 4 SOJs, (8) 4 1 SOJs 12 chips: (8) 4 4 SOJs, (4) 4 1 SOJs 24 chips: (16) 1 4 SOJs, (8) 1 1 SOJs 12 chips: (8) 1 4 SOJs, (4) 1 1 SOJs 4 chips: (4) 256 18 SOJs or 24 chips: (16) 256 4 SOJs, & (8) 256 1 PLCC 12 chips: (8) 256 4 SOJs, & (4) 256 1 PLCC 32 chips: (32) 16 1 SOJs or 8 chips: (8) 16 4 SOJs 16 chips: (16) 4 4 SOJs 8 chips: (8) 4 4 SOJs 16 chips: (16) 1 4 SOJs or 4 chips: (4) 1 16 SOJs 8 chips: (8) 1 4 SOJs or 2 chips: (2) 1 16 SOJs 16 chips: (16) 256 4 SOJs 8 chips: (8) 256 4 SOJs DESCRIPTION Parity SIMM, usually double sided Parity SIMM, usually double sided Parity SIMM, double or single sided Parity SIMM, usually double sided Parity SIMM, double or single sided Parity SIMM, usually double sided CAPACITY 64MB 32MB 16MB 8MB 4MB 2MB TYPE 16 36 8 36 4 36 2 36 1 36 512 36
Parity SIMM Non-parity SIMM, usually double sided Non-parity SIMM, usually double sided Non-parity SIMM, usually single sided Non-parity SIMM, usually double sided Non-parity SIMM, usually single sided Non-parity SIMM, usually double sided Non-parity SIMM
1MB 64MB 32MB 16MB 8MB 4MB 2MB 1MB
256 36 16 32 8 32 4 32 2 32 1 32 512 32 256 32
2
Memory Organization
The memory in your computer represents the result of evolution over several computer generations. Memory operation and handling is taken care of by your systems microprocessor. As CPUs improved, memory-handling capabilities have improved as well. Todays microprocessors, such as the Intel Pentium or Pentium Pro, are capable of addressing more than 4GB of system memorywell beyond the levels of contemporary software applications. Unfortunately, the early PCs were not nearly so powerful. Older PCs could only address 1MB of memory because of the limitations of the 8088 microprocessor. Because backward compatibility is so important to computer users, the drawbacks and limitations of older systems had to be carried forward into newer computers, instead of being eliminated. Newer systems overcome their inherent limitations by adding different types of memory, along with the hardware and software to access the memory. This part of the chapter describes the typical classifications of computer memory: conventional, extended, and expanded memory. This chapter also describes high memory concepts. Notice that these memory types have nothing to do with the actual ICs in your system, but the way in which software uses the memory.
CONVENTIONAL MEMORY
Conventional memory is the traditional 640KB assigned to the DOS Memory Area (10000h to 9FFFFh, as shown in Fig. 23-4). The original PCs used microprocessors that
766
1024Kb System ROM
FFFFFh F0000h System ROM E0000h Optional/user ROM D0000h Optional/user ROM C0000h Video RAM Video RAM B0000h A0000h User area 90000h User area 70000h User area 50000h User area System/user area 10000h User area 00000h Conventional and upper memory in a typical PC. 30000h
640Kb
0Kb
FIGURE 23-4
could only address 1MB of memory (called real-mode memory or base memory). Out of that 1MB, portions of the memory must be set aside for basic system functions. BIOS code, video memory, interrupt vectors, and BIOS data are only some of the areas that require reserved memory. The remaining 640KB became available to load and run your application, which can be any combination of executable code and data. The original PC only provided 512KB for the DOS program area, but computer designers quickly learned that another 128KB could be added to the DOS area while still retaining enough memory for overhead functions, so 512KB became 640KB. Every IBM-compatible PC still provides a 640KB base memory range, and most DOS application programs continue to fit within that limit to ensure backward compatibility to older systems. However, the drawbacks to the 8088 CPU were soon apparent. More memory had to added to the computer for its evolution to continue. Yet, memory had to be added in a way that did not interfere with the conventional memory area. Table 23-8 illustrates a comprehensive memory map for a typical PC.
EXTENDED MEMORY
The 80286 introduced in IBMs PC/AT was envisioned to overcome the 640KB barrier by incorporating a protected mode of addressing. The 80286 can address up to 16MB of memory in protected mode, and its successors (the 80386 and later) can handle 4GB of protected-
MEMORY ORGANIZATION
767
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC ADDRESS RANGE (H) 00000003FF 00000 00004 00008 0000C 00010 00014 00018 0001C 00020 00024 00028 0002C 00030 00034 00038 0003C 00040 00044 00048 0004C 00050 00054 00058 0005C 00060 00064 00068 0006C 00070 00074 00078 0007C 00080 00084 00088 0008C 00090 00094 00098 0009C 000A0
DESCRIPTION Interrupt Vector Table (256 double words): INT 00H Divide-by-zero interrupt handler INT 01H Single-step interrupt handler INT 02H Non-maskable interrupt (memory parity or I/O error) INT 03H Breakpoint INT 04H Arithmetic overflow interrupt handler INT 05H Print screen INT 06H Reserved INT 07H Reserved INT 08H Timer-interrupt routine (18.21590 /sec) IRQ0 INT 09H Keyboard service routine IRQ1 INT 0AH VGA retrace (and AT slave interrupts) IRQ2 INT 0BH Serial device 2 service routine IRQ3 INT 0CH Serial device 1 service routine IRQ4 INT 0DH Hard-disk interrupt routine IRQ5 INT 0EH Diskette interrupt routine IRQ6 INT 0FH Parallel-port service routine IRQ7 INT 10H Video services INT 11H Equipment check INT 12H Memory-size check INT 13H Diskette and hard disk I/O INT 14H RS-232 service call INT 15H System services calls INT 16H Keyboard call INT 17H Printer I/O call INT 18H Basic ROM entry (startup) INT 19H Boot loader: implement system (IPL) from disk INT 1AH Time-of-day call INT 1BH Keyboard break address INT 1CH User timer interrupt INT 1DH Monitor ROMfor 6845 video inititialization INT 1EH Disk-control table pointer INT 1FH Alphanumeric character pattern table pointer INT 20H DOS terminate program INT 21H Microsoft DOS function calls INT 22H DOS terminate address (not a callable function) INT 23H DOS Ctrl-break exit address (not a callable function) INT 24H DOS fatal-error exit address (not a callable function) INT 25H DOS absolute disk read INT 26H DOS absolute disk write INT 27H Terminate and stay resident (control passes to COMMAND.COM) INT 28H Idle loop, spooler waiting; issued by DOS when waiting
2
768
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 000A4 000A8 000AC 000B8 000BC 000C0 000C8 000CC 000D0 000FC 00100 00104 00108 0010C 00100 00114 00118 0011C 00120 00124 00128 0012C 00140 00144 00168 0016C 00170 00174 00180 0019C 001A0 001B0 001B4 001C0 001C4 001C8 001CC 001D0 001D4 001D8 001DC 001E0
DESCRIPTION INT 29H CON device raw output handler INT 2AH 3.x Network communications INT 2BH-2DH reserved for DOS INT 2EH Execute DOS command (undocumented) INT 2FH Print spool control (Multiplex Interrupt) INT 30H-31H Internal use INT 32H Reserved for DOS INT 33H Microsoft mouse-driver calls INT 34H-3EH Reserved for DOS INT 3FH Used by LINK to manage overlay segments INT 40H Fixed-disk/floppy-disk handler INT 41H ROM pointer; fixed-disk parameters INT 42H EGA: video vector screen BIOS entry INT 43H EGA: Initialization parameters INT 44H EGA: Graphics-character patterns INT 45H Reserved INT 46H AT: Pointer to second fixed disk parameters INT 47H Reserved INT 48H PCjr cordless-keyboard Xlat routine INT 49H PCjr non-keyboard scan-code Xlat table INT 4AH AT, PS/2 user alarm routine INT 4BH-4FH Reserved INT 50H Periodic alarm interrupt from timer INT 51H-59H Reserved INT 5AH Cluster adapter BIOS-entry address INT 5BH Cluster boot INT 5CH NETBIOS entry point INT 5DH-5FH Reserved INT 60H-66H Reserved for user program interrupts INT 67H EMM: Expanded memory manager routines INT 68H-6BH Unused INT 6CH System-resume vector INT 6DH-6FH Unused INT 70H Real-time clock INT 71H LAN adapter INT 72H Reserved INT 73H Reserved INT 74H Mouse interrupt INT 75H 80287 NMI Error INT 76H Fixed disk controller INT 77H Reserved INT 78H-7FH Unused
IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
MEMORY ORGANIZATION
769
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 00200 00218 0021C 003C4 003FF 00400-004FF 00400 00408 0040E 00410
DESCRIPTION INT 80H-85H Reserved for BASIC INT 86H AT: NetBIOS relocated INT 18H INT 87H-F0H Reserved for BASIC interpreter INT F1H-FFH Reserved for user program interrupts Used for power-on and initial boot stack BIOS Data Area: COM1: to COM4: port addresses LPT1: to LPT3: port addresses LPT4: address except PS/2 reserved Equipment flag bits: 1514 Number of LPTs attached 13 Internal modem (CVT) or reserved 12 Joystick 119 Number of COMs 8 Unused (jr: DMS chip present) 76 Number of disk drives 5 1 = 80 25 0 = 40 25 screen 4 1 = color 0 = monochrome 32 00 = 64K chips; 11 = 256K chips (PC,XT,AT) 1 Math coprocessor installed 0 IPL disk installed Init. flag; reserved (CVT self-test status) Memory size in K bytes Reserved Reserved Keyboard monitor flag bytes 0 and 1: bit: 7 ins lock 7 ins pressed 6 caps lock 6 caps pressed 5 num lock 5 num lock pressed 4 scroll lock 4 scroll pressed 3 alt pressed 3 pause locked 2 crtl pressed 2 sysreq pressed 1 <shift press 1 <alt pressed 0 >shift press 0 >alt pressed Alternate keypad entry Keyboard buffer head pointer Keyboard buffer tail pointer Keyboard buffer Drive recalibration status bit: 7 Interrupt flag 64 Reserved 3 Recalibrate drive 3 2 Recalibrate drive 2 1 Recalibrate drive 1 0 Recalibrate drive 0
2
00412 00413 00415 00416 00417
00419 0041A 0041C 0041E 0043E
770
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 0043F
DESCRIPTION Motor status bit: 7 Currently reading or writing 6 Reserved 54 00 Drive 0 Selected 01 Drive 1 Selected 10 Drive 2 Selected 11 Drive 3 Selected 3-0 Drive 3-0 motor on status Motor-control time-out counter Diskette Status Return Code 00H No error 01H Invalid diskette drive parameter 02H Address mark not found 03H Write-protect error 04H Requested sector not found 05H Reserved 06H Diskette change line active 07H Reserved 08H DMA overrun on operation 09H Attempt to DMA across a 64K boundary 0AH Reserved 0BH Reserved 0CH Media type not found 0DH Reserved 0EH Reserved 0FH Reserved 10H CRC error on diskette read 20H General controller failure 40H Seek operation failed 80H Diskette drive not ready Diskette drive controller status bytes (NEC) CRT_MODE bit: 7 Text 80 25 mono on mono card 6 Graphics 640 200 mono on color card 5 Graphics 320 200 mono on color card 4 Graphics 320 200 on color card 3 Text 80 25 color 2 Text 80 25 mono on color 1 Text 40 25 color 0 Text 40 25 mono on color card CRT_COLS Number of columns (80) CRT_LEN Length of regen buffer in bytes CRT_START Starting address in regen buffer Cursor position on each of eight pages CURSOR_MODE top-bottom line of cursor (cursor type) ACTIVE_PAGE index ADDR_6845 Base address for 6845 display chip 3B4H for monochrome 3D4H for color
00440 00441
00442 00449
0044A 0044C 0044E 00450 00460 00462 00463
MEMORY ORGANIZATION
771
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 00465
DESCRIPTION CRT_MODE_SETTING for 3 x 8 register 3B8H for MDA 3D8H for CGA CRT_PALLETTE setting register (3D9H) on color card Temporary storage for SS:SP during shutdown Flag to indicate interrupt Timer counter (timer low, timer high words) Timer overflow (24-hour roll-over flag byte) Break key state (bit 7 = 1 if break key pressed) Reset flag word: 1234 bypass memory test 4321 preserve memory 5678 system suspend 9ABC manufacturing test ABCD system POST loop (CVT) Hard-disk status or reserved for ESDI Adapter/A 00H No error 01H Invalid function request 02H Address mark not found 03H Write protect error 04H Requested sector not found 05H Reset failed 06H Reserved 07H Drive parameter activity failed 08H DMA overrun on operation 09H Data boundary error 0AH Bad sector flag detected 0BH Bad track detected 0CH Reserved 0DH Invalid number of sectors on format 0EH Control data address mark detected 0FH DMA arbitration level out of range 10H Uncorrectable ECC or CRC error 20H General controller failure 40H Seek operation failed 80H Time out AAH Drive not ready BBH Undefined error occurred CCH Write fault on selected drive E0H Status error/error register 0 FFH Sense operation failed Number of hard-disk drives Fixed disk-drive control byte (PC XT) Fixed disk-drive controller port (PC XT) LPT1: to LPT4: time-out byte values (PS/2 has no LPT4:) COM1: to COM4: timeout byte values Keyboard buffer start pointer (word) Keyboard buffer end pointer (word)
00466 00467 0046B 0046C 00470 00471 00472
2
00474
00475 00476 00477 00478 0047C 00480 00482
772
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 00484 00485 00487
DESCRIPTION ROWS video character Rows - 1 POINTS Height of character matrix-bytes per character INFO byte: bit: 7 Video mode number (of INT 10H funct.0) 65 Size of video RAM 0064K 10192K 01128K 11256K 4 reserved 3 (1) video subsystem is inactive 2 reserved 1 (1) video subsystem on monochrome 0 (1) alphanumeric cursor emulation enabled INFO_3 byte: bit: 7 Input FEAT1 (bit 6 of ISR0 (Input Status Reg.) 6 Input FEAT1 (bit 5 of ISR0) 5 Input FEAT0 (bit 6 of ISR0) 4 Input FEAT0 (bit 5 of ISR0) 3 EGA config. switch 4 (1=off) 2 EGA config. switch 3 1 EGA config. switch 2 0 EGA config. switch 1 Flags bit: 7 bit 4 Alphanumeric scan lines: 00 350-line mode 01 400 10 200 11 Reserved 6 (1) Display switching enabled 5 Reserved 3 (1) Default palett loading is disabled 2 (1) Using monochrome monitor 1 (1) Gray scale is enabled 0 (1) VGA is active DCC Display combination code table index (VGA) Media control bit: 76 Last diskette drive data rate selected 00500Kb per second 01300Kb per second 10250Kb per second 11reserved 54 Last diskette drive step rate selected 30 reserved Hard-disk status register Hard-disk error register Hard-disk interrupt control flag Combination hard disk/floppy card (bit 0=1) Drive-0 media-state byte Drive-1 media-state byte
00488
00489
0048A 0048B
0048C 0048D 0048E 0048F 00490 00491
MEMORY ORGANIZATION
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TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 00492 00493
DESCRIPTION Drive 2 media state byte Drive 3 media state byte bit: 76 Diskette drive date rate 00500Kb per second 01300Kb per second 10250Kb per second 11Reserved 5 Double stepping required 4 Media established 3 Reserved 20 Drive/media state 000 360Kb diskette/360Kb drive not established 001 360Kb diskette/1.2Mb drive not established 010 1.2Mb diskette/1.2Mb drive not established 011 360Kb diskette/360Kb drive established 100 360Kb diskette/1.2Mb drive established 101 1.2Mb diskette/1.2Mb drive established 110 Reserved 111 None of the above Drive 0 track currently selected Drive 1 track currently selected Keyboard mode state and type flags bit: 7 Read ID in progress 6 Last character was first ID character 5 Force NumLock if read ID and KBX 4 101/102 keyboard installed 3 Right Alt key pressed 2 Right Ctrl key pressed 1 Last code was E0 hidden code 0 Last code was E1 hidden code Keyboard LED flags bit: 7 Keyboard transmit error flag 6 Mode-indicator update 5 Cancel receive flag 4 Acknowledgment received 3 = 0 reserved 2-0 Keyboard LED state bits Offset address to user wait complete flag Segment to user wait complete flag User wait count, microseconds low word User wait count, microseconds high word Wait active flag bit: 7 Wait-time elapse and post flag 61 Reserved LANA DMA channel flags LANA 0 status LANA 1 status Saved hardfile interrupt vector
2
00494 00495 00496
00497
00498 0049A 0049C 0049E 004A0
004A1 004A2 004A3 004A4
774
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 004A8 004AC 004B4 004B5 004B9 004BA 004BB 004BC 004BD 004CE 004D0 004F0 00500005FF 00500
DESCRIPTION BIOS video save table and overrides Reserved Keyboard NMI control flags (CVT) Keyboard break-pending flags (CVT) Port-60 single-byte queue (CVT) Scan code of last key (CVT) Pointer-to-NMI buffer head (CVT) Pointer-to-NMI buffer tail (CVT) NMI scan-code buffer (CVT) Day counter (CVT and after) Reserved Application program communication area DOS Data Area: Print-screen status flag 1 = printer active 0FFH = printer fault Reserved for BASIC and POST work area Single-drive mode-status byte 0 = drive A 1 = drive B Reserved POST work area Reserved for BASIC BASIC Shell Flag = 2 if current shell BASIC segment address storage set with DEF SEG BASIC int 1Ch clock-interrupt vector BASIC int 23h ctrl-break interrupt vector BASIC int 24h disk-error interrupt vector BASIC dynamic storage DOS dynamic storage Used by DOS for diskette initialization Used by MODE command Reserved for DOS data Reserved for DOS I/O drivers from xIO.SYS xIO.SYS IRET for interrupts 1, 3, and 0FH during POST MS-DOS kernel from xDOS.SYS: Interrupt handlers and routines MS-DOS disk-buffer cache, FCBs and installable device drivers MCB (Memory control block, 16 bytes, paragraph aligned) Start of transient program
00501 00504
00505 00510 0050F 00510 00512 00516 0051A 0051B 00520 00522 00530 00534 00600 00700 008470FFFF
MEMORY ORGANIZATION
775
TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED) ADDRESS RANGE (H) 100009FFFF A0000AFFFF B0000B3FFF B4000B7FFF B8000BBFFF BC000BFFFF C0000C3FFF C4000C5FFF C6000C63FF C6400C7FFF C8000CBFFF CC000CFFFF D0000D7FFF D8000DBFFF DC000DFFFF E0000EFFFF F0000F3FFF F4000F7FFF F8000FBFFF FC000FEFFF FF000FFFEF FFFF0FFFF3
DESCRIPTION User Data Area (programs and data) Start of EGA and VGA graphics-display RAM modes 0Dh and above Start of MDPA and Hercules graphics-display RAM Reserved for graphics-display RAM Start of CGA color graphics-display RAM Reserved for graphics-display RAM EGA BIOS ROM Video-adapter ROM space 256 bytes of PGA communication area Last 7Kb of video adapter ROM space 16K of hard-disk BIOS adapter ROM space 32K cluster-adapter BIOS ROM Last 16Kb of adapter ROM space 64K expansion ROM space (AT, PS/2) System-monitor ROM System-expansion ROMs BIOS ROM, BASIC, and simple BIOS System ROM Hardware boot far jump vector
2
mode memory. Today, virtually all computer systems provide several MB of extended memory. Besides an advanced microprocessor, another key element for extended memory is software. Memory-management software must be loaded in advance for the computer to access its extended memory. Microsofts DOS 5.0 provides an extended memory manager utility (HIMEM.SYS), but other off-the-shelf utilities are available as well. Unfortunately, DOS itself cannot use extended memory. You might fill the extended memory with data, but the executable code comprising the program remains limited to the original 640KB of base memory. Some programs written with DOS extenders can overcome the 640KB limit, but the additional code needed for the extenders can make such programs a bit clunky. A DOS extender is basically a software module containing its own memory-management code, which is compiled into the final application program. The DOS extender loads a program in real-mode memory. After the program is loaded, it switches program control to the protected-mode memory. When the program in protected mode needs to execute a DOS (real mode) function, the DOS extender converts protectedmode addresses into real-mode addresses, copies any necessary program data from protected to real-mode locations, switches the CPU to real-mode addressing, and carries out the function. The DOS extender then copies any results (if necessary) back to protected-mode addresses, switches the system to protected-mode once again, and the program continues to
776
run. This back-and-forth conversion overhead results in less-than-optimum performance, compared to strictly real-mode programs or true protected-mode programs. With multiple megabytes of extended memory typically available, it is possible (but unlikely) that any one program will utilize all of the extended memory. Multiple programs that use extended memory must not attempt to utilize the same memory locations. If conflicts occur, a catastrophic system crash is almost inevitable. To prevent conflicts in extended memory, memory-manager software can make use of three major industry standards: the Extended Memory Specification (XMS), the Virtual Control Program Interface (VCPI), or the DOS Protected-Mode Interface (DPMI). This chapter does not detail these standards, but you should know where they are used.
EXPANDED MEMORY
Expanded memory is another popular technique used to overcome the traditional 640KB limit of real-mode addressing. Expanded memory uses the same physical RAM chips, but differs from extended memory in the way that physical memory is used. Instead of trying to address physical memory locations outside of the conventional memory range, as extended memory does, expanded memory blocks are switched into the base memory range, where the CPU can access it in real mode. The original expanded memory specification (called the Lotus-Intel-Microsoft LIM or EMS specification) used 16KB banks of memory which were mapped into a 64KB range of real-mode memory existing just above the video memory range. Thus, four blocks of expanded memory could be dealt with simultaneously in the real mode. Early implementations of expanded memory utilized special expansion boards that switched blocks of memory, but later CPUs that support memory mapping allowed expanded memory managers (EMMs or LIMs) to supply software-only solutions for i386, i486, and Pentium-based machines. EMS/LIM 4.0 is the latest version of the expanded memory standard which handles up to 32MB of memory. An expanded memory manager (such as the DOS utility EMM386.EXE) allows the extended memory sitting in your computer to emulate expanded memory. For most practical purposes, expanded memory is more useful than extended memory because its ability to map directly to the real mode allows support for program multi-tasking. To use expanded memory, programs must be written specifically to take advantage of the function calls and subroutines needed to switch memory blocks. Functions are completely specified in the LIM/EMS 4.0 standard.
UPPER MEMORY AREA (UMA)

The upper 384KB of real-mode memory is not available to DOS because it is dedicated to handling memory requirements of the physical computer system. This is called the High DOS Memory Range or Upper Memory Area (UMA). However, even the most advanced PCs do not use the entire 384KB, so there is often a substantial amount of unused memory existing in your systems real-mode range. Late-model CPUs, such as the i386 and i486 can remap extended memory into the range unused by your system. Because this found memory space is not contiguous with your 640KB DOS space, DOS application programs cannot use the space, but small independent drivers and TSRs can be loaded and run from this UMA. The advantage to using high DOS memory is that more of the 640KB DOS range remains available for your application program. Memory-management programs (such as the utilities found with DOS 5.0 and higher) are needed to locate and remap these memory blocks.
MEMORY CONSIDERATIONS
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HIGH MEMORY
A peculiar anomaly occurs with CPUs that support extended memorythey can access one segment (about 64KB) of extended memory beyond the real-mode area. This capability arises because of the address line layout on late-model CPUs. As a result, the realmode operation can access roughly 64KB above the 1MB limit. Like high DOS memory, this found 64KB is not contiguous with the normal 640KB DOS memory range, so DOS cannot use this high memory to load a DOS application, but device drivers and TSRs can be placed in high memory. DOS 5.0 is intentionally designed so that its 40 to 50KB of code can be easily moved into this high memory area. With DOS loaded into high memory, an extra 40 to 50KB or so will be available within the 640KB DOS range.
Memory Considerations
Memory has become far more important than just a place to store bits for the microprocessor. It has proliferated and specialized to the point where it is difficult to keep track of all the memory options and architectures that are available. This part of the chapter reviews established memory types, and explains some of the current memory architectures.
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MEMORY SPEED AND WAIT STATES

The PC industry is constantly struggling with the balance between price and performance. Higher prices usually bring higher performance, but low cost makes the PC appealing to more people. In terms of memory, cost-cutting typically involves using cheaper (slower) memory devices. Unfortunately, slow memory cannot deliver data to the CPU quickly enough, so the CPU must be made to wait until memory can catch up. All memory is rated in terms of speedspecifically, access time. Access time is the delay between the time data in memory is successfully addressed, to the point at which the data has been successfully delivered to the data bus. For PC memory, access time is measured in nanoseconds (ns), and current memory offers access times of 50 to 60 ns. 70-ns memory is extremely common. The question often arises: Can I use faster memory than the manufacturer recommends? The answer to this question is almost always Yes, but rarely does performance benefit. As you will see in the following sections, memory and architectures are typically tailored for specific performance. Using memory that is faster should not hurt the memory or impair system performance, but it costs more and will not produce a noticeable performance improvement. The only time such a tactic would be advised is when your current system is almost obsolete, and you would want the new memory to be useable on a new, faster motherboard if you choose to upgrade the motherboard later on. A wait state orders the CPU to pause for one clock cycle to give memory additional time to operate. Typical PCs use one wait state, although very old systems might require two or three. The latest PC designs with high-end memory or aggressive caching might be able to operate with no (zero) wait states. As you might imagine, a wait state is basically a waste of time, so more wait states result in lower system performance. Zero wait states allow optimum system performance. Table 23-9 illustrates the general relationship between CPUs, wait states, and memory speed. It is interesting to note that some of the fastest systems allow the most wait states. This flexibility lets the system support old, slow memory,
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TABLE 23-9 CPUS, WAIT STATES, AND MEMORY SPEED CPU 8088 8086 80286 80286 80286 80386SX 80386SX/DX 80386SX 80386DX 80386SX 80486DX 80486DX 80486SLC2 80486SLC3 80486SX 80486DX4 80486DX2 Pentium Pentium WAIT STATES 1 0 1 1 0 02 02 02 05 02 05 05 02 02 02 02 02 05 02 MEMORY ACCESS 200 ns 150 ns 150 ns 120 ns 85 ns 100 ns 85 ns 80 ns 80 ns 70 ns 80 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 60 ns 50 ns
but the resulting system performance would be so poor that there would be little point in using the system in the first place. There are three classic means of selecting wait states. First, the number of wait states might be fixed (common in old XT systems). Wait states might be selected with one or more jumpers on the motherboard (typical of i286 and early i386 systems). Current systems, such as i486 and Pentium computers, place the wait state control in the CMOS setup routine. You might have to look in an advanced settings area to find the entry. When optimizing a computer, you should be sure to set the minimum number of wait states.
Setting too few wait states can cause the PC to behave erratically.
DETERMINING MEMORY SPEED

It is often necessary to check SIMMs or DIMMs for proper memory speed during troubleshooting, or when selecting replacement parts. Unfortunately, it can be very difficult to determine memory speed accurately based on part markings. Speeds are normally marked cryptically by adding a number to the end of the part number. For example, a part number ending in -6 often means 60 ns, a 7 is usually 70 ns, and a 8 can be 80 ns. Still, the only way to be absolutely certain of the memory speed is to cross reference the memory part number with a manufacturers catalog, and read the speed from the catalogs description (i.e., 4M 32 50 ns EDO).
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PRESENCE DETECT (PD)

Another feature of modern memory devices is a series of signals known as the Presence Detect lines (youll see these as PDx signals in 72-pin pinouts, such as Table 23-2 and 233). By setting the appropriate conditions of the PD signals, it is possible for a computer to immediately recognize the characteristics of the installed memory devices, and configure itself accordingly. Presence detect lines typically specify three operating characteristics of memory: size (device layout) and speed. Table 23-10 highlights many of the most commonly used signal combinations.
UNDERSTANDING MEMORY REFRESH

The electrical signals placed in each DRAM storage cell must be replenished (or refreshed) periodically every few milliseconds. Without refresh, DRAM data will be lost. In principle, refresh requires that each storage cell be read and re-written to the memory array. This is typically accomplished by reading and re-writing an entire row of the array at one time. Each row of bits is sequentially read into a sense/refresh amplifier (part of the DRAM IC), which basically recharges the appropriate storage capacitors, then re-writes each row bit to the array. In actual operation, a row of bits is automatically refreshed whenever an array row is selected. Thus, the entire memory array can be refreshed by reading each row in the array every few milliseconds. The key to refresh is in the way DRAM is addressed. Unlike other memory ICs that supply all address signals to the IC simultaneously, a DRAM is addressed in a two-step sequence. The overall address is separated into a row (low) address and a column (high) address. Row
TABLE 23-10 INDEX OF PRESENCE DETECT (PD) SIGNALS PIN 67 (PD1) GND N/C GND N/C GND N/C GND N/C GND N/C GND N/C PIN 68 (PD2) N/C GND GND N/C N/C GND N/C GND GND N/C N/C GND PIN 69 (PD3) N/C GND N/C GND N/C PIN 70 (PD4) N/C N/C GND GND N/C PIN 71 (PD5) N/C N/C N/C N/C N/C N/C GND GND
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72-PIN SIMM Size (parity pinout) 256K 32/36 512K 32/36 1M 32/36 2M 32/36 4M 32/36 8M 32/36 256K 32/36 512K 32/36 1M 32/36 2M 32/36 4M 32/36 8M 32/36 60 ns 70 ns 80 ns 100 ns 120 ns
Size (ECC pinout)
Speed (parity/ECC pinout)
GND = Jumper installed N/C = No jumper installed
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address bits are placed on the DRAM address bus first, and the Row Address Select (RAS) line is pulsed logic 0 to multiplex the bits into the ICs address decoding circuitry. The low portion of the address activates an entire array row and causes each bit in the row to be sensed and refreshed. Logic 0s remain logic 0s and logic 1s are recharged to their full value. Column address bits are then placed on the DRAM address bus, and the Column Address Select (CAS) is pulsed to logic 0. The column portion of the address selects the appropriate bits within the chosen row. If a read operation is taking place, the selected bits pass through the data buffer to the data bus. During a Write operation, the Read/Write line must be logic 0, and valid data must be available to the IC before CAS is strobed. New data bits are then placed in their corresponding locations in the memory array. Even if the IC is not being accessed for reading or writing, the memory must still be refreshed to ensure data integrity. Fortunately, refresh can be accomplished by interrupting the microprocessor to run a refresh routine that simply steps through every row address in sequence (column addresses need not be selected for simple refresh). This row-only (or -RAS only) refresh technique speeds the refresh process. Although refreshing DRAM every few milliseconds might seem like a constant aggravation, the computer can execute quite a few instructions before being interrupted for refresh. Refresh operations are generally handled by the chipset on your motherboard. Often, memory problems (especially parity errors) that cannot be resolved by replacing a SIMM can be traced to a refresh fault on the motherboard.
MEMORY TYPES
For a computer to work, the CPU must take program instructions and exchange data directly with memory. As a consequence, memory must keep pace with the CPU (or make the CPU wait for it to catch up). Now that processors are so incredibly fast (and getting faster), traditional memory architectures are being replaced by specialized memory devices that have been tailored to serve specific functions in the PC. As you upgrade and repair various systems, you will undoubtedly encounter some of the following memory designations:
s DRAM (Dynamic Random-Access Memory) This remains the most recognized and
common form of computer memory. DRAM achieves a good mix of speed and density, while being relatively simple and inexpensive to produceonly a single transistor and capacitor is needed to hold a bit. Unfortunately, DRAM contents must be refreshed every few milliseconds or the contents of each bit location will decay. DRAM performance is also limited because of relatively long access times. Today, many video boards are using DRAM SIMMs to supply video memory. s SRAM (Static Random-Access Memory) The SRAM is also a classic memory design it is even older than DRAM. SRAM does not require regular refresh operations, and can be made to operate at access speeds that are much faster than DRAM. However, SRAM uses six transistors (or more) to hold a single bit. This reduces the density of SRAM and increases power demands (which is why SRAM was never adopted for general PC use in the first place). Still, the high speed of SRAM has earned it a place as the PCs L2 (or external) cache. Youll probably encounter three types of SRAM cache schemes: asynchronous, synchronous burst, and pipeline burst. s Asynchronous Static RAM (Async SRAM or ASRAM) This is the traditional form of L2 cache, introduced with i386 systems. Theres really nothing too special about ASRAM, except that its contents can be accessed much faster (20 ns, 15 ns, or 12 ns) than
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DRAM. ASRAM does not have enough performance to be accessed synchronously, and has long since been replaced by better types of cache. s Synchronous-Burst Static RAM (Sync SRAM or SBSRAM) This is largely regarded as the best type of L2 cache for intermediate-speed motherboards (~60 to 66MHz). With access times of 8.5 ns and 12 ns, the SBSRAM can provide synchronous bursts of cache information in 2-1-1-1 cycles (i.e., 2 clock cycles for the first access, then 1 cycles per accessin time with the CPU clock). However, as motherboards pass 66MHz (i.e., 75 and 83MHz designs), SBSRAM loses its advantage to Pipelined Burst SRAM. s Pipelined-Burst Static RAM (PB SRAM) At 4.5 to 8 ns, this is the fastest form of highperformance cache now available for 75MHz+ motherboards. PBSRAM requires an extra clock cycle for lead off, but then can sync with the motherboard clock (with timing such as 3-1-1-1) across a wide range of motherboard frequencies. If youre interested in more technical details about PBSRAM, check out the ASUS site at: http://asustek.asus.com.tw/Products/TB/mem-0001.html.
s VRAM (Video Random-Access Memory) DRAM has been the traditional choice for video
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memory, but the ever-increasing demand for fast video information (i.e., high-resolution SVGA displays) requires a more efficient means of transferring data to and from video memory. Originally developed by Samsung Electronics, video RAM achieves speed improvements by using a dual data bus scheme. Ordinary RAM uses a single data bus data enters or leaves the RAM through a single set of signals. Video RAM provides an input data bus and an output data bus. This allows data to be read from video RAM at the same time new information is being written to it. You should realize that the advantages of VRAM will only be realized on high-end video systems, such as 1024 768 256 (or higher), where you can get up to 40% more performance than a DRAM video adapter. Below that, you will see no perceivable improvement with a VRAM video adapter. s FPM DRAM (Fast-Page Mode DRAM) This is a popular twist on conventional DRAM. Typical DRAM access is accomplished in a fashion similar to reading from a booka memory page is accessed first, then the contents of that page can be located. The problem is that every access requires the DRAM to re-locate the page. Fast-page mode operation overcomes this delay by allowing the CPU to access multiple pieces of data on the same page without having to re-locate the page every timeas long as the subsequent read or write cycle is on the previously located page, the FPDRAM can access the specific location on that page directly. s EDRAM (Enhanced DRAM) This is another, lesser-known variation of the classic DRAM developed by Ramtron International and United Memories. First demonstrated in August 1994, the EDRAM eliminates an external cache by placing a small amount of static RAM (cache) into each EDRAM device itself. In essence, the cache is distributed within the system RAM; as more memory is added to the PC, more cache is effectively added as well. The internal construction of an EDRAM allows it to act like page-mode memoryif a subsequent read requests data that is in the EDRAMs cache (known as a hit), the data is made available in about 15 nsroughly equal to the speed of a fair external cache. If the subsequent read requests data that is not in the cache (called a miss), the data is accessed from the DRAM portion of memory in about 35 ns, which is still much faster than ordinary DRAM. s EDO RAM (Extended Data Output RAM) EDO RAM is a relatively well-established variation to DRAM, which extends the time that output data is validthus the words
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presence on the data bus is extended. This is accomplished by modifying the DRAMs output buffer, which prolongs the time where read data is valid. The data will remain valid until a motherboard signal is received to release it. This eases timing constraints on the memory and allows a 15 to 30% improvement in memory performance with little real increase in cost. Because a new external signal is needed to operate EDO RAM, the motherboard must use a chipset designed to accommodate EDO. Intels Triton chipset was one of the first to support EDO, although now most chipsets (and most current motherboards) currently support EDO. EDO RAM can be used in non-EDO motherboards, but there will be no performance improvement. BEDO (Burst Extended Data Output RAM) This powerful variation of EDO RAM reads data in a burst, which means that after a valid address has been provided, the next three data addresses can be read in only one clock cycle each. The CPU can read BEDO data in a 5-1-1-1 pattern (5 clock cycles for the first address, then one clock cycle for the next three addresses. Although BEDO offers an advantage over EDO, it is only supported currently by the VIA chipsets: 580VP, 590VP, 680VP. Also, BEDO seems to have difficulty supporting motherboards over 66MHz. SDRAM (Synchronous or Synchronized DRAM) Typical memory can only transfer data during certain portions of a clock cycle. The SDRAM modifies memory operation so that outputs can be valid at any point in the clock cycle. By itself, this is not really significant, but SDRAM also provides a pipeline burst mode that allows a second access to begin before the current access is complete. This continuous memory access offers effective access speeds as fast as 10 ns, and can transfer data at up to 100MB/s. SDRAM is becoming quite popular on current motherboard designs, and is supported by the Intel VX chipset, and VIA 580VP, 590VP, and 680VP chipsets. Like BEDO, SDRAM can transfer data in a 5-1-1-1 pattern, but it can support motherboard speeds up to 100MHz, which is ideal for the 75MHz and 82MHz motherboards now becoming so vital for Pentium II systems. Check out the following references for more information on SDRAM: ~http://www.chips.ibm.com/products/memory/sdramart/sdramart.html ~http://www.fujitsu-ede.com/sdram/index.html ~http://www.ti.com/sc/docs/memory/brief.htm CDRAM (Cached DRAM) Like EDRAM, the CDRAM from Mitsubishi incorporates cache and DRAM on the same IC. This eliminates the need for an external (or L2) cache, and has the extra benefit of adding cache whenever RAM is added to the system. The difference is that CDRAM uses a set-associative cache approach that can be 15 to 20% more efficient than the EDRAM cache scheme. On the other hand, EDRAM appears to offer better overall performance. RDRAM (Rambus DRAM) Most of the memory alternatives so far have been variations of the same basic architecture. Rambus, Inc. (joint developers of EDRAM) has created a new memory architecture called the Rambus Channel. A CPU or specialized IC is used as the master device and the RDRAMs are used as slave devices. Data is then sent back and forth across the Rambus channel in 256-byte blocks. With a dual 250MHz clock, the Rambus Channel can transfer data based on the timing of both clocksthis results in data-transfer rates approaching 500MB/s (roughly equivalent to 2-ns access time). The problem with RDRAM is that a Rambus Channel would require an extensive re-design to the current PC memory architecturea move that most PC makers strenuously resist. As a result, you are most likely to see RDRAM in high-end,
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specialized computing systems. Still, as memory struggles to match the microprocessor, PC makers might yet embrace the Rambus approach for commercial systems. s WRAM (Windows RAM) Samsung Electronics has recently introduced WRAM as a new video-specific memory device. WRAM uses multiple-bit arrays connected with an extensive internal bus and high-speed registers that can transfer data almost continuously. Other specialized registers support attributes, such as foreground color, background color, write-block control bits, and true-byte masking. Samsung claims data-transfer rates of up to 640MB/sabout 50% faster than VRAMyet WRAM devices are cheaper than their VRAM counterparts. It is likely that WRAM will receive some serious consideration in the next few years.
MEMORY TECHNIQUES
Rather than incur the added expense of specialized memory devices, PC makers often use inexpensive, well-established memory types in unique architectures designed to make the most of low-end memory. The three most-popular architectures are: paged memory, interleaved memory, and memory caching.
Paged memory This approach basically divides system RAM into small groups (or
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pages) from 512 bytes to several KB long. Memory-management circuitry on the motherboard allows subsequent memory accesses on the same page to be accomplished with zero wait states. If the subsequent access occurs outside of the current page, one or more wait states might be added while the new page is found. This is identical in principle to fast-page mode DRAM. You will find page-mode architectures implemented on high-end i286, PS/2 (model 70 and 80), and many i386 systems.
Interleaved memory This technique provides better performance than paged mem-
ory. Simply put, interleaved memory combines two banks of memory into one. The first portion is even, while the second portion is oddso memory contents are alternated between these two areas. This allows a memory access in the second portion to begin before the memory access in the first portion has finished. In effect, interleaving can double memory performance. The problem with interleaving is that you must provide twice the amount of memory as matched pairs. Most PCs that use interleaving will allow you to add memory one bank at a time, but interleaving will be disabled and system performance will suffer.
Memory caching This is perhaps the most recognized form of memory-enhancement
architecture (Fig. 23-5). Cache is a small amount (anywhere from 8KB to 1MB) of very fast SRAM, which forms an interface between the CPU and ordinary DRAM. The SRAM typically operates on the order of 5 to 15 ns, which is fast enough to keep pace with a CPU using zero wait states. A cache-controller IC on the motherboard keeps track of frequently accessed memory locations (as well as predicted memory locations), and copies those contents into cache. When a CPU reads from memory, it checks the cache first. If the needed contents are present in cache (called a cache hit), the data is read at zero wait states. If the needed contents are not present in the cache (known as a cache miss), the data must be read directly from DRAM at a penalty of one or more wait states. A small quantity of very fast
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Main system RAM CPU Tag RAM Cache logic Cache RAM
FIGURE 23-5
Major cache system components.
cache (called Tag RAM) acts as an index, recording the various locations of data stored in cache. A well-designed caching system can achieve a hit ratio of 95% or morein other words, memory can run without wait states 95% of the time. Two levels of cache are in the contemporary PC. CPUs from the i486 onward have a small internal cache (known as L1 cache) and external cache (SRAM installed as DIPs or COAST modules on the motherboard) is referred to as L2 cache. The i386 CPUs have no internal cache (although IBMs 386SLC offered 8KB of L1 cache). Most i486 CPUs provide an 8KB internal cache. Early Pentium processors were fitted with two 8KB internal cachesone for data and one for instructions. Todays Pentium II Slot 1 CPU incorporates 256 to 512KB of L2 cache into the processor cartridge itself.
Shadow memory ROM devices (whether the BIOS ROM on your motherboard or a
ROM IC on an expansion board) are frustratingly slow with access times often exceeding several hundred nanoseconds. ROM access then requires a large number of wait states, which slow down the systems performance. This problem is compounded because the routines stored in BIOS (especially the video BIOS ROM on the video board) are some of the most frequently accessed memory in your computer. Beginning with the i386-class computers, some designs used a memory technique called shadowing. ROM contents are loaded into an area of fast RAM during system initialization, then the computer maps the fast RAM into memory locations used by the ROM devices. Whenever ROM routines must be accessed during run time, information is taken from the shadowed ROM instead of the actual ROM IC. The ROM performance can be improved by at least 300%. Shadow memory is also useful for ROM devices that do not use the full available data bus width. For example, a 16-bit computer system might hold an expansion board that contains an 8-bit ROM IC. The system would have to access the ROM not once, but twice, to extract a single 16-bit word. If the computer is a 32-bit machine, that 8-bit ROM would have to be addressed four times to make a complete 32-bit word. You might imagine the hideous system delays that can be encountered. Loading the ROM to shadow memory in advance virtually eliminates such delays. Shadowing can usually be turned on or off through the systems CMOS Setup routines.
THE ISSUE OF PARITY
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The Issue of Parity

As you might imagine, it is vital that data and program instructions remain error-free. Even one incorrect bit because of electrical noise or a component failure can crash the PC, corrupt drive information, cause video problems, or result in a myriad of other faults. PC designers approached the issue of memory integrity by using a technique known as parity (the same technique used to check serial data integrity).
THE PARITY PRINCIPLE

The basic idea behind parity is simpleeach byte written to memory is checked, and a 9th bit is added to the byte as a checking (or parity) bit. When a memory address is later read by the CPU, memory-checking circuitry on the motherboard will calculate the expected parity bit and compare it to the bit actually read from memory. In this fashion, the PC can continuously diagnose system memory by checking the integrity of its data. If the read parity bit matches the expected parity bit, the data (and, indirectly, the RAM) is assumed to be valid, and the CPU can go on its way. If the read and expected parity bits do not match, the system registers an error and halts. Every byte is given a parity bit, so for a 32-bit PC, there will be 4 parity bits for every address. A 64bit PC, has 8 parity bits, etc.
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EVEN VS. ODD

The two types of parity are even and odd. With even parity, the parity bit is set to 0 if an even number of 1s are already in the corresponding byte (keeping the number of 1s even). If an even number of 1s is not in the byte, the even parity bit will be 1 (making the number of 1s even). With odd parity, the parity bit is set to 0 if an odd number of 1s is already in the corresponding byte (keeping the number of 1s odd). If an odd number of 1s is not in the byte, the odd parity bit will be 1 (making the number of 1s odd). Although even and odd parity work opposite of one another, both schemes serve exactly the same purpose and have the same probability of catching a bad bit. The memory device itself does not care at all about what type of parity is being usedit just needs to have the parity bits available. The use of parity (and the choice of even or odd) is left up to the motherboards memory-control circuit.
THE PROBLEMS WITH PARITY

Although parity has proven to be a simple and cost-effective means of continuously checking memory, there are two significant limitations. First, although parity can detect an error, it cannot correct the error because there is no way to tell which bit has gone bad. This is why a system simply halts when a parity error is detected. Second, parity is unable to detect multi-bit errors. For example, if a 1 accidentally becomes a 0 and a 0 accidentally becomes a 1 within the same byte, parity conditions will still be satisfied. Fortunately, the probability of a multi-bit error in the same byte is extremely remote.
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CIRCUMVENTING PARITY
Over the last few years, parity has come under fire from PC makers and memory manufacturers alike. Opponents claim that the rate of parity errors because of hardware (RAM) faults is very small and that the expense of providing parity bits in a memory-hungry marketplace just isnt justified anymore. There is some truth to this argument, considering that the parity technique is more than 15 years old and has serious limitations. As a consequence, a few motherboard makers have begun removing parity support from their low-end motherboards, and others are providing motherboards that will function with or without parity (usually set in CMOS or with a motherboard jumper). Similarly, some memory makers are now providing non-parity and fake parity memory as cheaper alternatives to conventional parity memory. Non-parity memory simply foregoes the 9th bit. For example, a non-parity SIMM would be designated 8 or 32 (i.e., 4M 8 or 4M 32). If the SIMM supports parity, it will be designated 9 or 36 (i.e., 4M 9 or 4M 36). Fake parity is a bit more deviousthe 9th bit is replaced by a simple (and dirt cheap) parity-generator chip that looks like a normal DRAM IC. When a read cycle occurs, the parity chip on the SIMM provides the proper parity bit to the motherboard all the time. In effect, your memory is lying to the motherboard. Although there is a cost savings, your memory is left with no means of error checking at all. Its a little like driving a car without a speedometeryou could go for miles without a problem, but sooner or later youll cross a speed trap. You can go indefinitely without parity, but when an error does occur, having parity in place can save you immeasurable frustration. Unless the lowest cost is your absolute highest priority, it is recommended that you spend the extra few dollars for parity RAM.
Most motherboards can be operated with non-parity RAM. It is also usually possible to mix parity and non-parity memory in the same system. In either case, you will need to disable all parity-checking features for the RAM.
ABUSE AND DETECTION OF FAKE MEMORY

Another potential problem with fake parity memory is fraud. There have already been reported instances where memory was purchased as parity at full priceonly to find that the parity ICs were actually parity generators. This was determined by dissecting the IC packages and finding that the IC die in the parity position did not match the IC dies in the other bit positions. The buyer doesnt know because parity generators are packaged to look just like DRAM ICs, and there is no other obvious way to tell, just by looking at the SIMM or other memory device. System diagnostic software also cannot detect the presence of parity memory vs. fake memory. There are really only two ways to protect yourself from fake memory fraud. First, industry experts indicate that many fake-parity ICs (the parity generators) are marked with designations such as BP, VT, GSM, or MPEC. If you find that 1 out of every 9 ICs on your SIMM carries such a designation (or any other designation not matching the first 8), you might have a fraud situation. Of course, the first step in all justice is a benefit of the doubt, so contact the organization you purchased the memory fromthey might simply have sent the wrong SIMMs.
MEMORY INSTALLATIONS AND OPTIONS
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Second, you can check the IC dies themselves. Unfortunately, this requires that you to carefully dissect several IC packages on the SIMM and compare the IC dies under a microscope resulting in the destruction of the memory device(s). If the 9th die looks radically different (usually much simpler) than the other 8, youve likely got fake parity. A non-destructive way to check the SIMM is to use a SIMM checker (if you have access to one) with a testing routine specially written to test parity memory. If the SIMM works, but the parity IC test fails (i.e., the tester cannot write to the parity memory), chances are youve got fake parity. If you determine that you have been sold fake parity memory in place of real parity memory and you cannot get any satisfaction from the seller, you are encouraged to contact the Attorney General in the sellers state, and convey your information to them. After all, if youre being stiffed, chances are a lot of other people are tooand they probably dont even know it.
ALTERNATIVE ERROR CORRECTION

Although this book supports the use of parity, it is also quick to recognize its old age. In the world of personal computing, parity is an ancient technique. Frankly, it could easily be replaced by more sophisticated techniques, such as Error-Correction Code (ECC) or ECC on SIMM (EOS). ECC (which is already being used in high-end PCs and file servers) uses a mathematical process in conjunction with the motherboards memory controller, and appends a number of ECC bits to the data bits. When data is read back from memory, the ECC memory controller checks the ECC data read back as well. ECC has two important advantages over parity. It can actually correct single-bit errors on-the-fly without the user ever knowing theres been a problem. In addition, ECC can successfully detect 2-bit, 3-bit, and 4-bit errors, which makes it an incredibly powerful errordetection tool. If a rare multi-bit error is detected, ECC is unable to correct it, but it will be reported and the system will halt. It takes 7 or 8 bits at each address to successfully implement ECC. For a 32-bit system, you will need to use 39 or 40 SIMMs (i.e., 8M 39 or 8M 40). These are relatively new designations, so you should at least recognize them as ECC SIMMs if you encounter them. As an alternative, some 64-bit systems use two 36-bit SIMMs for a total of 72 bits 64 bits for data and 8 bits (which would otherwise be for parity) for ECC information. EOS is a relatively new (and rather expensive) technology that places ECC functions on the memory module itself, but it provides ECC results as parity. While the memory module runs ECC, the motherboard continues to see parity. This is an interesting experiment, but it is unlikely that EOS will gain significant market share. Systems that use parity can be fitted with parity memory much more cheaply than EOS memory.
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Memory Installation and Options

Installing memory is not nearly as easy as it used to be. Certainly, todays memory modules just plug right in, but deciding which memory to buy, how much (or how little) to buy, and how to use existing memory in new systems, presents technicians with a bewildering variety of choices. This part of the chapter illustrates the important ideas behind choosing and using memory.
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GETTING THE RIGHT AMOUNT

How much memory do I need? This age-old question has plagued the PC industry ever since the 80286 CPU broke the 1MB memory barrier. With more memory, additional programs and data can be run by the CPU at any given timewhich indirectly helps to improve the productivity of the particular PC. The problem is cost. Typical DRAM is running around $15/MB (U.S.)compared to about $0.50/MB (U.S.) for hard-drive space. The goal of good system configuration is to install enough memory to support the PCs routine tasks. Installing too much memory means that youve spent money for PC resources that just remain idle. Installing too little memory results in programs that will not run (typical under DOS) or poor system performance because of extensive swap-file use (typical under Windows). So how much memory is enough? The fact of the matter is that enough is an ever-changing figure. DOS systems of the early 1980s (8088/8086) worked just fine with 1MB. By the mid-1980s (80286), DOS systems with 2MB were adequate. Into the late 1980s (80386), Windows 3.0 and 3.1 needed 4MB. As the 1990s got underway (80486), Windows systems with 8MB were common (even DOS applications were using 4 to 6MB). Today, with Pentium systems and Windows 95, 16MB is considered to be a minimum requirement, and 32MB systems are readily available. For today, this is the benchmark that you should use for general-purpose home and office systems. But by the end of the decade, 48 to 64MB systems will probably be the norm. And this is not to say that 32MB systems are the pinnacle of performance. Todays file servers and industrial-strength design packages are using 64MB to 128MB of RAMmotherboard chipsets can often support up to 512MB of RAM or more.
FILLING BANKS
Another point of confusion is the idea of a memory bank. Most memory devices are installed in sets (or banks). The amount of memory in the bank can vary, depending on how much you wish to add, but there must always be enough data bits in the bank to fill each bit position. Table 23-11 illustrates a relationship between data bits and banks for the range of typical CPUs. For example, the 8086 is a 16-bit microprocessor (two bytes). This means that two extra bits are required for parity, providing a total of 18 bits. Thus, one bank is 18 bits wide. You might fill the bank by adding eighteen 1-bit DIPs or two 30-pin SIMMs. As another example, an 80486DX is a 32-bit CPU, so 36 bits are needed to fill a
TABLE 23-11 CPUS VS. MEMORY BANK SIZE DATA WIDTH (W/PARITY) 9 bits 18 bits 18 bits 18 bits 36 bits 18 bits 36 bits 64 bits XMB BY 1 DIPS 9 18 30-PIN SIMMS 1 2 2 2 4 2 4 8 72-PIN SIMMS 1 (2 banks) 1 (2 banks) 1 1 (2 banks) 1 2
CPU 8088 8086 80286 80386SX, SL, SLC 80386DX 80486SLC, SLC2 80486DX, SX, DX2, DX4 Pentium
MEMORY INSTALLATION AND OPTIONS
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bank (32 bits plus 4 parity bits). If you use 30-pin SIMMs, you will need four to fill a bank. If you use 72-pin SIMMs, only one is needed. Notice that the size of the memory in MB does not really matter, so long as the entire bank is filled.
BANK REQUIREMENTS
There is more to filling a memory bank than just installing the right number of bits. Memory amount, memory matching, and bank order are three additional considerations. First, you must use the proper memory amount that will bring you to the expected volume of total memory. Suppose a Pentium system has 8MB already installed in Bank 0, and you need to put another 8MB into the system in Bank 1. Table 23-11 shows that two 72-pin SIMMs are needed to fill a bank, but each SIMM need only be 1M. Remember that a 1M 36-bit (with parity) device is 4MB. Because two such SIMMs are needed to fill a bank, the total would be 8MB. When added to the 8MB already in the system, the total would be 16MB. How about another example? Suppose that the same 8MB is already installed in your Pentium system and you want to add 16MB to Bank 1, rather than 8MB (bringing the total system memory to 24MB). In that case, you could use two 2M 72-pin SIMMs, where 2M 36 is 8MB (with parity) per SIMM. Two 8MB SIMMs yield 16MB, bringing the system total to (16MB + 8MB) = 24MB. Now for a curve. Suppose you want to outfit that Pentium as a network server with 128MB of RAM. Remember that 8MB is already in Bank 0, which means that only Bank 1 is available. Because the largest commercially available SIMMs are 8M 36 (32MB with parity), you can only add up to 64MB to Bank 1 (for a system total of 72MB. To get around this, you should remove the existing 1M 36 SIMMs in Bank 0, and fill both Bank 0 and Bank 1 with 8M 36 SIMMs, which would put 64MB in Bank 0, and 64MB in Bank 1yielding 128MB in total. You can review many of the recommended SIMM/DIMM combinations for a typical Pentium motherboard in Table 23-12.
TABLE 23-12 MEMORY COMBINATIONS FOR A TYPICAL MOTHERBOARD MEMORY SIZE 8MB 8MB 16MB 16MB 16MB 16MB 24MB 24MB 24MB 32MB 32MB 32MB 32MB 32MB
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SIMM 1 1M 32 2M 32 1M 32 1M 32 1M 32 4M 32 2M 32 1M 32
SIMM 2 1M 32 2M 32 1M 32 1M 32 1M 32 4M 32 2M 32 1M 32
SIMM 3 1M 32 2M 32 1M 32 2M 32 1M 32
SIMM 4 1M 32 2M 32 1M 32 2M 32 1M 32
SIMM 5 1M 32 2M 32
SIMM 6 1Mx32 2Mx32
DIMM 1 1M 64 2M 64 1M 64 1M 64 4M 64 2M 64
DIMM 2 1M 64 2M 64 2M 64
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TABLE 23-12 MEMORY COMBINATIONS FOR A TYPICAL MOTHERBOARD (CONTINUED) MEMORY SIZE 40MB 40MB 48MB 48MB 48MB 48MB 64MB 64MB 64MB 64MB 64MB 72MB 72MB 80MB 80MB 80MB 96MB 96MB 96MB 96MB 128MB 128MB 128MB 128MB 136MB 144MB 144MB 160MB 160MB 192MB 192MB 192MB 256MB 256MB 256MB 256MB SIMM 1 1M 32 2M 32 1M 32 2M 32 8M 32 4M 32 2M 32 1M 32 2M 32 1M 32 4M 32 2M 32 4M 32 16M 32 8M 32 4M 32 1M 32 2M 32 1M 32 4M 32 2M 32 8M 32 4M 32 8M 32 32M 32 16M 32 8M 32 SIMM 2 1M 32 2M 32 1M 32 2M 32 8M 32 4M 32 2M 32 1M 32 2M 32 1M 32 4M 32 2M 32 4M 32 16M 32 8M 32 4M 32 1M 32 2M 32 1M 32 4M 32 2M 32 8M 32 4M 32 8M 32 32M 32 16M 32 8M 32 SIMM 3 4M 32 4M 32 1M 32 2M 32 4M 32 2M 32 8M 32 8M 32 1M 32 8M 32 2M 32 4M 32 8M 32 4M 32 16M 32 16M 32 1M 32 16M 32 2M 32 16M 32 4M 32 8M 32 16M 32 8M 32 SIMM 4 4M 32 4M 32 1M 32 2M 32 4M 32 2M 32 8M 32 8M 32 1M 32 8M 32 2M 32 4M 32 8M 32 4M 32 16M 32 16M 32 1M 32 16M 32 2M 32 16M 32 4M 32 8M 32 16M 32 8M 32 SIMM 5 4M 32 2M 32 4M 32 8M 32 8M 32 4M 32 8M 32 16M 32 16M 32 16M 32 8M 32 16M 32 SIMM 6 4M 32 2M 32 4Mx32 8M 32 8M 32 4M 32 8Mx32 16M 32 16M 32 16M 32 8M 32 16M 32 DIMM 1 DIMM 2
1M 64 4M 64 2M 64 4M 64 8M 64 4M 64 4M 64 1M 64 8M 64 2M 64 8M 64 4M 64 8M 64 8M 64 8M 64 16M 64 16M x 64
Another bank requirement demands memory matchingusing SIMMs of the same size and speed within a bank. For example, when adding multiple SIMMs to a bank, each SIMM must be rated for the same access speed and share the same memory configuration (i.e., 2M 36). Finally, you must follow the bank order. For example, fill Bank 0 first, then Bank 1, then Bank 2, etc. Otherwise, memory will not be contiguous within the PC and CMOS will not recognize the additional RAM.
RECYCLING OLDER MEMORY DEVICES
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Recycling Older Memory Devices

Given the relatively high cost of PC memory, it is only natural that users and technicians alike would choose to re-use memory as much as possible when systems are upgraded or replaced. It is a simple matter to re-use memoryjust as you would re-use hard drives or video boards. But consider some special issues before you make plans to transfer memory from one system to another.
MEMORY SPEED
The goal of memory is to keep pace with the microprocessor using a minimum of wait states. It is possible to place a 100-ns SIMM in a Pentium system, but the wait states required to allow this awful mis-match would negate any benefits from the advanced microprocessor. As a consequence, it is most effective to use memory that is fast enough to handle the CPU in the system that will be receiving the memory. Table 23-10 shows typical memory speeds for various microprocessors. It is possible to use memory if the speed is faster than the minimum requirement, but all the memory in the bank should be the same speed. Ordinarily, there is no reason to buy memory that is faster than necessaryno additional benefit is realized by the system. The only time it might be advisable to invest in faster memory is if you know in advance that the memory will eventually be transferred to another system.
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MEMORY TYPE
You should also be sure to use the same type of memory (i.e., EDO, FPM, SDRAM, etc.). For example, if your motherboard is designed to use EDO RAM, and you have EDO RAM already installed, you should be sure to install more EDO RAM. Some motherboard designs allow you to mix memory types, but mixing memory types on other (especially older) motherboards might cause the system to malfunction.
SIMM STACKERS
Although your memory type should be able to fit into the new computer, there are ways to make it fit. One of the most popular memory adapters is the SIMM stacker. The devices are known by a variety of trade names, but all allow you to convert four 30-pin SIMMs into a 72-pin SIMM frame. However, with SIMM Stackers have two drawbacks:
s Cramped quarters SIMM adapter products require serious amounts of space. Re-
member that the adapter snaps into the SIMM socket and SIMMs attach to the adapter. As a result, the filled SIMM adapter looks a bit like a tree with branches. This is rarely a problem when SIMM sockets are placed side-to-side, but with several banks close together, multiple SIMM sockets might interfere with one another. s Timing penalty Timing is everything for memory, and with signals traveling on the order of nanoseconds, the very length of a printed signal run can adversely impact system performance. Generally speaking, you can expect access times to be increased by 10 ns or so when using a SIMM adapter. This is not a problem when the memory is measurably faster than needed. But if your memory speed is on the border, a SIMM adapter might necessitate an additional wait state.
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MIXING COMPOSITE AND NON-COMPOSITE SIMMS

Most ordinary 30-pin SIMMs use nine ICs (eight for data and one for parity). From time to time, you might encounter SIMMs with just a few ICs (usually three). The composite SIMM (with nine ICs) is olderusing less-dense memory. The non-composite SIMM (with three or so ICs) generally uses newer memory devices. In theory, it should be possible to mix composite and non-composite SIMMs together in the same bank or in the same system. However, system problems have been reported when this happens. As a rule, you can try mixing these two generations of memory, but if you encounter memory problems with the system later on, remove either memory type and see if the problem goes away.
REMOUNTING AND REBUILDING MEMORY

Memory recycling has taken another more unexpected turnsome small companies are actually taking older memory devices and re-mounting them on SIMMs and other memory structures. In this way, you can use DIPs that are re-mounted on a SIMM. For example, a company called Autotime (http://www.autotime.com) in Portland, OR will remove memory devices from one SIMM and install them on a SIMM that you need (i.e., remove the ICs from four 1MB 30-pin SIMMs and install and test them on one 4MB 72-pin SIMM).
Memory Troubleshooting
Unfortunately, even the best memory devices fail from time to time. An accidental static discharge during installation, incorrect installation, a poor system configuration, operating system problems, and even outright failures because of old age or poor manufacture can cause memory problems. This part of the chapter looks at some of the troubles that plague memory devices, and offers advise on how to deal with them.
A selection of tools are on the Companion CD, which can aid you in testing and troubleshooting PC memory. Check out CACHECHK.ZIP for cache testing, MEMSCAN.ZIP and RAMMAP.ZIP for general testing, and SHADTEST.ZIP for shadow RAM-performance testing.
MEMORY TEST EQUIPMENT

If you are working in a repair-shop environment or plan to be testing a substantial number of memory devices, you should consider acquiring some specialized test equipment. A memory tester, such as the SIMCHECK from Innoventions, Inc. (Fig. 23-6), is a modular microprocessor-based system that can perform a thorough, comprehensive test of various SIMMs and indicate the specific IC that has failed (if any). The system can be configured to work with specific SIMMs by installing an appropriate adapter module (Fig. 23-7). Intelligent testers work automatically, and show the progress and results of their examinations on a multi-line LCD Guesswork is totally eliminated from memory testing. Single ICs, such as DIPs and SIPs, can be tested using a single-chip plug-in module. The static RAM checker (Fig. 23-8) is another test bed for checking high-performance static RAM components in a DIP package. Both Innoventions test devices work together to provide a full-featured test system. Specialized tools can be an added expensebut no more
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FIGURE 23-6
The SIMCHECK main unit.

Innoventions, Inc.
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FIGURE 23-7
The SIMCHECK PS/2 SIMM adapter.

Innoventions, Inc.
FIGURE 23-8
The SIMCHECK static RAM unit.
Innoventions, Inc.
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so than an oscilloscope or other piece of useful test equipment. The return on your investment is less time wasted in the repair and fewer parts to replace.
REPAIRING SIMM SOCKETS

If there is one weak link in the architecture of a SIMM, it is the socket that connects it to the motherboard. Ideally, the SIMM should sit comfortably in the SIMM socket, then gently snap backheld in place by two clips on either side of the socket. In actuality, you really have to push that SIMM to get it into place. Taking it out again is just as tricky. As a result, it is not uncommon for a SIMM socket to break and render your extra memory unusable. The best (textbook) solution is to remove the SIMM socket and install a new one. Clearly, this tactic has some problems. First, removing the old socket will require you to remove the motherboard, desolder the broken socket, then solder in a new socket (which you can buy from a full-feature electronics store, such as DigiKey). In the hands of a skilled technician with the right tools, this is not so hard. But the printed circuit runs of a computer motherboard are extremely delicate, and the slightest amount of excess heat can easily destroy the sensitive, multi-layer connections. Fortunately, there are some tricks that might help you. If either of the SIMM clips have bent or broken, you can usually use a medium-weight rubber band that is about 1 shorter than the SIMM. Wrap the rubber band around the SIMM and socket, and the rubber band should do a fair job holding the SIMM in place. If any part of the socket should crack or break, it can be repaired (or at least reinforced) with a good-quality epoxy. If you choose to use epoxy, be sure to work in a ventilated area and allow plenty of time for the epoxy to dry.
CONTACT CORROSION
Heres one to tuck away for future reference. Corrosion can occur on SIMM contacts if the SIMM contact metal is not the same as the socketthis will eventually cause contact (and memory) problems. As a rule, check that the metal on the socket contact is the same as the SIMM contacts (usually tin or gold). You might be able get around the problem in the short term by cleaning corrosion off the contacts manually using a cotton swab and good electronics-grade contact cleaner. In the mean time, if you discover that your memory and connectors have dissimilar metals, you might be able to get the memory seller to exchange the SIMMs.
PARITY ERRORS
Parity errors constitute many of the memory faults that you will see as a technician. As you saw earlier in this chapter, parity is an important part of a computers self-checking capability. Errors in memory will cause the system to haltrather than continue blindly along with a potentially catastrophic error. But not just faulty memory that causes parity errors. Parity can also be influenced by your systems configuration. Here are the major causes of parity problems:
s s s s
One or more memory bits is intermittent or has failed entirely. Poor connections between the SIMM and socket. Too few wait states entered in BIOS (memory is too slow for the CPU). An intermittent failure or other fault has occurred in the power supply.
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s A bug, computer virus, or other rogue software is operating. s A fault has occurred in the memory-controller IC or BIOS.
When you are faced with a parity error after an upgrade, you should suspect a problem with wait states, so check that first. If the wait states are correct, systematically remove each SIMM, clean the contacts, and re-seat each SIMM. If the errors continue, try removing one bank of SIMMs at a time (chances are that the memory is bad). You might have to relocate memory so that Bank 0 remains filled. When the error disappears, the memory you removed is likely defective. If parity errors occur spontaneously (with no apparent cause), you should clean and reinstall each SIMM first to eliminate the possibility of bad contacts. Next, check the power-supply outputslow or noisy outputs might allow random bit errors. You might have to upgrade the supply if it is overloaded. Try booting the system clean from a write-protected floppy disk to eliminate the possibility of buggy software or computer viruses. If the problem persists, suspect a memory defect.
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TROUBLESHOOTING CLASSIC XT MEMORY

It seems only fitting to start an examination of memory problems with a brief overview of the original IBM PC/XT computer. In the good old days of personal computing, when only one or two commercial computers were on the market, there were few memory arrangements. POST could be written very specifically, and errors could be correlated directly to memory IC location. The POST routine in an XTs BIOS ROM is designed to identify the exact bank and bit where a memory error is detected, and display that information on the computers monitor. IBM PC/XT computers classify a memory (RAM) failure as error code 201. In actual operation, a RAM error would appear as XXYY 201, where XX is the bank, and YY is the bit where the fault is detected. As a result, it was often a simple matter to locate and replace a defective RAM IC. An XT is built with four RAM bankseach with nine bits (parity plus eight bits). Table 23-13 shows some bank and bit error codes for XTTABLE 23-13 INDEX OF IBM PC/XT ERROR CODES XXYY 201: MEMORY FAILURE BANK YY BIT 0 1 2 3 00 01 02 04 08 10 20 40 80 Parity bit D0 D1 D2 D3 D4 D5 D6 D7
XX 00 04 08 0C
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class computers. As an example, suppose that an XT system displayed 0002 201. This would indicate a memory failure in bank 0 at data bit D1. You need only replace the DIP memory IC residing at that location.
Symptom 23-1. You see a 1055 201 or 2055 201 error message Both
of these error codes indicate a problem with the systems DIP switch settings. Remember that XTs do not use CMOS RAM to contain a system setup configuration, so DIP switches are used to tell the system how much memory should be present. If memory is added or removed, the appropriate switches in switch bank 2 (bits 1 to 8) and switch bank 1 (bits 3 and 4) must be set properly. Turn off the computer, check your switch settings and reboot the computer.
Symptom 23-2. You see a PARITY CHECK 1 error message This error typ-
ically suggests a power-supply problemRAM ICs are not receiving the proper voltage levels, so their contents are being lost or corrupted. When this happens, parity errors will be produced. Remove all power from the computer, and repair or replace the power supply.
Symptom 23-3. You see a XXYY 201 error message This is a general RAM
failure format for XT computers, which indicates the bank and bit where the fault is located. XX is the faulty bank, and YY is the faulty bit. See Table 23-13 to decipher the specific bank and bit in an XT. For example, an error code of 0004 201 indicates a memory fault in bank 0 (00) and bit D2 (04). Replace the defective IC or bank of ICs.
Symptom 23-4. You see a PARITY ERROR 1 error message Multiple ad-
dresses or multiple data bits are detected as faulty in the XT. In some cases, one or more ICs might be loose or inserted incorrectly in their sockets. Remove power from the system and reseat all RAM ICs. If all RAM ICs are inserted correctly, rotate a new DRAM IC through each occupied IC location until the defective IC is located.
TROUBLESHOOTING CLASSIC AT MEMORY

Like the XT, IBMs PC/AT was the leader of the 80286 generation. Because there was only one model (at the time), ATs use some specific error messages to pinpoint memory (RAM or ROM) problems on the motherboard, as well as in its standard memory-expansion devices. The 200 series error codes represent system memory errors (Table 23-14). ATs present memory failures in the format: AAXXXX YYYY 20x. The 10-digit code can be broken down to indicate the specific system bank and IC number, although the particular bit failure is not indicated. The first two digits (AA) represent the defective bank, and the last four digits (YYYY) show the defective IC number. It is then a matter of finding and replacing the faulty DIP IC. Table 23-15 shows a set of error codes for early AT-class computers. For example, suppose that an IBM PC/AT displayed the error message: 05xxxxxx 0001 201 (we dont care about the xs). That message would place the error in IC 0 of bank 1 on the ATs system memory.
TROUBLESHOOTING CONTEMPORARY MEMORY ERRORS

Since the introduction of 286-class computers, the competition among motherboard manufacturers, as well as the rapid advances in memory technology, has resulted in a tremendous
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TABLE 23-14 200-SERIES ERROR CODES 201 202 203 204 205 207 210 211 212 213 215 216 221 225 230 231 235 241 251 Memory error (physical location will likely be displayed) Memory address line 015 error Memory address line 1623 error; line 1631 error (MCA) Memory remapped to compensate for error (PS/2) Error in first 128K (PS/2 ISA) of RAM BIOS ROM failure System-board memory-parity error Error in first 64K of RAM (MCA) Watchdog timer error DMA bus-arbitration time out Memory address error; 64K on daughter/SIP 2 failed (70) Memory address error; 64K on daughter/SIP 1 failed (70) ROM to RAM copy (shadowing) failed (MCA) Wrong speed memory on system board (MCA) Memory on motherboard and adapter board overlaps Non-contiguous adapter memory installed Stuck data line on memory module Memory module 2 failed Memory module 3 failed
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TABLE 23-15 CLASSIC AT ERROR CODES AAXXXXYYYY 20X: MEMORY FAILURE AA BOARD 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 YYYY 0000 0001 0002 0004 Motherboard Motherboard 128KB memory expansion 1st 512KB memory adapter 1st 512KB memory adapter 2nd 512KB memory adapter 2nd 512KB memory adapter 3rd 512KB memory adapter 3rd 512KB memory adapter 4th 512KB memory adapter 4th 512KB memory adapter 5th 512KB memory adapter 5th 512KB memory adapter FAILED IC Parity IC 0 1 2 YYYY 0100 0200 0400 0800 FAILED IC 8 9 10 11
BANK 0 1 n/a 0 1 0 1 0 1 0 1 0 1
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TABLE 23-15 CLASSIC AT ERROR CODES YYYY 0004 0008 0010 0020 0040 0080 FAILED IC 2 3 4 5 6 7 YYYY 0800 1000 2000 4000 8000 FAILED IC 11 12 13 14 15
amount of diversity in the design and layout of memory systems. Although the basic concepts of memory operation remain unchanged, every one of the hundreds of computer models manufactured today use slightly different memory arrangements. Todays PCs also hold much more RAM than XT and early AT systems. As a consequence of this trend, specific numerical (bank and bit) error codes have longsince been rendered impractical in newer systems, where megabytes can be stored in just a few ICs. The i386, i486, and todays Pentium/Pentium II computers use a series of generic error codes. The address of a fault is always presented, but no attempt is made to correlate the faults address to a physical IC. Fortunately, todays memory systems are so small and modular that trial-and-error isolation can often be performed rapidly. Lets look at some typical errors.
Symptom 23-5. The number 164 is displayed on the monitor This is a generic memory-size errorthe amount of memory found during the POST does not match the amount of memory listed in the systems CMOS setup. Run the CMOS setup routine and be sure that the listed memory amount matches the actual memory amount. If memory has been added or removed from the system, you will have to adjust the figure in the CMOS setup to reflect that configuration change. If CMOS setup parameters do not remain in the system after power is removed, try replacing the battery or CMOS/RTC IC. The latest CMOS setup routines do not list the amount of RAMit is detected automatically. However, you might simply have to enter the CMOS setup, then immediately save changes and exit to recalibrate the amount of detected RAM. Symptom 23-6. You see an Incorrect Memory Size error message This message might be displayed if the CMOS system setup is incorrect, or if there is an actual memory failure that is not caught with a numerical 200-series code. Check your CMOS setup, as described in Symptom 23-5 and correct it, if necessary. If the error persists, there is probably a failure in some portion of RAM. Without a numerical code, it can be difficult to find the exact problem location, so adopt a divide-and-conquer strategy. Remove all expansion memory from the system, alter the CMOS setup to reflect base memory (system board) only, and retest the system. If the problem disappears, the fault is in some portion of expansion memory. If the problem still persists, you know the trouble is likely in your base (system board) memory. Take a
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known-good SIMM or DIMM and systematically swap devices until you locate the defective device. If you have access to a memory tester, the process will be much faster. If you successfully isolate the problem to a memory expansion board (often found in older proprietary PCs), you can adopt the same strategy for the board(s). Return one board at a time to the system (and update the CMOS setup to keep track of available memory). When the error message reappears, you will have found the defective board. Use a knowngood RAM IC, SIMM, or DIMM, and begin a systematic swapping process until you have found the defective memory device.
Symptom 23-7. You see a ROM Error message displayed on the monitor
To guarantee the integrity of system ROM, a checksum error test is performed as part of the POST. If this error occurs, one or more ROM locations might be faulty. Your only alternative here is to replace the system BIOS ROM(s) and retest the system.
Symptom 23-8. New memory is installed, but the system refuses to recognize it New memory installation has always presented some unique problems because
2
different generations of PC deal with new memory differently. The oldest PCs require you to set jumpers or DIP switches for the computer to recognize new blocks of memory. The vintage i286 and i386 systems (i.e., a PS/2) use a setup diskette to tell CMOS about the PCs configuration (including new memory). More recent i386 and i486 systems incorporate an installed memory setting into a CMOS setup utility in BIOS. Late-model i486 and Pentium systems actually auto-detect installed memory each time the system is booted (so it need not be entered in the CMOS setup). Also check that an correct bank has been filled properly. The PC might not recognize any additional memory, unless an entire bank has been filled and the bank is next in order (i.e., Bank 0, then Bank 1, etc.). You might wish to check the PCs user manual for any unique rules or limitations in the particular motherboard.
Some late-model Pentium/Pentium II motherboards do not need banks filled in order, although thats usually the safest policy to follow when upgrading or troubleshooting any PC. Symptom 23-9. New memory has been installed or replaced, and the system refuses to boot When faced with complete boot failures, always start by check-
ing ac power, the system power switch, and power connections to the motherboard. Also see that all expansion boards are inserted evenly and completely in their expansion slots (flexing the motherboard during memory installation might have pried one or more boards out of their slots). Your memory modules might not be inserted correctly. Take the modules out and seat them again, making sure the locking arm is holding the module securely in place. If the problem continues, you probably do not have the right memory module for that particular computer. Be sure that the memory module (SIMM or DIMM) is compatible with your PC. Finally, check for any particular device order that might be required by the motherboard. Certain systems require that memory be installed in pairs or in descending order by size.
Symptom 23-10. You see an XXXX Optional ROM Bad, Checksum = YYYY error message Part of the POST sequence checks for the presence of any
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other ROMs in the system. When another ROM is located, a checksum test is performed to check its integrity. This error message indicates that the external ROM (such as a SCSI adapter or Video BIOS) has checked bad or its address conflicts with another device in the system. In either case, system initialization cannot continue. If you have just installed a new peripheral device when this error occurs (i.e., a SCSI controller board), try changing the devices ROM address jumpers to resolve the conflict. If the problem remains, remove the peripheral boardthe fault should disappear. Try the board on another PC. If the problem continues on another PC, the adapter (or its ROM) might be defective. If this error has occurred spontaneously, remove one peripheral board at a time and retest the system until you isolate the faulty board, then replace the faulty board (or just replace its ROM if possible).
Symptom 23-11. You see a general RAM error with fault addresses listed In actuality, the error message might appear as any of the following examples,
depending on the specific fault, where the fault was detected, and the BIOS version reporting the error:
s s s s s s s
Memory address line failure at XXXX, read YYYY, expecting ZZZZ Memory data line failure at XXXX, read YYYY, expecting ZZZZ Memory high address failure at XXXX, read YYYY, expecting ZZZZ Memory logic failure at XXXX, read YYYY, expecting ZZZZ Memory odd/even logic failure at XXXX, read YYYY, expecting ZZZZ Memory parity failure at XXXX, read YYYY, expecting ZZZZ Memory read/write failure at XXXX, read YYYY, expecting ZZZZ
Each of these errors are general RAM error messages indicating a problem in base or extended/expanded RAM. The code XXXX is the failure segment addressan offset address might be included. The word YYYY is what was read back from the address, and ZZZZ is the word that was expected. The difference between these read and expected words is what precipitated the error. In general, these errors indicate that at least one base RAM IC (if you have RAM soldered to the motherboard) or at least one SIMM/DIMM has failed. A trial-and-error approach is usually the least expensive route in finding the problem. First, re-seat each SIMM or DIMM and retest the system to be sure that each SIMM/DIMM is inserted and secured properly. Rotate a known-good SIMM/DIMM through each occupied SIMM/DIMM socket in sequence. If the error disappears when the known-good SIMM or DIMM is in a slot, the old device that had been displaced is probably the faulty one. You can go on to use specialized SIMM troubleshooting equipment to identify the defective IC, but such equipment is rather expensive unless you intend to repair a large volume of SIMMs/DIMMs to the IC level. If the problem remains unchangedeven though every SIMM has been checked, the error is probably in the motherboard RAM or RAM support circuitry. Run a thorough system diagnostic, if possible, and check for failures in other areas of the motherboard that affect memory (such as the interrupt controller, cache controller, DMA controller, or memory-management chips). If the problem prohibits a software diagnostic, use a POST board and try identifying any hexadecimal error code. If a support IC is identified, you can replace the defective IC or replace the motherboard outright. If RAM continues to be the
801
problem, try replacing the motherboard RAM (or replace the entire motherboard), and retest the system.
Symptom 23-12. You see a Cache Memory FailureDisabling Cache error The cache system has failed. The tag RAM, cache logic, or cache memory on your
motherboard is defective. Your best course is to replace the cache RAM IC(s) or COAST (Cache-on-a-Stick) module. If the problem persists, try replacing the cache logic or tag RAM (or replace the entire motherboard). You will probably need a schematic diagram or a detailed block diagram of your system in order to locate the cache memory IC(s).
Symptom 23-13. You see a Decreasing Available Memory error message This is basically a confirmation message that indicates a failure has been detected
in extended or expanded memory, and that all memory after the failure has been disabled to allow the system to continue operating (although at a substantially reduced level). Your first step should be to re-seat each SIMM/DIMM and ensure that they are properly inserted and secured. Next, take a known-good SIMM or DIMM and step through each occupied SIMM/DIMM slot until the problem disappearsthe device that had been removed is probably the faulty one. Keep in mind that you might have to alter the systems CMOS setup parameters as you move memory around the machine (an incorrect setup can cause problems during system initialization).
Symptom 23-14. You are encountering a memory error with HIMEM.SYS under DOS In many cases, this is a compatibility problem with system memory. For ex-
2
ample, the Intel Advanced/AS motherboard is incompatible with two specific Texas Instruments EDO SIMMs (part numbers TM124FBK32S-60 and TM248GBK32S-60). Other EDO SIMMs from TI and other vendors will not cause this error. Try a SIMM from a different manufacturer. Also be sure that youre using the latest version of HIMEM.SYS.
Symptom 23-15. Memory devices from various vendors refuse to work together The system experiences a Memory failure during the memory count at start
time. This is a very machine-specific problem. For example, Gateway Solo PCs can suffer this problem when customers use the same-size memory modules (4MB, 8MB, or 16MB) made from different vendors. Try matching the memory modules from the same manufacturer (including part number and speed).
Symptom 23-16. Windows 95 Protection errors occur after adding SIMMs/DIMMs Windows 95 stalls with Windows Protection Errors during boot or
randomly crashes with Fatal Exception Errors when opening applications. This is a known problem with the Intel Thor motherboard using the 1.00.01.CNOT BIOS after installing 32MB of RAM. This issue is usually caused by certain third-party SIMMs operating at speeds faster or slower than 60 ns. The motherboard probably has tight memory specifications, and SIMMs that operate at correct speed are required (not faster or slowereven though the SIMMs are marked properly). Some SIMM manufacturers mark the SIMMs at 60 ns, but the SIMMs actually run at 45 ns. Try some SIMMs from a different manufacturer. It is also possible that a BIOS upgrade might loosen timing enough to make the SIMMs usable.
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Further Study
Thats it for Chapter 23. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take a look at some of these memory resources: Autotime: http://www.autotime.com Cameleon Technology: http://www.camusa.com/ CST, Inc: http://www.simmtester.com/ Innoventions: http://www.simcheck.com/ Jaguar Marketing Group: http://www2.inow.com/~degeorge/jaguar.htm Kingston: http://www.kingston.com PNY: http://www.pny.com Simmsaver Technology, Inc.: http://www.simmsaver.com/

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23

Memory Package Styles and Structures

Memory Installation and Options

Recycling Older Memory Devices

The Issue of Parity

ESSENTIAL MEMORY CONCEPTS

Memory is a cornerstone of the modern PC.

Essential Memory Concepts

Address row select Address Address buffer

Storage cell array

Address column select

Cell I/O circuitry

CS Control circuit R/W

MEMORY PACKAGE STYLES AND STRUCTURES

Memory Package Styles and Structures

ADD-ON MEMORY DEVICES

Comparison of SIMMs and DIMMs.

MEMORY PACKAGE STYLES AND STRUCTURES

MEGABYTES AND MEMORY LAYOUT

MEMORY PACKAGE STYLES AND STRUCTURES

ACCESSTIME: (PRESENCE DETECT LINES)

MEMORY PACKAGE STYLES AND STRUCTURES

MEMORY PACKAGE STYLES AND STRUCTURES

MEMORY PACKAGE STYLES AND STRUCTURES

MEMORY PACKAGE STYLES AND STRUCTURES

MEMORY PACKAGE STYLES AND STRUCTURES

MEMORY PACKAGE STYLES AND STRUCTURES

1MB 64MB 32MB 16MB 8MB 4MB 2MB 1MB

256 36 16 32 8 32 4 32 2 32 1 32 512 32 256 32

1024Kb System ROM

IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15

00412 00413 00415 00416 00417

00419 0041A 0041C 0041E 0043E

0044A 0044C 0044E 00450 00460 00462 00463

00466 00467 0046B 0046C 00470 00471 00472

00475 00476 00477 00478 0047C 00480 00482

0048C 0048D 0048E 0048F 00490 00491

00494 00495 00496

00498 0049A 0049C 0049E 004A0

004A1 004A2 004A3 004A4

UPPER MEMORY AREA (UMA)

MEMORY SPEED AND WAIT STATES

DETERMINING MEMORY SPEED

PRESENCE DETECT (PD)

UNDERSTANDING MEMORY REFRESH

Size (ECC pinout)

Speed (parity/ECC pinout)

GND = Jumper installed N/C = No jumper installed

Major cache system components.

THE ISSUE OF PARITY

The Issue of Parity

THE PARITY PRINCIPLE

EVEN VS. ODD

THE PROBLEMS WITH PARITY

ABUSE AND DETECTION OF FAKE MEMORY

MEMORY INSTALLATIONS AND OPTIONS

ALTERNATIVE ERROR CORRECTION

Memory Installation and Options

GETTING THE RIGHT AMOUNT

MEMORY INSTALLATION AND OPTIONS

SIMM 6 1Mx32 2Mx32

RECYCLING OLDER MEMORY DEVICES

Recycling Older Memory Devices