Experiment no: 8 FOUR BIT MULTIPLIER Aim:

Date: 6.1.2012

To design and simulate four bit multiplier using Modelsim SE version 6.0 and to implement the design in Xilinx XC3S400 FPGA kit.

Logic Diagram:

4 bit multiplier Truth Table: A 0000 0010 0111 1110 1111 SKCET/ECE/VLSI LAB/09bb019 B 0000 1001 0100 1111 1111 P 00000000 00010010 00011100 11010010 11100001 Page 56

PROGRAM: --4 bit multiplier using structural modelling library ieee; use ieee.std_logic_1164.all; entity mul_4 is port(A:in std_logic_vector(3 downto 0); B:in std_logic_vector(3 downto 0); P:out std_logic_vector(7 downto 0)); end entity; architecture ar_mul_4 of mul_4 is component andg is port(a,b: in std_logic; c:out std_logic); end component; component halfadd_df is port(a,b:in std_logic; sum1,carry1:out std_logic); end component; component fulladd_d is port(A,B,C:in std_logic; sum,carry:out std_logic);

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end component; signal s: std_logic_vector(14 downto 0); signal su: std_logic_vector(7 downto 2); signal c: std_logic_vector(12 downto 2); begin A1:andg port map(A(0),B(0),P(0)); A2:andg port map(A(0),B(1),s(0)); A3:andg port map(A(1),B(0),s(1)); A4:andg port map(A(0),B(2),s(2)); A5:andg port map(A(1),B(1),s(3)); A6:andg port map(A(2),B(0),s(4)); A7:andg port map(A(0),B(3),s(5)); A8:andg port map(A(1),B(2),s(6)); A9:andg port map(A(2),B(1),s(7)); A10:andg port map(A(3),B(0),s(8)); A11:andg port map(A(1),B(3),s(9)); A12:andg port map(A(2),B(2),s(10)); A13:andg port map(A(3),B(1),s(11)); A14:andg port map(A(2),B(3),s(12)); A15:andg port map(A(3),B(2),s(13)); A16:andg port map(A(3),B(3),s(14)); H1:halfadd_df port map(s(0),s(1),P(1),c(2)); SKCET/ECE/VLSI LAB/09bb019 Page 57

H2:halfadd_df port map(su(2),c(2),P(2),c(12)); H3:halfadd_df port map(su(3),su(4),P(3),c(6)); H4:halfadd_df port map(su(6),c(6),P(4),c(9)); F1:fulladd_d port map(s(2),s(3),s(4),su(2),c(3)); F2:fulladd_d port map(c(3),s(5),s(6),su(3),c(4)); F3:fulladd_d port map(s(7),s(8),c(12),su(4),c(5)); F4:fulladd_d port map(c(4),s(10),s(9),su(5),c(7)); F5:fulladd_d port map(s(11),c(5),su(5),su(6),c(8)); F6:fulladd_d port map(c(7),s(12),s(13),su(7),c(10)); F7:fulladd_d port map(c(8),c(9),su(7),P(5),c(11)); F8:fulladd_d port map(c(10),c(11),s(14),P(6),p(7)); end ar_mul_4;

THEORY: Four Bit Multiplier: SKCET/ECE/VLSI LAB/09bb019 Page 56

A Binary multiplier is an electronic hardware device used in digital electronics or a computer or other electronic device to perform rapid multiplication of two numbers in binary representation. It is built using binary adders. The rules for binary multiplication can be stated as follows 1. If the multiplier digit is a 1, the multiplicand is simply copied down and represents the product. 2. If the multiplier digit is a 0 the product is also 0. For designing a multiplier circuit we should have circuitry to provide or do the following three things: 1. it should be capable identifying whether a bit is 0 or 1. 2. It should be capable of shifting left partial products. 3. It should be able to add all the partial products to give the products as sum of partial products. 4. It should examine the sign bits. If they are alike, the sign of the product will be a positive, if the sign bits are opposite product will be negative. The sign bit of the product stored with above criteria should be displayed along with the product. From the above discussion we observe that it is not necessary to wait until all the partial products have been formed before summing them. In fact the addition of partial product can be carried out as soon as the partial product is formed.

OUTPUT: Four Bit Multiplier:

SKCET/ECE/VLSI LAB/09bb019

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SKCET/ECE/VLSI LAB/09bb019

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RESULT: Thus Four Bit Multiplier is designed and simulated using Modelsim SE version 6.0 and implemented in Xilinx XC3S400 FPGA kit.

SKCET/ECE/VLSI LAB/09bb019

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