Overview of the AMBA specification

AMBA classification
Advanced High-performance Bus (AHB)
AHB is for high-performance, high clock frequency system modules.

Advanced System Bus (ASB)

ASB is for high-performance system modules.

Advanced Peripheral Bus (APB)

APB is for low-power peripherals.

AMBA Protocol: Actors

Master: Instigates transactions (16 max) Slave: Responds to transactions Arbiter: Manages bus access according to a designerdefined an arbitration scheme (round robin, TDMA, etc.) Decoder: Activates the slave that corresponds to the current address Bridge: Links busses with different protocols.

A typical AMBA-based microcontroller

AMBA Bus Protocol: Summary

ASB : Rapid, strongly supported but uses latches and tri-state busses that make the design more difficult to test. AHB : Rapid, recent, structured, testable but complex. Replaces ASB. APB : Simple to implement, but less flexible. Used for simple peripherals.

AMBA signals
AHB:
Data
HADDR[31:0] (Master -> Slave/Decoder) HWDATA[31:0] (Master -> Slave) HRDATA[31:0] (Slave -> Master)

Global control
HCLK (clock source -> Master) HRESETn (Reset Controller -> Master)

Control
HWRITE (Master -> Slave) HTRANS[1:0] (Master -> Slave)

AMBA signals
AHB:
Control
HBURST[1:0] (Master -> Slave) HPROT[3:0] (Master -> Slave)
Can be neglected for now.

HREADY (Slave -> Master) HRESP[1:0] (Slave -> Master) HSELx (Decoder -> Slave)

Multi slave control

HBUSREQx (Master -> Arbiter) HLOCKx (Master -> Arbiter) HGRANTx (Arbiter -> Master)

AMBA signals
Arbitration Signals
Control
HBUSREQx (Master -> Arbiter) HLOCKx (Master -> Arbiter) HGRANTx (Arbiter -> Master) HMASTER[3:0] (Arbiter -> Slave) HMASTERLOCK (Arbiter -> Slave) HSPLITx[1:0] (Slave -> Arbiter)

AMBA signals
APB:
Data
PADDR[31:0] (Bridge -> Slave) PWDATA (Bridge -> Slave)
Can up to 32 bit wide

PRDATA (Slave -> Bridge)

Can up to 32 bit wide

Control
PCLK (Bridge -> Slave) PRESTn (Bridge -> Slave) PWRITE (Bridge -> Slave) PENABLE (Bridge -> Slave) PSELx (Bridge -> Slave)

AMBA AHB

AMBA AHB
burst transfers split transactions single cycle bus master handover single clock edge operation non-tristate implementation wider data bus configurations (64/128 bits).

AHB interconnection

Bus master drives the address and control Arbiter selects one of the masters

Bus operation (1/2)

A granted bus master starts an AHB transfer by driving address and control signals: WRAP4
address direction width burst forms
0x10 Incrementing 0x14 burst: not wrap at address 0x18 boundaries 0x1c Wrapping burst: 0x20 wrap at particular 0x24 address INCR4 boundaries Address wrap in 4-word boundary

Bus operation (2/2)

During a transfer the slave shows the status using the response signals HRESP[1:0]
OKAY: transfer progressing normally when
HREADY is HIGH, transfer has completed successfully

ERROR: transfer error RETRY and SPLIT: transfer cant complete immediately, but the bus master should continue to attempt the transfer

Address decoding
A central address decoder provides HSELx for each slave Minimum address space that can be allocated to a single slave is 1K Byte

AHB bus master

Initiate read and write by providing an address and control interface Processor, DMA, DSP test interface

AHB bus slave

Respond to a read or write operation within a given address-space range Back to the master the success, failure or waiting

AHB arbiter

Basic transfer
An AHB transfer consists of two distinct sections:
Master action

Slave action

Transfer with wait state

Multiple Transfer

Pipelined Burst Transfers

The pipelining of memory accesses allows for a higher transfer rate, at the cost of an initial latency. For certain types of memory, the first access in a burst requires several cycles, and subsequent accesses take only one. AMBA uses a pipelined memory model.

Pipelined Burst Transfers : Address phase

During the address phase:
The master places the address and the other control signals on the bus The decoder selects the appropriate slave At the next rising edge of the clock, the slave stores the address and control signals The data phase begins

Pipelined Burst Transfers: Address phase (continued)

The address phase can be stretched if:
The bus is not immediately granted to the master (HGRANT = 0) The preceding data phase is not yet complete (HREADY = 0)

Pipelined Burst Transfers: Data phase

During the data phase:
The slave reacts to the access, according to the stored control signals. A slow slave can request several cycles by setting HREADY = 0. When HREADY = 1, the access is complete. If the access is a read, the master captures the data at that moment.

Transfer Type
Type
IDEL HTRANS[1:0]

Descripton
Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer should be ignored by the slave. Masters cannot take next transfer place immediately during a burst transfer Indicates the first transfer of a burst or a single transfer The remaining transfers in a burst are SEQUENTIAL.

00

BUSY NONSEQ SEQ

01 10 11

Burst Operation(1/2)
Type
SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WAP16 INCR16 HBURST[2:0] 000 001 010 011 100 101 110 111

Descripton Single Transfer Incrementing burst of unspecified length 4-beat wrapping burst 4-beat incrementing burst 8-beat wrapping burst 8-beat incrementing burst 16-beat wrapping burst 16-beat incrementing burst

Burst Operation(1/2)
Four-beat wrapping burst
WRAP4 0x30 0x34 0x38 0x3c 0x40 0x44

Burst operation (2/2)

Undefined Burst Length

Transfer Type Example

Slave transfer responses(1/2)

Slave transfer responses(2/2)

HREADY HRESP[1:0] Response 00 OKAY 01 ERROR 10 RETRY 11 SPLIT Two-cycle response ERROR & RETRY & SPLIT To complete current transfer, master can take following action

Two-cycle response

Split transfers
1. If the slave decides that it may take a large number of cycles to obtain the data, it returns a SPLIT response (instead of OK) to the arbiter and memorizes HMASTER 2. The arbiter grants the use of the bus to another master that requests it 3. When the slave is ready to complete the transfer, it asserts the appropriate bit of the HSPLITx (between 0 and 16) bus to the arbiter 4. The arbiter observes the HSPLITx signals every cycle. It will allow the master to complete the transfer if no higher priority master is using the bus 5. When the transfer eventually takes place the slave finishes with an OKAY transfer response

Split transfers

Narrow slave on a wider bus

Replicate the data onto both halves of the wide bus (as shown in the diagram above)

Wide slave on a narrow bus

multiplexing the input bus replication of the output bus.

Granting Bus Access

Handover After Burst

AMBA ASB

AMBA Bus Protocol: ASB

Advantages
ASB is supported by a very large number of common ARM processors and microcontrollers (ARM7TDMI, ARM940T, ARM9TDMI Relatively simple to implement Burst transfers supported

Disadvantages
Single, tri-state data bus Latch-based instead of register-based design Uses both clock edges Split transfers not supported

AMBA APB

AMBA APB
Low power Latched address and control Simple interface Suitable for many peripherals

APB specification
The APB specification is described under the following headings: State diagram Write transfer Read transfer

State diagram

Write transfer
SETUP ENABLE

1 0

1 1

Read transfer
SETUP ENABLE

1 0

1 1

APB bridge
Interface diagram

APB bridge description

Decodes the address and generates a peripheral select, PSELx. Only one select signal can be active during a transfer. Drives the data onto the APB for a write transfer. Drives the APB data onto the system bus for a read transfer. Generates a timing strobe, PENABLE, for the transfer.

APB slave
Interface diagram

APB slave description

For a write transfer, the data can be latched at the following points: on either rising edge of PCLK, when PSEL is HIGH on the rising edge of PENABLE, when PSEL is HIGH. For read transfers the data can be driven on to the data bus when PWRITE is LOW and both PSELx and PENABLE are HIGH.

Interfacing APB to AHB

Interfacing the AMBA APB to the AHB is described as follows: Read transfers
Write transfers Back to back transfers Tri-state data bus implementations .

Interfacing APB to AHB

Write transfer

Interfacing APB to AHB

Read transfer

Burst of Read Transfer

Burst of Write Transfer

Back to back transfers

Tristate data bus implementations

APB Test bench

APB Master BFM APB Slave DUT

Monitir

EXAMPLE(1/3)
APB write transfer
task w_setup; input [(addr_size-1):0] addr; input [(data_size-1):0] data; begin paddr<=addr; pwrite<=1'b1; psel<=1'b1; penable<=1'b0; pwdata<=data; @(posedge clk); end endtask

task enable; begin psel<=1'b1; penable<=1'b1; @(posedge clk); psel<=1'b0; penable<=1'b0; end endtask

task w_transfer; input [(addr_size-1):0] addr; input [(data_size-1):0] data; begin w_setup(addr, data); enable; end endtask

EXAMPLE(2/3)
APB read transfer
task r_setup; input [(addr_size-1):0] addr; input [(data_size-1):0] data; begin paddr<=addr; pwrite<=1'b0; psel<=1'b1; penable<=1'b0; @(posedge clk); prdata<=data; end endtask

task enable; begin psel<=1'b1; penable<=1'b1; @(posedge clk); psel<=1'b0; penable<=1'b0; end endtask

task r_transfer; input [(addr_size-1):0] addr; input [(data_size-1):0] data; begin r_setup(addr, data); enable; end endtask

EXAMPLE(3/3)
Function Task
task test1; integer i; begin reset_wf; for (i=1;i<=num_regs;i=i+1) begin write_transfer(i,i); end for (i=1;i<=num_regs;i=i+1) begin read_transfer(i,i); end end endtask

different hierarchy levels of test1

AHB Test bench

AHB Master BFM

AHB Slave DUT

Monitir

BFM

DUT

EXAMPLE(1/3)
Test bench for BRIDGE

EXAMPLE(2/3)
AHB to APB write transfer
task ahb_apb_write; input [31:0] address; input [31:0] wdata; output [1:0] response; begin //cycle 1 write_addr(address); response = #1 HRESP; //cycle 2 write_data(wdata); response = #1 HRESP; //cycle 3 idel; response = #1 HRESP; //cycle4 idel; response = #1 HRESP; end endtask

EXAMPLE(3/3)
AHB to APB read transfer
task ahb_apb_read; input [31:0] address; input [31:0] rdata; output [1:0] response; begin //cycle 1 read_addr(address); response = #1 HRESP; //cycle 2 reade_data(rdata); response = #1 HRESP; //cycle 3 reade_data(rdata); response = #1 HRESP; end endtask

AHB/APB Bridge Design

AHB/APB bridge design in FPGA

Logic Module
HCLK HRESETn HTRANS[1:0] HWRITE HSIZE[1:0] HADDR[31:0] HDATA[31:0] HREADY HESP[1:0] HBUSREQ HLOCK HDRID[3:0] LED Switch

XCV2000E
AHB decoder

8
Push bottom

Register peripheral

AHB

18

OSC

Keypad controller AHB To APB Bridge LCD controller interface USB device controller Interrupt controller

keypad

160x160 LCD Panel USB device Transcever

2D FDCT/IDCT nLMINT

AHB decoder
Select peripheral Address = C100_0000 ~ C5FF_FFFF

assign iHSELAHBAPB = ((iHSELLOGICMODULE == 1'b1) & ((HADDR[27:24] >= 4'b0001) & (HADDR[27:24] <= 4'b0101))) ? 1'b1 : 1'b0; assign iHSELDCT = ((iHSELLOGICMODULE == 1'b1) & (HADDR[27:20] == 4'b0000)) ? 1'b1 : 1'b0; assign iHSELDefault

Select 2D DCT/IDCT

= ((iHSELLOGICMODULE == 1'b1) Address = C000_0000 ~ C0FF_FFFF & ~((HADDR[27:24] >= 4'b0001) & (HADDR[27:24] <= 4'b0101)) & ~(HADDR[27:20] == 4'b0000)) ? 1'b1 : 1'b0;
Logic Module
HCLK HRESETn HTRANS[1:0] HWRITE HSIZE[1:0] HADDR[31:0] HDATA[31:0] HREADY HESP[1:0] HBUSREQ HLOCK HDRID[3:0] LED Switch

Select error response Address = C600_0000 ~ CFFF_FFFF

XCV2000E
AHB decoder

8
Push bottom

Register peripheral

AHB

18

OSC

Keypad controller AHB To APB Bridge LCD controller interface USB device controller Interrupt controller

keypad

160x160 LCD Panel USB device Transcever

2D FDCT/IDCT nLMINT

Memory map of the Logic Module

160MB Logic module 3 Logic module 2 Logic module 1 Logic module 0 Core module Alias memory 16MB USB 16MB keypad

0xCFFF_FFFF

Bus error response 0xC600_0000 0xC5FF_FFFF 0xC500_0000 0xC4FF_FFFF 0xC400_0000

LCD Interrupt controller Logic Module Registers 2D FDCT/IDCT

0xF0000000 0xE0000000 0xD0000000 0xC0000000

0xC3FF_FFFF 0xC300_0000 0xC2FF_FFFF 0xC200_0000 0xC1FF_FFFF 0xC100_0000 0xC0FF_FFFF 0xC000_0000

16MB

16MB

PCI
16MB Core module/ Motherboard Memory and peripherals 16MB

Logic Module select

assign iHSELLOGICMODULE = ((((HDRID == 4'b1110) & (HADDR[31:28] == 4'b1100)) | ((HDRID == 4'b0111) & (HADDR[31:28] == 4'b1101)) | ((HDRID == 4'b1011) & (HADDR[31:28] == 4'b1110)) | ((HDRID == 4'b1101) & (HADDR[31:28] == 4'b1111))) & (HRESETn == 1'b1)) ? 1'b1 : 1'b0;

0xF0000000 0xE0000000 0xD0000000 0xC0000000

Logic module 3 Logic module 2 Logic module 1 Logic module 0

Peripheral Select
// constants for APB address decoding `define REGSBASE `define INTCBASE `define LCDBASE `define USBBASE `define KEYBASE 4'b0001 4'b0010 4'b0011 4'b0101 if (HAddrMux[27:24] == `USBBASE) PSELUSBint = 1'b1; if (HAddrMux[27:24] == `LCDBASE) PSELLCDint = 1'b1; if (HAddrMux[27:24] == `INTCBASE) PSELINTCint = 1'b1; if (HAddrMux[27:24] == `REGSBASE) PSELREGSint = 1'b1; if (HAddrMux[27:24] == `KEYBASE) 4'b0100 PSELKEYint = 1'b1;
keypad USB LCD Interrupt controller Logic Module Registers

0xC5FF_FFFF 0xC500_0000 0xC4FF_FFFF 0xC400_0000 0xC3FF_FFFF 0xC300_0000 0xC2FF_FFFF 0xC200_0000 0xC1FF_FFFF 0xC100_0000

FSM of the bridge

Valid == 1b1 HWRITE==1'b1 ApbEn = 1b1 iPENABLE = 1b1 Wr2RdReg==1'b1 Valid==1'b1 HWRITE==1'b1 WrBurstReg==1'b1 (RegValid == 1'b1) & (RegValidPrev == 1'b0) HWriteReg==1'b1 ApbEn = 1b1 PWDATAEn = 1b1 NextPWRITE = 1b1

APB to AHB read transfer

AHB to APB write transfer

Bus Wrapper & Interface Design

HW/SW communication with FIFO as the interface

Use two FIFOs to implement the interface data buffers
PSELx PENABLE WRITE PWDATA Tri_State Controller PADDR
32 32 Bus Partition Din 8 RD WR_ACK FULL WR FIFO_W
RD_ACK

Din[7:0] ND

EMPTY

RFD

FIFO_W_R Controller

RDY Dout[11:0]

Address Decoder PRDATA PRESETn PCLK

Interrupt
32

MemoryMapped FIFO Status Register

Bus Partition 12

FSM
EMPTY FULL RD WR

RST

AMBA APB

Interrupt Generation

CLK

Wrapper

Interface

FIFO_R

DCT

Memory Map for hardware modules

0 x C F F F _ FF F F
160M B Log ic m odule 3 Log ic m odule 2 Log ic m odule 1 Log ic m odule 0 Core m odu le Alias m em ory 16M B US B 16M B keyp ad

B us error response 0 x C 6 0 0 _ 00 0 0 0 x C 5 F F _ FF F F 0 x C 5 0 0 _ 00 0 0 0 x C 4 F F _ FF F F 0 x C 4 0 0 _ 00 0 0
LCD In terrup t con troller Log ic M od u le Reg isters 2D FD CT/ID CT

0 x F 0 0 0 0 00 0 0 x E 0 0 0 0 00 0 0 x D 0 0 0 0 00 0 0 x C 0 0 0 0 00 0

0 x C 3 F F _ FF F F 0 x C 3 0 0 _ 00 0 0 0 x C 2 F F _ FF F F 0 x C 2 0 0 _ 00 0 0 0 x C 1 F F _ FF F F 0 x C 1 0 0 _ 00 0 0 0 x C 0 F F _ FF F F 0 x C 0 0 0 _ 00 0 0

16M B

16M B

PCI
16M B Core m odu le/ M oth erb oard M em ory and periph erals 16M B

Address Decoding Range for Each Block in the Interface design

0xC000_0000~0xC04F_FFFF

0xC0A0_0000~0xC0FF_FFFF

0xC050_0000~0xC09F_FFFF