EFFICIENT IMPLEMENTATION OF KALMAN FILTER BASED

IMPEDANCE RELAYS
J. L. Pinto de S, Senior Member IEEE P. Flores, Student Member IEEE
Instituto Superior Tcnico, DEEC, Seco Energia, 1096 Lisboa Codex, Portugal.
ABSTRACT - Kalman filters as applied to distance re-
lays have usually been assumed to require too much com-
puting resources to be feasible.
In this paper a parallel implementation of a Kalman
filter based distance relay is reported, exhibiting a good
performance with no particular computing power re-
quirements.
The relay software is fully implemented with a High
Level Language over a multitasking real time environ-
ment. The underlying hardware is based on a number of
inexpensive 32 bit microcrocontrollers, inter-communi-
cating through efficient serial links.
A prototype is tested in laboratory, providing the
evaluation of processing burdens in relation with differ-
ent algorithm options.
1. INTRODUCTION
A few years ago the evolution of general-purpose
microprocessors reached the point in which built-in float-
ing-point coprocessors became the state of the art. This evo-
lution has been paralleled by that of microcrocontrollers, so
that 32 bit devices have been available in the market.
On the other hand, Kalman filters are the optimal recur-
sive filters for sophisticated noise models of electromagnetic
fault induced transients |1|. Although their superior perfor-
mance, regarding accuracy and speed, has been established
for sampling times near half a cycle and beyond [2], the fact
is that reported Kalman filter implementations have so far
required complex adaptive features, supported only by exotic
processors and Assembler based software.
In this paper a modular architecture for digital relays is
introduced in which the modules are similar to classic func-
tional relay elements, but are virtual in that they are software
objects instead of physical devices. This software architec-
ture is fully implemented in a High Level Language over a
multi tasking real time environment. The underlying hard-
ware is based on a variable number of 32 bit microcro-
controllers, inter-communicating through inexpensive serial
links.
Over the mentioned architecture a Very High Speed dis-
tance relay is implemented, without sacrificing any modular-
ity or High programming Level, applying Kalman filters.
The full architecture and algorithm implementation is re-
ported, as well as test data.
2. THE HARDWARE INFRASTRUCTURE
The underlying hardware of the developed architecture is
designed according to two fundamental criteria: maximum
chip integration and low cost expandability, both based on
easy to link microcontrollers. These architectures are quite
common in modern controllers, and there is at least a relay
manufacturer which has developed a similar basis for its
well-known protective relays.
As the core processing unity, 32-bit 68332 Motorola mi-
crocrocontrollers at 21 MHz were adopted, together with a
small addition of static RAM and EPROM. These units are
by now small modules with a few chips provided at a retail
cost of a few hundred $USD, a 19 x 6 inches board carrying
3 such modules. Anyway, because microcrocontrollers usu-
ally embody most hardware needed to interface other chips
(into "System Integration Modules"), these boards are rather
simple.
As the interconnection media, serial links with moderate
baud rates were adopted. Motorola microcrocontrollers have
two serial links per chip, a distinctive advantage for the sake
of this project. One of these links is synchronous and partic-
ularly suitable for chip interconnection (4 wires); the other
one is asynchronous. A feature of these microcrocontrollers
is that a lot of their serial links is automatically managed by
pre-programmed built-in devices, freeing the processors for
parallel work.
The 4-wires synchronous serial link (SSL) is quite insen-
sitive to EMI even working at a frequency of 4 MHz, which
is enough for the inter-communication needs of the system.
Since the SSL requires that one of the chips acts as a master
selecting the others to communicate, a polling based
management is a natural basis for a protocol. A simple sys-
tem can have a master and up to 15 slaves, which have not
necessarily to be identical microcrocontrollers chips.
Most peripherals of the developed architecture are smart,
being managed by 8 bit single-chip Motorola 68HC05 as
dedicated microcontrollers. These chips also include a SSL
interface that enables their connection to the serial bus of the
2
architecture, doing jobs such as analog-to-digital conversion
and man machine interface control. Figure 1 illustrates the
developed hardware architecture. Figures 2 and 3 illustrate
how the slave 68HC05 microcontrollers are employed to
manage the Analog-digital and Man-Machine Interface sub-
systems.
68332
(Main)
Master/Slave
68332
(K 1)
Slave
68HC705
(ADCM)
Master/Slave
68HC705
(MMIM)
Slave
MOSI
MISO
SCK
PCS0
PCS1
PCS2
PCS3
MOSI
MISO
SCK
PCS0
MOSI
MISO
SCK
SS
MOSI
MISO
SCK
SS

D
e
c
o
d
e
r

D
e
c
o
d
e
r
M
O
S
I
S
C
K
P
C
S
0
P
C
S
1
P
C
S
2
P
C
S
3
M
I
S
O

D
e
c
o
d
e
r
PORT A

Fig. 1: A parallel architecture based on the Synchronous
Serial Link (SSL)
3
MUX Buffer S&H
68HC705
(ADC)
ADC
2
12

Fig. 2: Analog Interface managed by a 68HC05
Another useful peripheral integrated into the MC 68332
is the TPU. It is a powerful Time programmable unit with 16
I/O pins, which are used to manage the binary I/O, a lot of
the processing being automatically done by built-in firm-
ware. Figure 4 illustrates how this peripheral is employed to
access binary Inputs and to control command and signaling
Output relays.

68HC705
(MMIM)
t 3
0.30000
1-8 9-19
20-24

Fig. 3: MMI module managed by another 68HC05

68332
T
P
U
0
2
15
I/O
I/O

Fig. 4: Binary inputs and outputs managed by the 68332
3. THE SOFTWARE INFRASTRUCTURE
3.1 - The multitasking environment
In a multitasking environment, a number of programs
(called tasks in real-time applications) run as if each one has
a processor. Of course, since there is only a real CPU, this is
shared by those programs according to priorities that take
into account their real time requirements for responsiveness.
However, when a program is suspended from the CPU, it has
no conscience of that (it sleeps). It is the multitasking ker-
nel that manages the access to the CPU, preempting a task
when this has to wait for some external or internal event, or
when another with a higher priority is awaken, in a transpa-
rent way for every task. Therefore, a multitasking environ-
ment provides a decoupage among tasks which is very con-
venient.
In order to preempt a task by another, the kernel has data
structures describing the tasks into which the CPU data of
the programs are saved to be reloaded later. The corres-
ponding operation by the kernel is called context switching,
and the time spent to do this is an overhead intrinsic to mul-
titasking environments. Since in digital relaying processing
time is a critical resource, it becomes clear that multitasking
is mostly a software modularity requirement.
A feature of the 68332 microcontroller is its compatibility
with the 32 bit 680x0 Motorola microprocessor family, for
3
which there is a lot of available software. An example of this
is the reuse of a kernel written by the first author a decade
ago for substations automation [3], which is now well de-
bugged.
The communication between tasks is handled by this ker-
nel through mailboxes and message passing services as in
some kernels available in the market; for a 68332 at 21
MHz, the overhead for executing such a service, including a
context switching, never exceeds 0,060 ms. Only the mes-
sages address is passed by the kernel, instead of the message
itself, which explains the achieved efficiency. These services
are requested by each task as if they were executed by the
machine hardware itself, and provide the "Send Message",
the "Wait for Message" and the non-blocking "Accept Mes-
sage" services on public mailboxes (as well as time-out ser-
vices).
The HLL employed in this project was the C language, to
which most young engineers have been taught nowadays. To
interface the C code to the multitasking kernel, very simple
Assembler routines were developed, but no change was made
in the C floating-point classical maths library. A good mas-
tering of C pointers is recommended to handle the message
data that deal with the input-output of the tasks, but coding
their inner body is straightforward.
3.2 - The SSL data management
The microcontroller managing the SSL has to share this
channel with the Analog Interface and the communication to
the other chips. However, since the sampling rate is usually
the main issue determining the inter-microcontroller
communication demands, the polling cycles can usually be
triggered after the acquisition of each sample set. This was
done in the developed architecture, each poll providing an
exchange of a pack of information between the manager and
the other microcontrollers. Each two high priority polling
cycles, a low-priority cycle is performed for non critical
software functions.
At a higher level, each microcontroller has a SSL han-
dling task with image mailboxes where the output messages
are queued until an information exchange occurs. In a ordi-
nary microcontroller, input messages are formatted and sent
to the destination tasks, while all the output messages are
sent to the manager. The manager, however, can input mes-
sages to output them again to other microcontrollers. To do
this it has to know the host chips of the destination tasks,
which have also to be known in the configuration stage of
the system.
With this protocol, each task has no necessity to know
whether another providing some work is running on the
same or on another chip. From its point of view, all other
tasks run on their own processors, be them real or virtual. It
is clear that this decoupage among software modules makes
their modification very easy, the only needed information on
the addressed tasks being their true or image mailboxes.
4. PROTECTION ALGORITHMS
In the developed implementation, fault type classifica-
tion, a decision that requires the availability of all possible
phasors, is not performed before the phasors estimation. It
has been shown that three pairs of phasors of currents and
voltages are enough to generate all the others required by
impedance computation. Furthermore, these pairs of phasors
can be estimated in true parallelism, as illustrated in Fig. 5.
QSPI
ISR1
QSPI
ISR2
PHASOR_O PHASOR_AB PHASOR_AC
IMPEDANCE
ZONE I
ZONE II ZONE III
QSPI
ISR3
AUTOMATION
TIMER II TIMER III
K 1 K 2 K 3 Main
uo, io
uab, iab
uac, iac
Uo, Io Uab, Iab Uac, Iac
Zfault Zfault Zfault
On/Off
On/Off
On/Off
Sign. Sign.

Fig. 5: Critical modules are computed in parallel
4.2 - Phasor estimation modules by DFT and Kalman fil-
ters
Although the required minimum number of pairs of pha-
sors to determine all the relations in a 3-phase system is
three, modal signals feature the separation of the aerial from
the ground voltages and currents in transmission lines, for
both the steady-state and the transient signals. This can be
exploited from an optimum filtering point of view [4]. In ad-
dition, modal signals can be derived from the phase signals
4
through transformations involving only elementary opera-
tions.
It can be shown that for transposed lines, a family of
equivalent modal transformations can be derived, such as the
Clarks or the Karrenbaeurs. Although these transforma-
tions are similar and easy to infer from each other, the 3
Karrenbaeurs pairs of signals are almost a direct sub-set of
the 6,5 pairs employed in the traditional full-scheme, and are
the simplest to implement:
Xab
Xac
Xo

(
(
(
=
1
3

1 1 0
1 0 1
1 1 1

(
(
(
Xa
Xb
Xc

(
(
(
(1)
The Analog to Digital smart module broadcasts the sam-
ples acquired to all the 68332 based modules, each of the
modal processors determining whether a discontinuity in any
currents is present (regarding a cycle before), in order to
trigger the Kalman filter, and isolating the corresponding
pair of samples for inner processing.
Next, the modal estimator task receives a message carry-
ing its pair of samples, and processes it to output an estimate
of the corresponding phasors. Two algorithms are available.
The first one is the recursive DFT (2), taken as the usually
running algorithm in steady-state conditions, while the other
is the Modal Kalman Filter (MKF+), for transient fast esti-
mation after fault inception (3) [5]. The latter can run for
only one cycle after fault inception, when fault-induced tran-
sients are most significant. The two sets of expressions for
DFT and Kalman filters are basically alike; for DFT:
Au = u
k
- u
k-n
;

Uc
k
= (2cos(e
0
kAt)/n) Au + Uc
k-1
;
Us
k
= (2sin(e
0
kAt)/n) Au + Us
k-1
;
Ai = i
k
- i
k-n
;
Ic
k
= (2cos(e
0
kAt)/n) Ai + Ic
k-1
;
Is
k
= (2sin(e
0
kAt)/n) Ai + Is
k-1. (2)
while, for kalman filters:
Au = u
k
- (huc(kAt) Uc
k-1
+ hus(kAt) Us
k-1
);
Uc
k
= Kuc(kAt) Au + Uc
k-1
;
Us
k
= Kus(kAt) Au + Us
k-1
;
Ai= i
k
-(hic(kAt) Ic
k-1
+his(kAt) Is
k-1
+hidc(kAt) Idc
k-1
);
Ic
k
= Kic(kAt) Ai + Ic
k-1
;
Is
k
= Kis(kAt) Ai + Is
k-1
;
Idc
k
= Kidc(kAt) Ai + Idc
k-1
; (3)
Since the DFT does not explicitly account for the decay-
ing dc component of the currents, it offers a limited capabil-
ity to filter it out in the absence of a mimic impedance; this
being another reason to not run it just after fault inception
for VHS operation. On the other hand, the calculation of the
residuals (Au and Ai) by Kalman filters can require a few
extra terms to account for the zero-state transients of the pre-
filters, due to their short cut-off [5]. However, those tran-
sients are significant only for 1/4 cycle, after which they can
be neglected.
Because a pre-defined sampling rate was not assumed,
the coefficients in (2,3) were not pre-defined as constant val-
ues, even though they are pre-computed and stored in mem-
ory after defining each sampling rate. This is also because
High Level Languages make the implementation tricks asso-
ciated to some sampling rates less valuable. As a result, ex-
pressions (2) and (3) for the DFT and MKF+ estimators be-
come similar from a computational point of view. It is worth
noting that besides easy programming and portability, HLL
can reduce the error resulting from truncation in recursive
algorithms, due to the floating-point routines (although in
the implemented code the DFT computation of Au and Ai
takes them as integers, speeding up that estimate). Equations
(2,3) have a straightforward translation in C code.
4.3 - Impedance measurement
No matter the way the modal phasors are estimated, two
fundamental types of expressions can be used for computing
line fault impedance: those based on the Symmetrical Com-
ponents from Phadke et al. [6], and the classic expressions
from Lewis and Tippet [7].
To map the modal phasors onto the Symmetrical compo-
nents is a simple transformation which was presented in [4].
To map the modal phasors onto the variables of the classic
impedance expressions is still simpler, the resulting expres-
sions having been first presented by Sachdev and Kolla [8]
(also restated in a Appendix).
To get a full picture of the involved HLL code and of the
corresponding processing burden for the two criteria, it has
to be pointed out that although both require a previous fault
classification based on the assessment of the phasors, their
estimation is independent of the distance computation in
both methods. This means that if a fault evolves, the esti-
mators have not to be switched from some signals to others,
thus loosing all the previously processed information. On the
other hand, it has been shown that from an accuracy point of
view both criteria are very similar [2]. The main steps to be
programmed in each criterion are summarized in Appen-
dices.
5. PERFORMANCE EVALUATIONS
Measuring the execution time of the most important intro-
duced modules with the "In circuit Emulator", we have for
the fundamental modules:
Table I - Computing times (C code in a 68332 at 21 MHz)
5
Modal recursive DFT for U and I: 0,44 ms;
Modal Kalman Filter + for U and I: 1,06 ms;
A complex division: 0,56 ms;
Symmetrical Components Z calculus for a LG fault: 3,36 ms;
Modal Z calculus for a LG fault: 2,08 ms;
Operating characteristics evaluation (polygonal): 0,32 ms.
In a High Speed relay, 1 or 1 1/2 cycles are satisfactory de-
cision times which are similar to what is performed by non
digital relays. With this in mind, it is worth noting that it
has been shown that a minimum of 4 samples per cycle is
sufficient to extract phasors, if suitable short cut-off prefil-
ters and DFT are employed [9]. Although such a sampling
rate carries an uncertainty of 1/8 cycle in the tripping
time, and it can be poor to filter out decaying dc compo-
nents, it demands a moderate processing power and has been
implemented in a few commercial products. In particular,
given the processing times of Table I, it is clear that a single
microcontroller with only virtual parallelism (multitasking)
is enough for High Speed distance relaying.
However, for VHS distance relaying in which a tripping
time around half a cycle is intended, the uncertainty associ-
ated to that sampling period has to be further reduced.
If the DFT is to be applied (in its half cycle version), and
the sampling rate is increased to 12 samples per cycle, it has
to be taken into account that a mimic impedance has to be
added and, to fully profit from its half cycle data window,
the cut-off of the prefilters has to be increased from the for-
mer 100 Hz of the 4 samples per cycle version, to 300 Hz, so
that their transient is limited to a sampling period. This re-
quirement does not apply to the MKF+ estimators. Because
of the increase in its sampling rate, VHS operation also re-
quires more computing, a configuration in which there is a
dedicated microcontroller to estimate a pair of modal pha-
sors allowing a natural exploitation of parallelism. However,
the impedance computation has still to wait for most results
of those estimators. The only possible parallelism regarding
impedance computation and the remaining modules is be-
tween fault classification (which works with the currents
only) and the estimation of the voltage phasors. Therefore,
for VHS operation the computational complexity of the
impedance expressions is the critical bottleneck, with an
advantage for Modal expressions also because a larger por-
tion of their code is just in fault classification.
Fig. 6 illustrates the time partition of a VHS configura-
tion, where the possible asynchronous behavior of the code is
also clear (particularly for impedance determination, which
can show a slipping delay regarding the availability of the
phasors, although it must be run only each twice estimates
update).
Considering the 7 to 10 observations milliseconds needed
by the estimation process (on a 20 ms cycle basis), and also
the time required by the output interface, such a relay can
safely trip a circuit-breaker in 1/2 to 3/4 cycles.
Sampling
Modal Kalman filter for U0, I0
Modal Kalman filter for Uab, Iab
Modal Kalman filter for Uac, Iac
0 1 2 3 ms
impedance computation

Figure 6 - VHS distance relaying with 4 microcontrollers (C source code and
multitasking) - time scheduling
6. CONCLUSIONS
A trivial architecture for Kalman filter based distance re-
lays was presented, based on full High Level Language pro-
gramming, a parallel environment with multiprocessing and
multitasking, and inexpensive hardware based on 32 bit mi-
crocontrollers.
Based on 3 parallel pairs of Kalman filters for modal va-
riables, it was shown that the remaining bottleneck for effi-
cient implementation is the impedance computation, for
which the classical expressions adapted to the Karrenbaeur
variables were shown to provide the best performance.
ACKNOWLEDGMENTS
This project was funded by JNICT, the Portuguese Na-
tional Council for Science and Technology, and supported by
INTERG - "Institute of Energy.
REFERENCES
[1] - J.L. Pinto de S, "Stochastic Analysis in the time do-
main of Very High Speed Distance Relaying, part I - The-
ory", IEE Proceedings - C, May 1994.
[2] - Ibiden, "Stochastic Analysis in the time domain of Very
High Speed Distance Relaying, part II - Illustrations", IEE
Proceedings - C, May 1994.
[3] - J.L. Pinto de S, J. Sucena Paiva, "A multi-tasking soft-
ware architecture to implement concurrent switching se-
quences designed with Petri Nets", IEEE Trans. on Power
De-livery, Vol. 6, n 3, pp. 1058-1064, July 1991.
[4] - J.L. Pinto de S, "Modal Kalman Filter based Imped-
ance relaying", IEEE Trans. on Power Delivery, Vol. 6, n 1,
pp. 78-84, January 1991.
[5] - Ibiden, "A new Kalman filter approach to digital relay-
ing", IEEE Trans. on Power Delivery, Vol. 8, n 3, pp. 1652-
1660, July 1992.
[6] - A.G. Phadke, M. Ibrahim, T. Hlibka, "Fundamental
6
Basis for Distance Relaying with Symmetrical Components",
IEEE Trans. on PAS, Vol. 96, n 2, pp. 635-646, March-
April 1977.
[7] - W.A. Lewis, L.S. Tippett, "Fundamental Basis for Dis-
tance Relaying on 3-Phase Systems", AIEE Trans., Vol. 66,
pp. 694-708, 1947.
[8] - M.S. Sachdev, S.R. Kolla, "A Polyphase digital dis-
tance relay", Spring Meeting of the Canadian Electrical As-
sociation, Vancouver, B.C., March 1987.
[9] - J. Carr, R.V. Jackson, "Frequency Domain Analysis
Applied to Digital Transmission Line Protection", IEEE
Trans. on PAS, Vol. 94, n 4, pp. 1157-1166, July-August
1975.
APPENDICES
I- Fault distance computation with Symmetrical Components
To map the modal onto the Symmetrical phasors, only
the aerial Xab and Xac have to be transformed, for example:
a=Xab
c
+Xac
c
; b=Xab
s
+Xac
s
; c= 3(Xab
c
-Xac
c
) ; d=
3 (Xab
s
-Xac
s
) ; X+
c
=a+d; X-
c
= a-d; X+
s
= b-c; X-
s
= b+c.
The fault type classification procedures that follow this
transformation are presented in [10], pp. 149. It is worth
noting that the computation of a complex impedance re-
quires a number of operations:
Z =
U
I
=
UcIc UsIs
I
+
2 + j
UcIs UsIc
I

2
with I
2
=

Ic
2
+ Is
2
.
Symmetrical Components based distance expressions can
require up to at least 3 such complex divisions for LG faults.
In addition, a burdensome computation arises regarding the
module of the complex quotient |I
0
/I
+
|, because it can re-
quire a square root (which takes 1 ms in the 68332 C float-
ing-point code).
[10] - A.G. Phadke, J.S. Thorp, "Computer Relaying for
Power Systems", Research Studies Press Ldt., 1988.
II- Fault distance computation with Modal Phasors
With the classic fault distance expressions, LL and LLG
faults require the related delta voltages and currents [7]. So,
with the transformation defined in (1), it is for:
phases a,b: Z =
Uab
Iab
; phases a,c: Z =
Uac
Iac
;
phases b,c: Z =
Uab Uac
Iab Iac

.
Any one of these expressions can be used for 3-phase faults.
For single LG faults, expressions of [7] become:
phase a: Z=
Uab Uac Uo
Iab Iac (Z0 / Z )Io
+ +
+ + +
;
phase b: Z=
-2Uab Uac Uo
-2Iab Iac (Z0/ Z )Io
+ +
+ + +
;
phase c : Z =
Uab Uac Uo
Iab Iac (Z0 / Z )Io
+
+ +
2
2
.
As with the original expressions of [7], only a complex
division is required for each fault. Furthermore, with the ex-
ception of I0, the numerator and the denominator of those
divisions only involve complex additions or subtractions of
the Karrenbaeur phasors. However, this approach needs the
complete identification of a fault, which can be done as fol-
lows:
- do Io
2
=
Ico
2
+

Iso
2
; if Io
2
< c
2
then the fault is without
ground, else the fault involves the ground. If the fault is
without ground, compute the square values of Iab, Iac and
Iab-Iac; the largest value identifies the expression to use. It
is to point out that this square value can be reused next to
perform the selected complex division.
If the fault involves the ground, compute I+ and either
determine the LG faulted phase as for the Symmetrical
Components method, or identify the fault as a LLG and pro-
ceed as for faults without ground.
BIOGRAPHIES
Jos Pinto de S was born and raised in Angola when that
country was still a Portuguese cologne. He got his 5-years
degree in Electrical Engineering (Power Option) in 1980,
and a Ph.D. in Electrical and Computers Engineering in
1988, both from Instituto Superior Tcnico (IST), Lisbon. In
between he was fully dedicated for 5 years to a cooperative
University-utility project for Substation Automation. He is
now an associate professor of IST, teaching both undergra-
duate and graduate courses. His present research interests
are the science and technology of Integrated Protection and
Control Systems.
P. Flores (1969) was born in Lisbon. He got his 5-years de-
gree in Electrical Engineering (Power Option) in 1993 from
IST, and is now working towards his Master degree. He has
implemented the reported project since 1991, at first as a
part-time job and later as his term project. He enjoys jog-
ging, climbing, and applying computers and maths to solve
Power System problems.