Dc-link Capacitor Voltage Balancing for a Five-level Diode-clamped Active Power Filter Using Redundant Vectors

H.-B. Zhang1 S.J. Finney1 J.E. Fletcher1 A.M. Massoud2 J. Yang1 B.W Williams1 1: The authors are with Department of Electronic and Electrical Engineering, Glasgow, UK

2: Texas A&M University at Qatar, Doha, Qatar

Abstract___This paper investigates the compensation and modulation processes of the five-level diode-clamped APF, compensating a three-phase rectified RL load by redundant vectors. From the analysis, a hybrid SVM algorithm allows capacitor voltage balancing. Simulation and experimental results validate the SVM algorithm. Keywords___ five-level diode-clamped active power filter, capacitor voltage balancing, SVM. I. INTRODUCTION output MULTILEVEL inverters synthesize an acsources, voltage from discrete or interconnected dc mostly capacitors, and produce higher quality waveforms with lower voltage stresses on power semiconductor switches. An N-level diode-clamped multilevel inverter has N-1 dc rail series connected capacitors. When applied in motor drives or back-to-back structured ac/dc/ac converters [8]-[11], the dc-link voltage of diode-clamped multilevel inverter is constant. The currents injected into any of the dc-link capacitor interconnections cause voltage variations of all the capacitors, and the capacitor voltages are balanced when the total energy of the capacitor bank achieves its constrained minimum [12]. Active power filters (APF) employing diode-clamped multilevel inverters usually do not have an external dc-link supply. As an APF sources the instantaneous power difference between the utility and the load, the total energy of the capacitor bank changes, resulting in capacitor voltage ripple. This capacitor voltage ripple increases the maximum voltage applied to the switches and capacitors, produces low frequency distortion in the ac output voltages, and is directly linked to the capacitor sizing and lifetime [13][14]. The APF dc-link capacitor voltages do not change unless they are involved in compensating vectors in one modulation cycle. Thus the dc-link capacitor voltage balancing strategies for a three-phase diode-clamped multilevel inverter with constant total dc-link voltage, may not be readily applied to APF structures without this constraint. Dc-link capacitor voltage balancing methods for three-level neutral-point clamped APFs have been extensively investigated [15]-[18], and capacitor voltage balancing is achieved with redundant three-level modulation space vectors, while dc-link capacitor voltage balancing algorithms for five-level diode-clamped APFs, as shown in Fig.1, are rarely reported.

Fig.1. Diode-clamped five-level shunt active power filter This paper considers five-level APF modulation to compensate nonlinear load currents. The APF compensation and modulation processes can be arranged such that, although during one line cycle the compensating reference voltage vectors reach the full modulation index area of five-level modulation plane, most vectors are within the low modulation index area. This characteristic enables a SVM algorithm to balance dc-link capacitor voltages, using only redundant space vectors. The proposed hybrid algorithm combines the usual five-level SVM and quasi three-level operation, where the redundant short vectors and optimal vector sequences in each modulation cycle are utilized. Simulation and experimental results demonstrate the validity of the proposed balancing algorithm. II. FIVE-LEVEL SVM AND APF MODULATION CHRACTERISTICS The five-level SVM diagram is shown in Fig.2. Four hexagons, as indicated by the bold lines, divide the plane into four regions, A, B, C, and D. Connection of the vertices of the space vectors, forms 96 triangles for five-level SVM. When the reference vector vertex locates in one of these triangles, a vector sequence consisting of the nearest three vectors and the-

Fig.2. Five-level space vector diagram ir redundant vectors can be used to compose its time-average approximity. In five-level SVM, zero vectors do not cause capacitor voltage variation due to capacitor zero current. Vectors and their redundancies on the first hexagon, for example, 100/211/322/433, involve only one dc-link capacitor for one specific vector. For vectors and their redundancies on the 2nd, 3rd, and 4th hexagon vertices, the corresponding dc-link circuit involves two, three, or four capacitors, for example, 200/311/422, 300/411, and 410 respectively. These possibilities introduce challenge in adjusting individual capacitor voltages and complexity in averaging the net energy among the dc link capacitors. The APF compensation and modulation processes can be arranged such that, although during one line cycle the compensating reference voltage vectors reach the full modulation index area of five-level modulation plane, most vectors are within the low modulation index area. In one line cycle, the reference voltage vector partly locates in the low modulation index area, such as regions A and B, for compensating load currents with slow change and/or no significant high order harmonics. When significant stiff load current change occurs, the reference voltage vector enters high modulation index areas due to APF compensating action. This characteristic enables a SVM algorithm to balance the APF dc-link capacitor voltages, with only redundant space vectors. In terms of APF dc-link voltage high utilization, a minimum constant dc-link voltage, which maintains APF capability to track significant stiff change of the load current, is appropriate. III. THE PROPOSED SVM ALGORITHM The proposed algorithm treats the SVM plane as two areas, I and II, as shown in Fig.3. Area I consists of regions A and B and area II consists of regions C and D. When the voltage reference vector locates in area I, redundant vectors around the 1st hexagon are used to provide accurate control of the dc-link capacitor voltages, and a standard five-level SVM algorithm is used. In Area II, SVM is treated as three-level SVM. The inte-

Fig.3. Area division of proposed five-level SVM rmediate switching states in this modulation area, such as 300/411, 310/421, etc, are neglected which results in poor exploitation of the five-level SVM advantages but the capacitor voltages are treated in pairs and the balancing process is simplified. A generalized SVM algorithm is used when calculating the timing parameters [19] [20], as shown in Fig.3. The transformations for the reference vector Vref from Cartesian coordinates to 60 coordinates are: (1) 2 V mag
V
p

sin(

2V

mag

sin

(2)

where Vmag is the magnitude of Vref, and Vp and Vq are the coordinates of Vref on the and axes of the 60 coordinate system. 1. Area I The SVM plane and associated vectors are shown within the shaded area. Compensation of each capacitor voltage is ensured by vectors 100, 110, 110, 010, 011, 001, 101 and their respective redundant vectors. Due to symmetry in the SVM plane, only the first sextant is considered for analysis, as shown in Fig. 4. When vectors V1, V2, and V3, are used to compose the desired voltage vector Vref in a modulation cycle Ts: (3) V ref T S = V 1 t 1 + V 2 t 2 + V 3 t 3
T s = t1 + t 2 + t 3

(4)

The calculation of timing parameters in the 60 coordinate system has two conditions [19]: when Vref is in sectors 1, 2 and 4, the arrangement of V1, V2, and V3 is as shown in Fig.4 (i): (5) t1 = TS t 2 t 3 t2 = V p - p TS t 3 = (V q q T S when Vref is in sector 3, the arrangement of V1, V2, and V3 is as shown in Fig.4 (ii): t1 = TS t2 t3 t2 =p+1Vp TS , t3 = VP p+Vq q1 TS (6) where p=floor(Vp) and q=floor(Vq).

Fig.4 First sextant for area I and its vectors For capacitor voltage balancing vectors in this sextant, sectors 1 and 2 have one group of short vectors available (100/211/322/433 for sector 1 and 110/221/332/443 for sector 2) while sectors 3 and 4 have two groups of short vectors (100/211/322/433 and 110/221/332/443 for both sectors), whence only sectors 1 and 3 need be analyzed. 1.1 Sector 1 In sector 1, there are four short vectors 100, 211, 322 and 433, and their corresponding active circuits are shown in Fig. 6. parts i-iv respectively. Symmetrical modulation is used to achieve voltage balancing and each vector sequence has dual capacitor voltage adjusting ability. For C1 and C4, there is one vector sequence available for voltage adjustment, 100-200-210-211-211-210-200-100 and 322-422-432-433-433 -432-422-322 respectively, while for C2 and C3 there are two vector sequences available. C1 and C4 Vector sequence 100-200-210-211-211-210-200-100 for C1 is considered for analysis. If Vc1=Max(Vc1, Vc2, Vc3, Vc4) and assuming the current ifa is positive, which means a discharging process for the capacitors, then the maximum conducting time of t1 is assigned to vector 100 to discharge capacitor C1. If Vc2=Max(Vc1, Vc2, Vc3, Vc4), then the maximum conducting time of t1 is assigned to vector 211 to discharge capacitor C2. C2 and C3 The case for C2 is analyzed. There are two vector sequences which impose the same voltage deviation effect for Vc2 adjustment: 100-200-210-211-211-210-200-100 and 211-311-321-322-322-321-311-211. Selection between these two vector sequences is made by investigating the two adjacent capacitor voltages, Vc1 and Vc3. Assuming Vc2=Max(Vc1, Vc2, Vc3, Vc4) and the current ifa is positive, if Vc1>Vc3, then the first vector sequence is selected to discharge capacitor C1, otherwise the second vector sequence is selected. This step ensures the capacitor with maximum/minimum voltage and its adjacent second highest/lowest voltage capacitor experience same discharging/charging process within a modulation cycle. The highest/lowest voltage capacitor experiences a maximum discharging/charging time and the second highest/lowest voltage capacitor experiences a shorter discharging/charging time. The conditions for selecting the vector sequence and time distribution for compensating capacitor voltages in sector 1 are generalized in Table 1, where Vmax=Max(Vc1, Vc2, Vc3, Vc4) and Vmin=Min(Vc1, Vc2, Vc3, Vc4).

Fig.5. First sextant for area II and its vectors 1.2 Sector 3 In sector 3, there are two groups of short vectors, 100/211/322/433 and 110/221/332/443. Both allow access to the individual capacitors. Group 100/211/322/433 employs current ifa while group 110/221/332/443 employs current ifc to compensate the capacitor voltages. In order to optimize the compensating effect, the compensating ability of each group must be assessed [18]: If |ifat1|>|ifct2|, then group 100/211/322/433 has better balancing ability than 110/221/332/443, i.e., states 110/221/332/443 have less influence on the capacitor voltages. Therefore 100/211/322/433 is chosen, otherwise 110/221/332/443 is selected. The remainder of the process is as for Sector 1 in 1.1. 2. Area II In area II, the modulation method treats five-level SVM as three-level SVM, where the capacitor voltages are compensated in pairs, namely C1 and C2, C3 and C4. The first sextant of area II and the associated vectors are shown in Fig. 8. In the three sectors, 1, 2, and 3, sectors 1 and 2 are the similar, i.e. one group of adoptable vectors, and in sector 3, two groups of adoptable vectors are available. Coordinates obtained from (1) and (2) are for a five-level SVM calculation. In order to transform these for three-level SVM utilization, the reference vector Vref in five-level SVM is normalized into the three-level SVM plane, by halving its magnitude, as shown in Fig. 8. Therefore: Vref3=Vref, Vp3=Vp, and Vq3=Vq. (7) where Vp3 and Vq3 are the coordinates for Vref3 in the normalized three-level SVM space. Therefore the timing parameters for each involved vector are: when Vref is in sectors 1 or 2. (8) t1 =TS t2 t3 t2 = Vp3 - p3 TS t3 = (Vq3 q3 TS , when Vref is in sector 3.
t1 =TS t2 t3 t2 = p3 +1Vp3 TS t3 = Vp3 p3 +Vq3 q3 1 TS

(9)

where p3=floor(Vp3) and q3=floor(Vq3). 2.1 Sectors 1 and 2 Sectors 1 and 2 both have one group of adoptable vectors, namely 200/422 and 220/442 respectively, and sector 1 is analyzed. The corresponding active circuits for 200/422 are shown in Fig. 6 parts v and vi respectively. In sector 1, the vector sequence is 200-400-402-422-422402-400-200 and the current for voltage compensation is ifa.

Fig.6. Circuits for vectors i: 100 ii: 211 iii: 322 iv: 433 v: 200 and vi: 422 TABLE 1 Vector Sequence Selection and Balancing Time Distribution for Sector 1 in Area I
Sector Capacitor C1 Conditions (ifa>0, Vmax=Vc1) or (ifa<0, Vmin=Vc1) ifa>0, Vmax=Vc2 C2 ifa<0, Vmin=Vc2 1 ifa>0, Vmax=Vc3 C3 ifa<0, Vmin=Vc3 C4 Vc1>Vc3 Vc1<Vc3 Vc1>Vc3 Vc1<Vc3 Vc2>Vc4 Vc2<Vc4 Vc2>Vc4 Vc2<Vc4 (ifa>0, Vmax=Vc4) or (ifa<0, Vmin=Vc4) Vector sequence 100-200-210-211-211-210-200-100 100-200-210-211-211-210-200-100 211-311-321-322-322-321-311-211 211-311-321-322-322-321-311-211 100-200-210-211-211-210-200-100 211-311-321-322-322-321-311-211 322-422-432-433-433-432-422-322 322-422-432-433-433-432-422-322 211-311-321-322-322-321-311-211 322-422-432-433-433-432-422-322 Balancing vectors 100/211 100/211 211/322 211/322 100/211 211/322 322/433 322/433 211/322 322/433

t1 t

211 100 322 211 100 211 433 433 211 322

100 211 211 322 211 322 322 322 322 433

If ifa is positive, two pairs of capacitor experience the same discharging process. If (Vc1+Vc2)>(Vc3+Vc4), the maximum time of t1 is distributed within vector 200 otherwise within vector 422. If ifa is negative, two pairs of capacitors experience a charging process. If (Vc1+Vc2)>(Vc3+Vc4), the maximum time of t1 is distributed within vector 422. 2.2 Sector 3 In sector 3, there are two vector sequences available: 200-220-420-422-422-420-220-200 and 220-420-422-442 -442-422-420-220. The first group employs current ifa for voltage compensation and the second group involves ifc: If |ifat1|>|ifct2|, then the vector sequence 200-220-420-422-422-420-220-200 is selected, otherwise 220-420-422-442-442-422-420-220. The reminder of the process is as for Sector 1 and 2. IV. SIMULATION RESULTS

The MATLAB simulation platform is as in Fig. 1. Two scenarios are implemented with the condition of balanced source side impedances. Both have a three phase diode bridge load, and one also has a single phase load. Simulation parameters are listed in Table II. TABLE II: Parameters for Simulation and Practical
Ea, Eb, Ec Ra, Rb, Rc La, Lb, Lc Lfa, Lfb, Lfc Cf C1, C2, C3, C4 25 Vac (rms) 2 2mH 18 mH 1 uF 470 F Vdc R1 L1 R2 Rf Ts 100 Vdc 130 8mH 100 80 12 kHz

1. Balanced Nonlinear Load The dc-link capacitor voltages after APF activation are shown in Fig. 9. Part i shows that the total dc-link voltage remains constant. The voltage ripple, of 0.35% the total dc-link voltage, oscillates at six times the line freque-

(A) Fig.9. Dc-link capacitor voltages: (A) with balanced load (B) with unbalanced load cy due to the load rectification characteristics. Part ii shows the four balanced capacitor voltage tracking, and the voltage difference range between any two capacitor voltages is less than 0.2%. 2. Unbalanced Nonlinear Load Fig. 10 shows the dc-link capacitor voltages. Part i shows the total dc-link voltage is maintained constant, but with 5% voltage ripple oscillating at twice the line frequency. Part ii shows the four capacitor voltages are balanced and iii shows the four capacitor voltages, amplified. 3. Evaluation of the Balancing Algorithm The proposed algorithm is evaluated in terms of the maximum capacitor voltage difference between the four dc-link capacitors, with respect to the normalized dc-link voltage and switching frequency, as shown in Fig. 11. Capacitor voltage indicates capacitor voltage normalized with respect to the utility phase rms voltage and switching frequency with respect to the line frequency. With the simulation model, capacitor voltage balancing is difficult to achieve for a normalized capacitor voltage of less than 0.7. For a specific dc-link voltage, the higher the switching frequency, the higher the compensating activity and ability to achieve a stiff compensating current, which means better APF energy regulation, thus more precise control. At a specific switching frequency, at a low dc-link voltage, a higher dc-link voltage gives better balance, until a critical value is reached after which the capacitor voltage difference increases. This critical value is a function of system bandwidth and modulation index. On one hand, a high dc-link voltage after this critical value introduces phase current oscillation, and capacitor voltages become irregular with increased voltage difference. On the other hand, the reference vector locus

(B)

approaching the center of modulation plane imposes limitations on the conduction times of the compensating vectors. This reduces compensation and results in irregular energy flowing into the dc-link capacitor bank which increases voltage ripple.
Capacitor voltage difference %

1.5 1 0.5 0 40 80 120 160 0.9 0.8 0.7

200

Sw itching frequency (Normalized to line frequency)

1.3

1.2

1.1

Capacitor voltage (Normalized to phase voltage r.m.s)

Fig.11 Evaluation of the balancing algorithm V. EXPERIMENTAL VERIFICATION

The practical parameters for the experimental platform, based on Fig.1, are the same as for the simulations. An Infineon TriCore TC1796 is used to implement the control scheme. 1. Balanced Nonlinear Load Fig. 12 (i) shows the total dc-link voltage Vdc, and ii shows the zoomed capacitor voltages. The dc-link voltage is maintained with less than 1.6% total voltage variation. Balancing has been achieved with less than 0.8% voltage difference between capacitors, which is insignificant in practical terms. There is a small line frequency voltage component in the capacitor voltages, as shown in ii, due to system measurement errors and nonlinearities.

(i)

(i)

(ii) Fig.12 Capacitor voltages under balanced load conditions 2. Unbalanced Nonlinear Load Fig.13 shows the capacitor voltages for an unbalanced non-linear load, where although the voltages are controlled and balanced, 4.8% voltage ripple appears. The hardware components must withstand a widely varying voltage stress, where the maximum capacitor voltage difference is less than 2.4%. VI. CONCLUSION

(ii) Fig.13 Capacitor voltages under unbalanced load conditions

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Dc-link capacitor voltage balancing for the five-level diode-clamped APF has been achieved, with full utilization of the dc-link voltage. Based on APF operational characteristics, a hybrid SVM algorithm which considers the optimal vector sequence within each modulation cycle, has been proposed for balancing dc-link capacitor voltages. For redundant vector sequences with same balancing ability, optimal selection is made according to the most-appropriate two adjacent capacitors. For the redundant vectors sequences with different balancing abilities, that with best balancing capability is used. Simulation and experimental results were presented to validate the proposed process. REFERENCES
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