An IDDQ Current Sensing Circuit for Concurrent Timing Error Detection in a Bank of Flip-Flops Ravi Kanth Uppu- 11/29/2011

Abstract: Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system operation are caused by transient faults, which often manifest themselves as abnormal signal delays that may result in violations of circuit element timing constraints. The concurrent errordetection circuit senses and signals when data in any of the flip-flops from a bank of flip-flops has been potentially corrupted by a setup or hold timing violation. The circuit employs on-chip quiescent supply current evaluation to determine when the input changes in relation to a clock edge. Current through the detection circuit should be negligible while the input is stable. If the input changes too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the time of the clock transition, and an error is flagged. I. Over View of the Design The error-detection circuit developed allows a flip-flop (or other circuit element) to detect if its timing specifications in relation to a clock edge have been potentially violated; specifically, if the input signal has not been stable over the setup and hold time window. The basic principle upon which the detector operates is that in CMOS circuits, current is drawn from the power supplies only during switching transients. This current can be measured over time to determine when the inputs change in relation to a clock edge, such as the flip-flop clock. The key idea is to use a current sensor to detect any current flow in a dummy inverter (transient current generator) that is connected in parallel to the flip-flop and is driven by the same input, Din. Switching delays associated with this inverter are so controlled that any instability of the input signal over the setup and hold time window results in a transient current in the sensor circuit. II. Circuit Details The error-detection circuit developed allows a flip-flop (or other circuit element) to detect if its timing specifications in relation to a clock edge have been potentially violated; specifically, if the input signal has not been stable over the setup and hold time window. The basic principle upon which the detector operates is that in CMOS circuits, current is drawn from the power supplies only during switching transients. This current can be measured over time to determine when the inputs change in relation to a clock edge. The key idea is to use a current sensor to detect any current flow in a dummy inverter (transient current generator) that is connected in parallel to the flip-flop and is driven by the same input. Switching delays associated with this inverter are so controlled that any instability of the input signal over the setup and hold time window results in a transient current in the sensor circuit. Fig. 1 shows two transient current waveforms for the dummy inverter. The left waveform (1) is for the case when the input signal changes right at the minimum setup-time specification for the flip-flop with respect to the flip-flop clock. Any shift of this waveform to the right would indicate a setup time violation. The other waveform (2) shows the transient current when the input changes right at the minimum hold time specification. Any shift of this waveform

to the left would indicate a hold-time violation. The timing error- detection circuit compares the current in the dummy inverter against a reference current at a designated sensor clock time, shown in Fig. 1. A timing violation error is flagged if the transient current in the dummy inverter exceeds the reference. Observe that if the input changes and stabilizes before the setup time, then current waveform (1) will shift further to the left while retaining its shape. Thus, it will have dropped below the reference at the sensor clock time, so no error will be flagged. However, if the input changes after the setup time, waveform (1) shifts to the right and an error will be flagged. Similarly if the input changes after the hold time, the current will not have risen enough to flag an error at the sensor clock time. However, if the input changes before the hold time, the waveform (2) will shift to the left and an error is flagged. There are three basic parts to the circuit. These are i) buffer, timing capacitance, and transient current generator, ii) current sensor, and iii) clock delay generator. The major advantage of this design is that, when a bank of flip-flops is to be protected, circuitry ii) and iii) can be shared since only one copy is needed and the additional overhead for each flip-flop, which is only the circuit in part i), is modest. The input to the sensor is a buffer that consists of an inverter connected in parallel to the input of the flip-flop. The purpose of this buffer is twofold. First, it serves to buffer the sensor from the input line of the flip-flop. This reduces the loading effects of the sensor on the signal line. The second purpose is to modify the transient curve characteristics. The transient curve characteristics are to be modified in such a way that the window of the transient curve is almost the same as the setup time. Increasing the window would improve the error detection window while performing DVS or any other faults that occur due to Single Event Upsets (SEU). The transient curve characteristics can me modified by the sizing factor of the transistors that precede the current generator. In our case we used a 1aF capacitor.

Fig (1) Transient currents in relation to Setup & Hold times

The following figure shows setup of a bank of flip-flops, with buffer, current generator, current sensor & clock delay generator. Bank of Flip-Flops

Error

Clock Delay Generator

Current Sensor

The current transient curve characteristics are observed to be as follows:

The following simulation results were obtained from Modelsim Design Architect, using TSMC 180nm technology. These results illustrate the functioning of a current sensor for a bank of flipThe setup time & hold time were observed to be 55ps & 40ps respectively, from the above figure it is evident that the window of the transient curve is about 63ps, this can be manipulated by the capacitance between the two inverters.

flops, further it can be substantiated that only the buffer & current generator are to be built for every flip-flop which would be the only overhead and the clock delay generator and current sensor are shared by the bank of flip-flops.

The first figure shows the violations in setup & hold time, this can be assured by looking at the error signal. Whenever the error signal goes low there is a potential setup or a hold time violation. The first graph is the delayed clock, which is followed by the current transitions that are generated (due to the inputs applied to each flip-flop) by the current generator and the final graph is the error signal given by the current sensor. The second figure shows the zoomed version of the first one.

Future Applications:
The above setup can be used with a pipeline processor, with just the delayed clock & the current sensor circuit in common for each pipeline stage for a Lower power based Adaptive testing. Dynamic Voltage Scaling (DVS) can be effectively implemented, if the critical path falls beyond clock period. Detection of Single Event Upsets (SEU) is also possible. Consumes reasonable area over head.

References:
An IDDQ Sensor for Concurrent Timing Error Detection, Christopher G. Knight, Adit D. Singh, Member, IEEE, and Victor P. Nelson, Senior Member, IEEE. RazorII: In Situ Error Detection and Correction for PVT and SER Toleranc, Shidhartha Das, Member, IEEE, Carlos Tokunaga, Student Member, IEEE, Sanjay Pant, Member, IEEE, Wei-Hsiang Ma, Student Member, IEEE, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, and David T. Blaauw, Member, IEEE