A Novel Genetic Algorithm for the Automated Design of Performance Driven Digital Circuits: A Critical Appraisal

Olla A. Ashour
Department of Mathematics, Faculty of Science, Alexandria University, Alexandria, Egypt Email: olla.ashour@gmail.com

Abstract
[Critical abstract of] Ben. I Hounsell and Tughrul Arslan. Novel genetic algorithm for the automated design of performance driven digital circuits. Proceedings of the 2000 Congress on Evolutionary Computation, 1(1), 601-608, July 2000. This research describes the design of complex circuit design using genetic algorithms by taking consideration important constraints mainly area (or number of circuit components) and timing which affect the performance of the circuit while directly evolving and evolving circuits in a hardware description language (HDL) that allows for easy circuit synthesis and simulation. The results of this study allow for the design of any complex circuits by only providing to the genetic algorithm a Boolean table while easily simulating the structure of the complex circuit designed and in addition providing efficient and high-performance circuits. The paper will interest circuit designers and those developing sub-micron technologies as todays silicon technologies take in consideration performance as a factor more than other any other factor. The paper could be a reading material for courses related to machine learning, circuit designs, and artificial intelligence. The paper is informative and organized in an overall well structure. In order to improve the papers presentation, purpose and justification further figures especially of the circuit structures, citations of claims, and additional criteria in the performance factors and the development of the genetic algorithm could have been taken in consideration during the research. In addition a more detailed explanation of the results with more statistics and figures. The bibliography could be extended slightly, to include a few more old and recent references.

1 Introduction
1.1 About the Authors
The paper Novel Genetic Algorithm for the Automated Design of Performance Driven Digital Circuits is co-written by Ben. I Hounsell and Tughrul Arslan of the Department of Electronics and Electrical Engineering, University of Edinburgh, Mayfield Rd, Edinburg, Scotland and was presented in the Proceedings of the 2000 Congress on Evolutionary Computation in 16-19 July 2000 at La Jolla, CA, USA. As of the year 2000, the author Tughrul Arslan published more than 50 articles in the fields of Analogue and Digital Circuit Design using traditional CAD tools and evolutionary algorithms in order to

produce high performance circuits which were mostly published in either the IEEE Journal or presented in many International conferences/proceedings. Professor Arslan was an Associate Editor for the IEEE Transactions on Circuits and systems I and IEEE Transactions on Circuits and Systems II. He is a member of the IEEE CAS Committee on VLSI Systems and Applications and is involved in the organization of numerous conferences. Recently he was the general chair for the IEEE NASA/ESA conference on Adaptive Hardware and Systems (AHS) and the ECSIS Bio-inspired, Learning, and Intelligent Systems for security Symposium (BLISS). He has been invited as a keynote speaker to a number of international conferences [5]. On the other hand, little information is available on Ben. I Hounsell, but as of 2000, only two known papers [1, 7] have been found published based on search results from IEEE, Springer and Google Scholar in which one of the papers is the paper under critical appraisal here.

1.2 Purpose and Significance of Work

Due to advances in silicon technology, new methods of circuits design have to be researched in order to design circuits with optimal performance. Traditionally in order to design a digital circuit, it requires that designers know large collections of domain-specific rules in order to design circuits based on a Boolean logic table to implement certain functionality. Generally, in order to implement a digital circuit, a 3 step process is involved. Logical specification transformation of circuit onto a form suitable for the target technology, optimization of design with respect to a number of user defined constraints and finally to map the circuit design onto target technology in order to test it. But the process requires that designers know large collection of domain-specific rule which hinders the design process as it depends on the training and experience of the designer and the amount of domain-specific knowledge known to the designer so hence restricting the design. So an alternative has to be found. Also traditionally for designers during optimization of designs, the circuits evolved before optimization must be each tested against a fitness function and it is not feasible to transfer the circuit directly onto silicon for evaluation( intrinsic evaluation) every time a design is improved (evolved) before it reaches optimal level, hence, it is time consuming and wastes resources. So an alternative approach was found namely Evolvable Hardware (EHW) which unlike traditional techniques which employ top down design methodology in which complex systems are broken down into small sub-systems and assigned to a number of design groups, evolvable hardware on the other hand approaches the design problem as a whole system generating a black box of the completed circuit, i.e. Bottom up design methodology. The only information that is presented to the design engineer is a Boolean logic table and the evolutionary algorithm can produce a set of possible circuit designs for the specified functionality of the Boolean logic table which is later evolved until the constraints imposed on the algorithm are met.

In addition, circuit evaluation can be done through software simulation (extrinsic evaluation) as opposed to intrinsic evaluation which allows evolved circuits to be easily examined and tested once a solution has been found. Hence, evolvable hardware considers the automated design of digital systems using both software simulation and programmable hardware technologies (which implements the optimized circuit onto the specific silicon technology) [1]. The paper presented describes the above technologies in the utilization of circuit design i.e. evolvable hardware and extrinsic evaluation as due to the increased growth of computing devices it has become inevitable to design complex circuit designs which cannot be limited by the designers knowledge of domain specific rules. The above methodologies will help create very complex circuits that were not possible before and to evolve circuits larger than those detailed with only having the knowledge of a Boolean table and to provide the optimal circuits based on the constraints imposed by the design. So hence a new advancement in circuit design specifically in designing computing devices that was not possible before is introduced in their work. Fig 1 Provides a Summary of the Process [4].

The paper is mainly targeted for DSP (Digital Signal Processing) applications and VLSI (Very Large Scale Integrated) circuit designers. In addition other audiences interested in Genetic Programming and its various utilizations in many scientific fields can benefit from the use of GA in a specific research as circuit design. In the design of VLSI (Very Large Scale Integrated) circuits, there are many concerns for which VLSI designers take in consideration such as area, performance, cost, reliability and power [2]. So, one of the most important significance of this paper is that with compared to other research papers in the same field [6, 8, 9] which used evolvable hardware or specifically evolutionary algorithms in designing circuits, the authors incorporated performance constraints that were not utilized in previous research during the optimization (the fitness of a circuit undergoing evaluation) process in namely i.e. timing and area constraints.

Additionally, the authors created a novel environment for which to simulate and test evolved circuits and later only implement the optimized circuit directly onto the hardware using a hardware programmable language thus effectively designing novel complex circuits and reducing time and resources in the design process optimization. Compared to [10] in which the novel environment used is a Java-based tool using FPGAs (Field Programmable Gate Array) to implement legal configurable circuits which are neither temperature, voltage, nor silicon dependent , Arslan and Hounsell created a novel environment in which the environment termed Virtual chip is a combination of C routines and VHDL (Very High Speed Integrated Hardware Description Language) which based on their citied work is one of the two dominant languages used in describing digital electronic systems. Furthermore, this paper compared with previous work of author Tughrul Arslan concentrates on the timing and area constraints where notably he previously worked more on power as a more important constraint in circuit design in both traditional methods such as Circuit Aided Design(CAD) and in the more innovative evolutionary algorithms methods specifically Genetic Algorithms. However, Both Tughrul Arslan and Ben.I Hounsell worked together on the paper Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits[7] presented during the duration of 8-12 July 2000 in a different proceeding in which they developed the novel environment i.e. Virtual Chip and used the Genetic Algorithm in exactly the same way, the only difference is that in [7] they used only a 3-bit multiplier to demonstrate their findings while in our paper of interest they used the full adder, 2- and 3-bit multipliers and the 7-bit pattern recognizer to demonstrate their results so this paper does not have any significance in the field of Circuit Design using evolutionary algorithms except to only prove that the work earlier presented by the authors can be extended to implement and design additional arithmetic circuits but it does not introduce any new ideas.

2 Summary and Description of the Paper

Genetic algorithms for evolvable hardware are used to develop chromosome structures which encode the functional description of a circuit. In the utilization of genetic algorithms to design circuits, the resulting circuit is called the phenotype which consists of many smaller logic cells called genotypes. The representations of solutions in the GA use permutation-based encoding of fixed length, so therefore only a specified number of logic elements are presented to the framework. The circuit description defined in the chromosome structure is as follows

Figure 2: Ch ro mosome structure defining sections for specific circuit description

where specific sections of each chromosome are reserved for describing the inputs and outputs required for the desired circuit. Logic elements are referenced by position within the chromosome. Total chromosome length is defined as the number of logic elements summed with the number of circuit inputs. The genetic algorithm used in this paper does not use individual primitive gates only to design circuits but rather a range of functional elements or macro-blocks stored in the component library such as combinatorial ORed output. Each genotype (logic element) in a circuit is allocated a specific position within the corresponding chromosome. Initially the position of logic cell is determined randomly but cells can be allocated different positions after initialization through manipulation of genetic operators.

Figure 3: Examp le of macro -based encoding describing a macro element (fulladder) and its connectivity.

Note: Cell connectivity is not restricted to nearest positional element but rather cells are free to connect to any cell of higher position within the chromosome. So hence, a wide range of possible circuit configurations are possible. However feed-back connections are not permitted since they produce undesirable effects not desirable in DSP applications. In any genetic algorithm parameters and constraints have to be defined and imposed for which the algorithm will use in order to reach optimality. They are as follows: Number of Inputs and outputs required for desired circuit; Definition of input and output vectors that describe circuit functionality and upon which evaluation takes place; Number of logic elements within a chromosome used to create the circuit. Maximum number of possible fan-outs (the number of gate inputs to which it is connected) per cell output. In order to optimize cell connectivity, each output pin is randomly allocated a fan-out ranging between one and a user defined maximum; Definition of global clock speed for timing constraints;

Population size, defining the number of circuit solutions concurrently evolving within the search space.

The Genetic Algorithm: Two-way tournament selection implemented (Two chromosomes are selected randomly and the fittest becomes a member of the next generation.) One-point crossover at 0.7; Chromosome repair is applied using nearest neighbor and in the event no logic elements are available for connection, current element is assigned a floating and further attempts at reconnection are made during later crossover operations;

Figure 4: Examp le of broken element connectivity resulting fro m crossover.

Mutation using Muhlenbein derivation P (m) = 1/L with application specific operators, where L denotes the total number of logic elements encoded in the chromosome (N).

Figure 5: Four mutation operators used by the genetic algorith m.

Population Size = 50; Fitness is represented as a percentage of circuit functionality. Correctness is calculated by summing the total number of correct bits produced by the circuit solution under evaluation and comparing it to desired output response. = =

is the total number of bits comprising the desired output vectors. is the actual number of bits matched with output vectors during Evaluation. Evaluation of the fitness function is achieved through interaction with a HDL (Hardware Description Language) namely VHDL (Very High Speed Integrated Hardware Description). A combination of the VHDL and the Genetic Algorithm are implemented through a novel environment called Virtual Chip which provides an automated design procedure. It directly evolves and evaluates circuits in HDL after the genetic algorithm is used to evolve circuits. Since the Virtual Chip evolves circuit structures directly within the VHDL, detailed simulation and analysis of each circuit is possible with any technology specific component library i.e. specific constraints as area and timing. The automated design procedure is performed through a testbench which instantiates and interconnects all logic elements within each chromosome, used to describe a specific circuit solution. Evaluation is performed by instantiating and simulating all circuits described within a population of chromosomes, as if they were being implemented within a single reconfigurable chip. In order to apply the timing constraint, all inputs and outputs are synchronized with flip-flops governed by a global clock to account for propagation delays and ensure that all output signals have reached a steady state. Individual Circuits evolved are each grouped by a 4-bit output within the virtual environment. Each grouping is tagged according to the circuits ID within the evolving population. Every circuit solution is therefore represented as a technology independent VHDL netlist whereby netlists are direct interpretations of the circuit chromosome and define a circuit in terms of its logic elements and inter-connectivity. CAD tools can then be used to both optimize the circuit and translate the generic netlist into a technology specific netlist form suitable for implementation in hardware. The Virtual chip is a fusion of C code and VHDL. The genetic algorithm itself is executed in C and generates the VHDL required to instantiate each chromosome encoded

circuit. The Genetic algorithm and evaluation environment can be summarized as follows:

Figure 6: Execution flow and encoding format of the genetic algorithm and Virtual ch ip evaluation environ ment.

Table 1: Co mparison of the genetic and conventional circuit generation of d ifferent arithmet ic circuits in terms of functionality.

Note: Timing Slack is defined to be the duration for which the slowest output of the circuit remained stable before the next data pulse arrives. Each Circuit structure was evolved 10 times and terminated after 10,000 generations if a fully correct solution (fitness = 1.0) had not been found. Analysis of the arithmetic circuits presented in the paper provides insights into complexity issues associated with automated circuit design. Table 1 details the average number of generations required by the genetic algorithm to produce a correct circuit solution. The figure below displays the average performance of the genetic implementation when evolving each circuit architecture.

Figure 7: Typical nu mber of generations taken to evolve a 1-bit fu lladder, 2-bit mu ltip lier and 7-bit pattern recognizer.

In conclusion, a novel genetic algorithm for the automated design of performance driven arithmetic circuits has been presented. The algorithm also describes a flexible chromosome encoding designed to fasciculate complex circuit structures with a minimal number of logic elements. The environment in which circuits are evaluated has also been presented. Four arithmetic architectures have been examined. Each of the architectures was autonomously generated using the genetic algorithm and compared with equivalent architectures developed using conventional high-level design methodologies (CAD). Results show that the arithmetic circuits generated using the genetic algorithm operate well within the timing restrictions imposed. For this reason the use of a genetic algorithm leads to a significant saving in design time whilst taking into consideration timing issues crucial to todays deep sub-micron technologies.

3 Evaluation and Analysis of Work

In their paper, Arslan and Hounsell organized their overall organization plan in paper as required by international conferences and journals in terms of an introduction, describing the methodologies used, later discussing their implementation and results and finally ending with a conclusion. Generally the paper is well conceived and the authors do achieve their objectives in their implementation and results. But in moving between one section or subsection to another, there is a lack of clear definition on what is the purpose of this subsection and how it relates to the overall picture. One way the authors could have fixed this issue is by providing a more detailed insight into the methodologies or technologies to be used in a introduction before directly describing how they will implement these technologies in their research. Furthermore in each section/subsection, a introduction of the subsequent sections/subsections can be introduced to help enhance the understanding of the reader and to allow for easier reading. In any research, assumptions are always made. These assumptions may be stated or lurk behind statements. The underlying assumptions taken by the authors were considered assumptions as there was no evidence stated in terms of citations to support their arguments. First of all the authors assume that in the use of evolvable hardware and extrinsic evaluation of circuit design, the system is not accurately modeled as timing and area constraints of DSP circuits is not take in consideration. The authors argue that for high performance of DSP circuits, area and timing constraints must be accounted for. However the authors did not offer any citation to support this argument. Also in the encoding of a circuit in a chromosome, the authors stated Feed-back connection, however are not permitted as there effects are not

desirable for most DSP applications. Unfortunately again Hounsell and Arslan did not offer any reference to support their argument. Furthermore they did not offer any insight into these undesirable effects. One of the major claims that the authors claimed as stated by them is The authors are currently unaware of applications using genetic algorithms which incorporate timing and area performance considerations into the fitness of a circuit undergoing evaluation where hereby there is notably no citation referenced on the specific use of a Genetic Algorithm in the design of digital circuits to prove this claim. Yes, the authors have referenced Evolutionary Strategies and Evolutionary Programming but none specifically involving the use of Genetic Algorithms, so here a question is proposed on what basis did they offer the above claim?! In the design of VLSI (Very Large Scale Integrated) circuits, there are many concerns for which VLSI designers take in consideration such as area, performance, cost, reliability and power considerations. Power Consideration has begun to take more consideration than that area and speed and is considered a more critical constraint than area and timing [2]. Despite the authors having citied [2] they only took in consideration area and timing constraints which are not sufficient for the design of performance driven digital circuits. It can be argued that the use of area and timing as constraints is insufficient and as [2, 3] stated that due to the increase of computing devices, it has become more important to take power dissipation more into consideration. It may be pointed out that even thou Arslan in previous work [5] described circuit design using genetic algorithm with power as a constraint he did not however evaluate the circuit performance with respect to power as a constraint through interaction with a hardware descriptive language. The authors choose to use the genetic algorithm as their evolutionary algorithm by stating that it is the most dominant approach used as stated by Goldberg (1989) and Bck (1996) but however neither the authors or Goldberg and Bck compared the use of other evolutionary algorithms in the design arithmetic circuits such as neural networks, fuzzy logic and genetic algorithm and how it is preferable to use the genetic algorithm. Generally, in order to implement a Genetic Algorithm, a problem must be defined for which the algorithm will utilize in order to reach Optimization i.e. the fitness function. The Authors defined the problem as such The automated design of arithmetic circuits is not trivial. Each possible circuit solution for a given task lies within a search space. The search space is defined by the number of different component building-blocks presented to the framework, the number of logic elements used to generate the circuit, and the application for which the circuit is being evolved. Evolutionary algorithms are employed within EHW as they provide a non-heuristic investigation of what is potentially a very large search space. Successful solutions are often made more difficult to find as the output response must be exact, for instance as part of a sequence of operations such as memory mapping. This differs from other types of circuit which instead approximate a specified analogue transfer function. It is a combination of these factors which has resulted in the difficulties experienced by researchers to evolve circuits larger than those detailed. In addition, one draw-back of extrinsic evaluation is that little information is processed in terms of how accurately a system is modeled, as in most cases the additional detail required has not been integrated into the software. This inhibits the

development of high performance DSP circuits where timing and area constraints are of great importance, and therefore must be accounted for in EHW applications. The authors are currently unaware of applications using genetic algorithms which incorporate timing and area performance considerations into the fitness of a circuit undergoing evaluation. But based on research papers that use Genetic Algorithms as their focal points [3,4,6] they usually describe the problem in terms of an equation that needs to be optimized i.e. an Objective Function usually it being a minimization function. In their paper the authors did not clearly state their optimization problem whereby they should have stated clearly perhaps in a process diagram or in an equation definition, a clear description of the parameter equation inputted into the Genetic Algorithm on which the constraints will be imposed which will eventually lead to optimization. In the implementation and results section, no depiction was offered of the structures of the arithmetic circuits in terms of architecture using the genetic algorithm. In [6, 9] the authors gave a clear description of the circuit components structure that resulted from using the genetic algorithm to design them. The authors only gave a written description but if a structure of the circuit was provided it would have enhanced the paper greatly. Also another major drawback of this paper is the authors did not describe any problems encountered or have resulted, and how to avoid these problems or how to further extend the research into minimizing those problems. A key importance of the paper was the authors in their genetic algorithm used a two way tournament selection. Tournament selection has several benefits; it is efficient to code, works on parallel architecture and allows the selection pressure to be easily adjusted. Moreover another advantage was the addressing of broken element connectivity resulting from crossover that was not addressed before. But an additional GA operation the authors could have integrated is elitism in crossover where at least one solution is copied without changed to a new population, so the best solution found can survive to end of run without any changes. One of the main significance of the paper with compared to similar research is the development of a the virtual chip environment to provide a means of synthesizing circuits and testing each of the design evolved in every generation using direct hardware description language. In the implementation and results section, the authors quoted Due to the implicit parallelization of the Virtual Chip environment, the entire population is compiled, and simulated as one entity. This differs from most standard approaches which evaluate each individual solution sequentially. As a result, within the Virtual Chip environment, an entire population of fifty individuals, evolving for example fifty 2-bit multiplier circuits, can be simulated and evaluated in approximately five seconds. In contrast, if each circuit were evaluated as an individual entity, it would take approximately two minutes to evaluate the same population, here a conclusion was made i.e. that it would take two minutes to evaluate the population without any findings for which to draw that conclusion. Also another conclusion that the authors offered without providing reasonable explanations and insight into it was that they concluded in the results Analysis of the arithmetic circuits presented in this paper

also provides insights into complexity issues associated with automated circuit design they did not offer any descriptions of those complexity issues. It can also be stated that in the bibliography provided, there is not enough citation referenced. The paper was published in 2000 and the oldest paper citied was 1989 and in between 1989 and 1995 no papers at all were citied. In addition there is a lack of referenced papers in the design of circuits using genetic algorithms as only 2 papers were about circuit design using genetic algorithm from the 12 papers referenced and there were many papers published in that field during that time such as [9].

4 Conclusion
The paper overall discusses a very significant aspect in circuit design and effectively presents a novel genetic algorithm for the automated design of performance driven arithmetic circuits. The results described by the authors effectively describe and fulfill the objectives and aims described by the authors. It is only in the some sections of the paper that lacked clarification of methodologies, results, and conclusions. In addition there were many claims not effectively supported by facts and citations. In addition there were several additional factors that could have been taken in consideration during the research.

References
[1] HOUNSELL, B.I. AND ARSLAN, T., A Novel Genetic Algorithms for the Automated Design of Performance Driven Digital Circuits, in Proceedings of the 2000 Congress on Evolutionary Computation, 1(1), 601-608, July 2000 [2] PERDAM, M., Power Minimization in ic design: Principles and applications, ACM Transactions on Design of Electronic Systems, 1(1), 3-56, January 1996 [3] AL-SAIARI, U.S., Digital Circuit Design through Simulated Evolution, M.SC. Thesis, King Fahd University of Petroleum and Minerals, Dhahran, November 2003 [4] J.BAHARATHI, P.SAKTHIVEL, Design of High Performance Synchronous Digital Circuits for Evolvable Hardware Application using Genetic Algorithm, Proceedings of the 6 th WSEAS International Conference on Evolutionary Computing, pp 302-307, Lisbon, Portugal , June 2005 [5] The University of Edinburgh, System Level Integration Research Group, Prof. Tughrul Arslan Profile http://www.see.ed.ac.uk/~slig/people/staff/arslan.php [Last Visited: January 2012] [6] MILLER.J.F., THOMSON .P., FOGARTY.T, Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study, Department of Computer Studies, Napier University 1997

[7] B. HOUNSELL AND T. ARSLAN, A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits, GECCO-2000, pp. 525 532, 8-12 July 2000 [8] COELLO, CARLOS A.; CHRISTIANSEN, ALAN D. & HERNNDEZ AGUIRRE, ARTURO, Automated Design of Combinational Logic Circuits Using Genetic Algorithms, Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms ICANNGA'97, University of East Anglia, Norwich, England. Edited by D. G. Smith, N. C. Steele and R. F. Albrecht, Springer-Verlag, pp. 335-338. 2(4), April 1997 [9] MILLER.J.F., KALGANOVA.T., LIPNITSKAYA.N., JOB.D., The Genetic Algorithm as a Discovery Engine: Strange Circuits and New Principles, Proceedings of the AISB, Citeseer, 1999