23/03/12

ARMCC: NESTING INTERRUPTS

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ARMCC: NESTING INTERRUPTS

Information in this article applies to: RealView Compiler Version 3.0 or higher ce

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QUESTION

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The classic ARM architecture only provides two interrupts (IRQ and FIQ). The Vectored Interrupt Controller or Advanced Interrupt Controller provides interrupt priorities and interrupt nesting for th standard interrupt, but it requires that you set the I bit in the CPSR. What is the best method to allow interrupt nesting with the RealView compiler?

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ANSWER

It should be noted that good programming technique implies that you keep interrupt functions ve When you are using short interrupt functions, interrupt nesting becomes unimportant. When you an Real-Time Operating System (such as the RTX Kernel), the stack usage of user tasks becomes unpredictable when you allow interrupt nesting.

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However, if you still need interrupt nesting in your application, you may implement it using an ass language wrapper function as described below: E a e: function you want to allow interrupt nesting: / Citrutfnto / nerp ucin / CerEN1itrutfa / la IT nerp lg / wi aln tm / at og ie / iceetitrutcut / nrmn nerp on / AkoldeItrut / cnweg nerp

Within the following __i

vi en1iq(od _iq { od it_r vi) _r ETN XIT =2 ; dly(; ea ) +itpcut +nr_on; VCetdr=0 IVcAd ;

Change the interrupt function as shown below: etr vi en1iq(od; xen od it_r vi) vi en1sv(od { od it_r vi) ETN XIT =2 ; dly(; ea ) +itpcut +nr_on; /VCetdr=0 /IVcAd ; / waprAMitrutfnto / rpe S nerp ucin / Citrutcd / nerp oe / CerEN1itrutfa / la IT nerp lg / wi aln tm / at og ie / iceetitrutcut / nrmn nerp on / AkoldeItrut / cnweg nerp

Add the following assembler wrapper (in a separate assembly module) to the interrupt function:

PEEV8 RSRE AE RA NS_R,CD,RAOL ETIQ OE EDNY AM R IPR en1sv MOT it_r EPR en1iq XOT it_r en1iq it_r PS UH MS R PS UH MR S PS UH B L PP O MR S
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{0R,1,R R-3R2L L,SS R PR {R L CS_,#xF PRc 01 {R L en1sv it_r {R L CS_,#x2 PRc 09

;sv rgse cnet ae eitr otx ;Cp SS_r t L oy PRiq o R ;Sv SS_r ae PRiq ;Eal IQ(y Md) nbe R Ss oe ;Sv L ae R

;RsoeL etr R ;DsbeIQ(R Md) ial R IQ oe

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23/03/12

ARMCC: NESTING INTERRUPTS MR S CS_,#x2 PRc 09 PP O {R L MR S SS_xf L PRcs, R

;DsbeIQ(R Md) ial R IQ oe ;RsoeSS_r t L etr PRiq o R ;Cp L t SS_r oy R o PRiq ;AkoldeItrut cnweg nerp

VCetdr=0 IVcAd ; MV O R,0 0# SR T R,R,-xD] 0[0#0F0 PP O SB US ED N {0R,1,R R-3R2L R5R4#x04 1,1,000

;rsoergse cnet etr eitr otx ;rtr fo itrut eun rm nerp

Note:

The example above shows interrupt nesting with the NXP LPC2000 devices. It is important th move the interrupt acknowledge sequence VICVec Add = 0; to the assembly wrapper. Othe devices may require a different interrupt acknowledge sequence. Therefore consult the user's of the ARM device that you are using.

MORE INFORMATION
Nesting Interrupt (irq) Functions with RealView Compiler

SEE ALSO
ARM: SPORADIC INTERRUPT PROBLEMS ARM: DESCRIPTION OF ERROR MESSAGES

FORUM THREADS
The following Discussion Forum threads may provide information related to this topic. LPC2378 - RTX protect interrupts handler Nested Interrupts in Bootloader Nested Interrupts nested interrupt problem Nested interrupts nested interrupts Error C197: inline-asm: invalid expression token MSR CPSR_c, #(0x12|0x80)
L as t Reviewed: T ues day, M arc h 2 3 , 2 0 1 0

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