Abstract- Hearing aids are primarily useful in improving the hearing and speech comprehension of people who have

hearing loss that results from damage to the small sensory cells in the inner ear. Decimation is the process of reducing the sampling rate. In practice, this usually implies low pass-filtering a signal. The range of human hearing is generally considered to be 20 Hz to 20 kHz, but the ear is far more sensitive to sounds between 1 kHz and 4 kHz. Hence it is more useful to design a hearing aid application operating within the specified frequency range. So decimation filter perform the task of reducing this sampling rate. In this, we deal with the design and implementation of a decimation filter used for hearing aid applications. We implement the decimation filter using the canonic signed digit (CSD) representation. Its complete architecture is captured using DSP Block set. The filter will implement on VHDL. Introduction- A hearing aid is a small electronic device that one wears in or behind his/her ear. It makes sounds louder so that a person with hearing loss can listen, communicate, and articipate better in daily activities. A hearing aid can help people hear more in both quiet and noisy situations. Both the input signal and the output signal are in analog form. Digital signal processing provides an alternative method for processing the analog signal as shown in figure 1.2. To perform the processing digitally, there is a need for an interface between the analog signal from outside world and the digital processor. This interface is called an analog to digital converter. The output of the A/D converter is a digital signal that is appropriate as an input to the digital processor

Figure 1 Block diagram of a digital signal processing system.

The analog input signal must first be sampled and digitized using an ADC (analog to digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form. In a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current shown in figure 2.

Fig 2: Basic set-up of a digital filter

Advantages of digital hearing aids Digital hearing aids promise many advantages over conventional hearing aids. These include: Programmability; Much greater precision in adjusting electro acoustic parameters; Selfmonitoring capabilities; Control of acoustic feedback The use of advanced signal-processing techniques for noise reduction; Automatic control of signal levels; and Self-adaptive adjustment to changing acoustic environment PAPER 1 TITLE: LOW POWER DIGITAL FILTER IMPLEMENTATION IN FPGA FOR HEARING AID APPLICATION Decimation filter: A suitable filter for hearing aid application is designed using Distributed Arithmetic. The filter uses decimation filter followed by two filters i.e. FIR filter followed by corrector filter. Using Comb-FIR-FIR and Comb-Half-band FIR-FIR, the power is calculated and the values are 61 mw and 50 mw respectively. Low power latch: A novel low power latch is designed in this dissertation. The design is carried out using both 350 nm and 180 nm technology. PAPER 2 TITLE: DESIGN AND IMPLEMENTATION OF A DICIMATION FILTER FOR HEARION AID The comb-half-band FIR-FIR decimation filters designed using Matlab and checked for real-time implementation using Simulink. The stop band attenuation obtained is -80 dB. The use of the hardware efficient CSD multiplier instead of a conventional multiplier contributes to a substantial reduction in hardware. It contributes to a hardware saving of 69%, and a power saving of 83% compared to the combFIR-FIR architecture. PAPER 3 TITLE: AN AREA OPTIMIZATION OF DECIMATION FILTER USING CSD REPRESENTATION FOR HEARING AID APPLICATION In this decimation filter using canonical signed digit representation for hearing aid application with input signal frequency as 1.28 kHz and the output signal frequency as 4 kHz with stop band attenuation of -80db. The advantage of this filter in comparison to the existing is that a considerable reduction in hardware and less power dissipation can be achieved.

PAPER 4 TITLE: ON DISHGN AND IMPLEMENTATION OF DECIMATION FILTER FOR MULTISTANDARD WIRELESS TRANSCEIVERS. In this paper, we have studied the architecture, the synthesis and the hardware implementation of a decimation filter designed for 6-bit data stream input, from a fourth-order sigmadelta modulator adapted for multistandard wireless receiver. The prototyped filter is based on fifthorder comb filter, one half-band filter stages and a FIR correction filter. Obtained results show that the use of carry ripple adders allows minimizing LCELL amount for comb filter implementation. For half-band and FIR correction filters, which are based on multiplying operations, single generic multiplier based architecture is the more suitable solution. PAPER 5 TITLE: A PARTIAL POLYPHASE VLSI ARCHITECTURE FOR VERY HIGH SPEED CIC DECIMATION FILTERS In this paper the partial polyphase VLSl architecture for very high speed CIC decimation filters is presented. It has following advantages: I) no recursive loop in the new architecture; 2) Facilitate high speed operation since filters can operate at much lower sampling rate mean while achieve the same performance as Hogenaucrs CIC filters; 3) Low power consumption due to computations are performed at lower sampling rate; 4) Lower complexity for VLSl implementation when the decimation ratio and filter order are high. PAPER 6 TITLE: LOW POWER AND HARDWARE EFFICIENT DECIMATION FILTER The multi-rate multi-stage three half-band FIR filters and the IIR filter used in the decimation filter structure reduce the power consumption and the hardware used for implementation. The proposed decimation filter has 61% less hardware and consumes 42% less power compared to conventional decimation filters.