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SPCE061A
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16-bit Sound Controller
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Preliminary
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology
to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of
patent or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury
to the user, without the express written approval of Sunplus.
Preliminary
SPCE061A
Table of Contents
PAGE
3. FEATURES .................................................................................................................................................................................................. 4
4. APPLICATION FIELD.................................................................................................................................................................................. 4
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5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
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6.1. CPU ..................................................................................................................................................................................................... 7
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6.2. MEMORY ............................................................................................................................................................................................... 7
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6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................... 7
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6.4. POWER SAVINGS MODE ......................................................................................................................................................................... 7
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6.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8
6.6. INTERRUPT ............................................................................................................................................................................................ 8
6.7. I/O ........................................................................................................................................................................................................ 8
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6.8. TIMER / COUNTER .................................................................................................................................................................................. 9
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6.11. SERIAL INTERFACE I/O (SIO)..............................................................................................................................................................11
6.12. UART ...............................................................................................................................................................................................11
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7.2. DC CHARACTERISTICS (VDD = 3.6V, VDDIO = 3.6V (PORTA & B), TA = 25℃) ....................................................................................... 13
7.3. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 5.5V (PORTA & B), TA = 25℃) ....................................................................................... 14
7.4. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃) ....................................................................................... 14
7.5. ADC CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ................................................................................................................................ 15
7.6. V2VREF REGULATOR CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ...................................................................................................... 15
7.7. DAC CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ................................................................................................................................ 15
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11. DISCLAIMER............................................................................................................................................................................................. 29
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12. REVISION HISTORY ................................................................................................................................................................................. 30
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speed assures the ’nSP™ is capable of handling complex digital Program Flash Operating voltage: 3.0V - 3.6V
signal processes easily and rapidly. Therefore, the SPCE061A is IO PortA & B operating voltage: 3.0V - 5.5V
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applicable to the areas of digital sound process and voice 32K-word flash memory
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recognition. The operating voltage of 3.0V through 3.6V and 2K-word working SRAM
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speed of 0.32MHz through 49.152MHz yield the SPCE061A to be Software-based audio processing
easily used in varieties of applications. The memory capacity Crystal Resonator
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includes 32K-word flash memory plus a 2K-word working SRAM. Standby mode (Clock Stop mode) for power savings,
Other features include 32 programmable multi-functional I/Os, two Max. 2.0A @ VDD = 3.6V
16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Two 16-bit timers/counters
Reset/Detection, eight channels 10-bit ADC (one channel built-in Two 10-bit DAC outputs
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MIC amplifier with auto gain controller), 10-bit DAC output and 32 general I/Os (bit programmable)
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Approx. 210 sec speech @ 2.4Kbit/per sec with SACM_S240
2. BLOCK DIAGRAM PLL feature for system clock
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ICE FLASH
u'nSP x2
ICECLK
ICESDA
and
ICE
TimerBase ADC external top reference voltage
SLEEP controller RAM INT control
RESET
VMIC 2.0V voltage regulator output, 5mA of driving capability
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VEXTREF
VCOIN CPU VADREF Serial interface I/O (SIO)
Clock 10-bit A/D AGC
X32I PLL
X32O RTC
& AGC MICOUT
MICP
Built-in microphone amplifier and AGC function
MICN
UART receiver and transmitter (full duplex)
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LVD/LVR OPI
WATCHDOG
10-bit DAC1 Output
10-bit DAC2 Output
AUD1
Low voltage reset and low voltage detection
AUD2
UART
SIO Watchdog enable (bonding option)
IOB7 (Rx) IOB10 (Tx) IOB1 (SDA) IOB0 (SCK)
ICE function for development and down load into flash memory
32 PIN GENERAL I/O PORT
Security function to protect code to be read and written.
IOA15 - 0 IOB15 - 0
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4. APPLICATION FIELD
Voice recognition products
Intelligent interactive talking toys
Advanced educational toys
Kids learning products
Kids storybook
General speech synthesizer
Long duration audio products
Recording / playback products
5. SIGNAL DESCRIPTIONS
Mnemonic PIN No. Type Description
IOA [15:8] 46 - 39 I/O IOA [15:8]: bi-directional I/O ports
IOA [7:0] 34 - 27 I/O IOA [7:0] can be software programmed to wakeup I/O pins
IOA [6:0] can be optioned as ADC Line-in input
IOB [15:11] 50 - 54 I/O IOB [15:11]: bi-directional I/O ports
IOB 10 57 I/O IOB10 can also be selected as UART Transmitter (Tx).
IOB 9 58 I/O IOB9 can also be Multi-duty cycle output of TimerB (BPWMO).
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IOB 8 59 I/O IOB8 can also be Multi-duty cycle output of TimerA (APWMO).
IOB 7 60 I/O IOB7 can also be selected as UART receiver (Rx).
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IOB 6 61 I/O IOB6 is a bi-directional I/O ports.
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IOB 5 62 I/O IOB5 can also be selected as feedback signal with EXT2.
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IOB 4 63 I/O IOB4 can also be selected as feedback signal with EXT1.
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IOB 3 64 I/O IOB3 can also be selected as an external interrupt input pin (EXT2)(Negative-edge Triggered).
IOB 2
IOB 1
IOB 0
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65
66
67
I/O
I/O
I/O
IOB2 can also be selected as an external interrupt input pin (EXT1)(Negative-edge Triggered).
IOB1 can also be selected as a serial interface data. (SDA)
IOB0 can also be selected as a serial interface clock (SCK)
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DAC1 12 O Audio DAC1 output
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reference voltage)
st
MICOUT 18 O Microphone 1 amplifier output
nd
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WDGOPT
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6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
The SPCE061A is equipped with a 16-bit ’nSP™, the newest Moreover, a high performance hardware multiplier with the
16-bit microprocessor by SUNPLUS and pronounced as capability of FIR filter is also built in to reduce the software
micro-n-SP. Eight registers are involved in ’nSP™: R1 - R4 multiplication loading.
(General-purpose registers), PC (Program Counter), SP (Stack
Pointer), Base Pointer (BP) and SR (Segment Register). The 6.2. Memory
interrupts include three FIQs (Fast Interrupt Request) and eight 6.2.1. SRAM
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IRQs (Interrupt Request), plus one software-interrupt, BREAK.
The amount of SRAM is 2K-word (including Stack), ranged from
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$0000 through $07FF with access speed of two CPU clock cycles.
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Phase Lock Loop
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FOSC Fosc/n CPU Clock
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32768Hz X'tal (PLL)
System Clock generator PLL OUT n:1,2,4,8,16,32,64
24.576MHz(default) (Default : Fosc/8)
20.48MHz
32.768MHz
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40.96MHz
49.152MHz
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b7 b6 b5 b2 b1 b0
b7,b6,b5 of P_SystemClock(W )($7013H) of P_SystemClock(W )($7013H)
System clock frequency selection
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Flash memory ($008000 ~ $00FFFF) is a high-speed memory with wake CPU up whenever RTC occurs. Since the RTC is
access speed of two CPU clock cycles. FLASH erase and generated each 0.5 seconds, time can be traced by the numbers
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program functions must be used in IDE tools. of RTC occurrence. In addition, SPCE061A supports 32768Hz
oscillator in strong mode and auto_weak mode. In strong mode,
32768Hz OSC always runs at the highest power consumption. In
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6.5.2. Low voltage reset
4096Hz IRQ4_4KHz Low
In addition to the LVD, the SPCE061A has another important
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2048Hz IRQ4_2KHZ Low
function, Low Voltage Reset (LVR). With the LVR function, a 1024Hz IRQ4_1KHz Low
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reset signal is generated to reset system when the operating 4Hz IRQ5_4Hz Low
voltage drops below 2.3V for 4 consecutive clock cycles. Without
2Hz IRQ5_2Hz Low
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LVR, the CPU becomes unstable and malfunction when the
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Time-base 1 IRQ6_TMB1 Low
operating voltage drops below 2.3V. The LVR will reset all
Time-base 2 IRQ6_TMB2 Low
functions to the initial operational (stable) states when the voltage
UART (TxRDY or RxRDY) UART IRQ Low
drops below 2.3V. A LVR timing diagram is given as follows:
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6.7. I/O
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Fosc
Two I/O ports are built in SPCE061A, PortA and PortB. The
VDD PortA is an ordinary I/O with programmable wakeup capability. In
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2.3V
addition to the regular IO function, the PortB can also perform
Tw
some special functions in certain pins. Suppose operating
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Tvdd
operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad
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RESET
Tw=Fosc x 4 cycle Treset is capable of operating from 0V through VDDIO. However IOB13
Tvdd > Tw and IOB14 are recommended to operate <=3.6V during standby
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6.6. Interrupt
Buffer(R)
The SPCE061A has 14 interrupt sources, grouped into two types,
Port_Data(W)
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
Register
priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt Port_Buffer(W) pull high
Pin pad
while IRQ is the low-priority one. An IRQ can be interrupted by a
Port_DIR(R/W) Control
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any logic
pull low
other interrupt sources.
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Port_ATTR(R/W)
Data(R)
Although data can be written into the same register through and enable the key wakeup function. Wakeup is triggered when
Port_Data and Port_Buffer, they can be read from different places, the PortA state is different from at the time latched. In addition to
Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port. an ordinary I/O port, PortB carries some special functions. A
To activate key wakeup function, latch data on PORT_IOA_Latch summary of PortB special functions is listed as follows:
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IOB1 SDA Serial interface data Refer to see SIO section
IOB2 EXT1 External interrupt source 1(Negative-edge Triggered) IOB2 set as input mode
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Feedback Works with IOB4 by adding a RC circuit between IOB2 set as inverted output
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Output1 them to get an OSC to EXT1 interrupt
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IOB3 EXT2 External interrupt source 2(Negative-edge Triggered) IOB3 set as input mode
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Feedback Works with IOB5 by adding a RC circuit between IOB3 set as inverted output
IOB4
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Output2
Feedback Input1
Feedback Input2
them to get an OSC to EXT2 interrupt
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IOB7 Rx UART Receiver Refer to see UART section
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Refer to the above table, the configuration of IOB2, IOB3, IOB4, Initially, write a value of N into a timer and select a desired clock
and IOB5 involves feedback function in which an OSC frequency source, timer will start counting from N, N+1, N+2, ... through
can be obtained from EXT1 (EXT2) by simply adding a RC circuit FFFF. An INT (TimerA/TimerB) signal is generated at the next
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between IOB2 (IOB3) and IOB4 (IOB5). clock after reaching “FFFF” and the INT signal is transmitted to
INT controller for further processing. At the same time, N will be
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6.8. Timer / Counter reloaded into timer and start all over again. The clock source A is
The SPCE061A provides two 16-bit timers/counters, TimerA and a high frequency source and clock source B is a low frequency
TimerB. The TimerA is called a universal counter. TimerB is a source. The combination of clock source A and B provides a
general-purpose counter. The clock source of TimerA comes variety of speeds to TimerA. A “1” represents pass signal and not
from the combination of clock source A and clock source B. In gating. In contrast, “0” indicates deactivating timer. The EXT1
TimerB, the clock source is given from source C. When timer and EXT2 are the external clock sources. Moreover, counter can
generate time-out signal for input clock source to a four bits (16
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TimerA_Timeout
Tapwmo
Tduty
APWMO
Generally speaking, the clock source A and C are fast clock 6.9.2. Watchdog
sources and source B comes from RTC system (32768Hz).
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The purpose of watchdog is to monitor if the system operates
Therefore, clock source B can be utilized as a precise counter for normally. Within a certain period, watchdog must be cleared. If
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time counting, e.g., the 2Hz clock can be used for real time watchdog is not cleared, CPU assumes the program has been
counting.
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running in an abnormal condition. As a result, the CPU will reset
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the system to the initial state and start running the program all
6.8.1. Timebase over again. The watchdog function can be removed by bonding
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Timebase, generated by 32768Hz, is a combination of frequency option. In SPCE061A, the clear period is 0.75 seconds. If
selections. The outputs of timebase block are named to TMB1 watchdog is cleared within each 0.75 seconds, the system will not
and TMB2. TMB1 is frequency for TimerA (Clock source B). be reset. To clear watchdog, simply write “0bxxxx xxxx xxxx
The TMB1 and TMB2 are the sources for Interrupt (IRQ6). xx01” to Port_Watchdog_Clear(W). The content written to
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Furthermore, timebases generates additional 2Hz to 4096Hz Port_Watchdog_Clear(W) for watchdog clearance must be exactly
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interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC). the same as the one illustrated above (0bxxxx xxxx xxxx xx01).
Other values given to the Port_Watchdog_Clear(W) for watchdog
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TMB2 TMB1 clearance may end up with system reset. The watchdog function
128Hz 8Hz remains enabled during standby mode if the 32768Hz is turned
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512Hz 32Hz
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signal to turn the system clock (PLL) on. The IRQ is able to choose the external or internal (=AVDD) top reference
signal makes CPU to complete the wakeup process voltage. If constant voltage source is unavailable, SPCE061A
and initialization. The key wakeup and interrupt offers a constant voltage 2.0V with 5.0mA driving ability with a
sources (IRQ1 - IRQ6) can be used for wakeup capacitor connected.
sources.
The SPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving
current for audio outputs, DAC1 and DAC2.
SCK
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1st write P_SIO_Data (W), $701AH STOP
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2nd write P_SIO_Data (W), $701AH
READ MODE
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read control bit = 1
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SCK
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SDA SDA Ax+1 Ax Ax-1 A0 Dx+1 Dx D0 Dx+1 Dx D0
6.12. UART
UART block provides a full-duplex standard interface that Rx and Tx of UART are shared with IOB7 and IOB10. When
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facilitates the communication with other devices. With this SPCE061A receives and/or transmits a frame of data, the b7
interface, SPCE can transmit and receive simultaneously. The (RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be
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maximum baud-rate can be up to 115200bps. This function can set to “1” and the UART IRQ is activated at the same time.
be accomplished by using PortB and Interrupt (UART IRQ). The
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can be enabled/disable;
also even/odd check
WDGOPT is the optional pin for watchdog by bonding option. The fuse to disable IDE function, where PFUSE supplies 5.0V and
shape looks as the figure given below. When watchdog is selected, PVIN connects to ground (0V) about one second. After all, the
WDGOPT is floating. If watchdog is not selected, WDGOPT is flash memory can no longer be read or written.
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that when watchdog is not selected, it is easy to make the
connection between VDD and WDGOPT.
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VDD
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W DGOPT
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7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
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Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
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7.2. DC Characteristics (VDD = 3.6V, VDDIO = 3.6V (PortA & B), TA = 25℃)
Limit
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Characteristics Symbol Unit Test Condition
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Min. Typ. Max.
Operating Voltage VDD 3.0 3.3 3.6 V
FOSC = 49.152MHz,
Operating Current IOP - - 33 mA
AD, DAC disable, no load
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2.0 Disable 32KHz crystal
Standby Current ISTB - - A
5.0 Enable 32Khz, Disable PLL (Fosc)
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Output DAC current -2.0 2.0mA mode For one channel
IAUD - - mA
(AUD1, AUD2) -3.0 3.0mA mode DAC
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RPH - - 210 K
(PA15 :0, PB15 :0) VIN = VSS
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7.3. DC Characteristics (VDD = 3.3V, VDDIO = 5.5V (PortA & B), TA = 25℃)
Limit
Characteristics Symbol Unit Test Condition
Min. Typ. Max.
Operating Voltage VDD 3.0 3.3 3.6 V
FOSC = 49.152MHz,
Operating Current IOP - 26 - mA
AD, DAC disable, no loading
Disable 32KHz crystal
2.0
When IOB13, IOB14 < = 3.6V
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Standby Current ISTB - - A
Enable 32Khz, Disable PLL (Fosc)
5.0
When IOB13, IOB14 < = 3.6V
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Input High Level VIH - 0.7VDDIO - V
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Input Low Level VIL - 0.3VDDIO - V
Output DAC current -2.0 2.0mA mode For one channel
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IAUD - - mA
(AUD1, AUD2) DAC
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-3.0 3.0mA mode
Output High Current IOH - -5.0 - mA VOH = 4.0V
Output Low Current IOL - 12 - mA VOL = 1.0V
Input Pull-Low Resister VDDIO = 5.5V
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RPL - 110 - K
(PA15 :0, PB15 :0) VIN = VDD
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7.4. DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
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Limit
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Unit
Characteristics Symbol Unit
Min. Typ. Max.
ADC Power Dissipation for LINE_IN IADC - 1.0 - mA
ADC Power Dissipation For MIC_IN - 1.9 - mA
ADC LINE_IN Input Voltage Range from
VINL (Note 1) VSS - 0.3 - VDD + 0.3 V
IOA[6:0]
ADC Microphone Input Voltage Range VINM VSS - 0.3 - VDD + 0.3 V
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External ADC Top Voltage VEXTREF (Note 2) 2.0 - VDD + 0.3 V
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Resolution of ADC RESO - - 10 bits
Signal-to-Noise Plus Distortion of ADC from
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SINAD (Note 4) - 56 - dB
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Line In
Effective Number of Bit ENOB (Note 5) 9.0 - bits
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Integral Non-Linearity of ADC INL - ±4.0 - LSB (Note 3)
Differential Non-Linearity of ADC DNL (Note 6) - ±0.5 - LSB
AD Conversion Rate FCONV - - Fcpu/512 Hz
Microphone Amplifier Gain (Note 7) A MIC - - 42 dB
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Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (VDD+0.3V)
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Note4: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/512 = 95KHz, Fin = 1.0KHz Sine waves at VDD = 3.0V from the IOA
[6:0] input.
Note5: ENOB = (SINAD-1.76)/6.02.
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Note7: The microphone amplifier maximum gain = 15 * (60K / (1.5K + REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is
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Limit
Characteristics Symbol Unit Test Condition
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Unit
Characteristics Symbol Unit
Min. Typ. Max.
DAC resolution RESO - - 10 bit
Signal to Noise Ratio of DAC SNR - 54 - dB
Sample Rate FS - - 100K Hz
Output Voltage Accuracy range VDAC 0 - VDD/2 V
Note1: The DAC output voltage in accuracy range have max 10 bits resolution.
7.8. Pull High Resister and VDDIO 7.11. I/O Output Low Current IOL and VOL
500 25
400 20
RPH(Kohms)
300
IOL (mA)
15
200
10
100
0 5
2.4 3.4 4.4 0
VDDIO(V) 0.5 1.5 2.5 3.5 4.5
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VOL (V)
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7.9. I/O Output High Current IOH and VOH
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7.12. DAC output current vs. VDD (2mA mode with
500hm resistor)
15
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10
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IOH (mA)
2.500
5
2.000
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IDAC(mA)
0
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0.500
0.000
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0 4.000
2.4 2.9 3.4 3.9 4.4 4.9
3.000
IDAC(mA)
VDDIO(V)
2.000
1.000
0.000
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6 1K 5.1K
SPCE061A OPI
0.1
U C 5000p
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IOA[15:7] IOA[15:7]
AGC
IOB[15:0] IOB[15:0] 4.7 470K
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100 0.1
VDDIO
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VADREF
VSSIO
VDDH(5V) 0.1 47
8. APPLICATION CIRCUITS
AVDD (3.3V)
AVDD VEXTREF
8.1. Application Circuit - (1) rS S
X32O X32I
VCOIN
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8 7 0.1 RESET 3.3K 0.1
100 0.1
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0.22
5 1K
1 DAC1 VMIC
Speaker1 2
3 4 0.1 1K
3K 220
6 1K
y ia 0.22
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MICP
0.1
VDDH(3.6V) MIC
0.22
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SPY0030A MICN
8 7
3K
100 0.1 10K
10K
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0.22
5
1 DAC2
Speaker2 2 0.22
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3 4 0.1 MICOUT
18
1K
6 1K
SPCE061A 5.1K
OPI
0.1
U C 5000p
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IOB[15:0]
IOA[15:7]
IOB[15:0]
AGC
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4.7 470K
VDDH(3.6V)
VDDIO
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100 0.1
VADREF
VSSIO
AVDD (3.6V) 0.1 47
AVDD
8.2. Application Circuit - (2)
VEXTREF
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DAC2
0.22
U n on MICOUT
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200~2K SPCE061A 5.1K
OPI
U C IOA[15:7] IOA[15:7] 5000p
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AGC
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100 0.1
VDDIO
4.7 470K
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VADREF
VDDH(5V) VSSIO
AVDD (3.3V) 0.1 47
AVDD
100 0.1
8.3. Application Circuit - (3)
VEXTREF
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2 3
DAC2
MICOUT
0.22
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200~2K SPCE061A 5.1K
OPI
U C IOA[15:7] IOA[15:7]
5000p
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AGC
IOB[15:0] IOB[15:0]
4.7 470K
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VDDH(3.6V)
VDDIO
100 0.1 VADREF
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AVDD (3.6V)
AVDD
VEXTREF
100 0.1
8.4. Application Circuit - (4)
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X32O X32I
VCCIN
3300p
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0.1 RESET 3.3K 0.1
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VMIC
Speaker1
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VDDH(5V)
0.1
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200~2K MICN
Note:
Case(1): UseAVDD(internal)as AD reference
voltageby settingP_ADC_CTRL($7015)
Speaker2
b7 = 0
MICOUT VEXTREF
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DAC2
V2VREF
0.1
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Note:
200~2K SPCE061A1 OPI
Case(2): V2VREF as AD topreferencevoltageby
settingP_ADC_CTRL(#7015)
U CIOA[15:7] IOA[15:7] AGC
b7 = 1, b8 = 0
VEXTREF
us s IOB[15:0] IOB[15:0] V2VREF
100F
pl plu
VADREF 0.1F
VDDH(5V)
VDDIO 0.1 Note:
Case(3): Useexternal signalas AD topreference
100 0.1
un un
voltageby settingP_ADC_CTRL($7015)
Note b7 = 1, b8 = 1.
VSSIO (detailsee theprogrammingguide)
VDDH(5V) AVDD(3.3V) VEXTREF Input external
8.5. Application Circuit - (5)
VDD
VSS
IOA[6:0] IOA[6:0]
(7-channel LINE_IN)
Fo
SPCE061A Application Circuit (LINE_IN and with BJT amplifier, for 3-battery use only)
Preliminary
X32O X32I
VCOIN
3300p
0.1
og RESET 3.3K 0.1
Pr l
VMIC
Speaker1
DAC1
VDDH(3.6V)
y ia MICP
200~2K
nl ity t 0.1
Note:
O ers den
MICN Case(1): Use AVDD(internal) as AD top reference
voltage by setting P_ADC_CTRL($7015)
Speaker2 b7 = 0
VEXTREF
MICOUT
se iv fi
DAC2
V2VREF
0.1
U n on
OPI Case(2): Use V2VREF as AD top reference
22
200~2K
voltage by setting P_ADC_CTRL($7015)
SPCE061A b7 = 1, b8 = 0
U
IOA[15:7] IOA[15:7] AGC VEXTREF
/
C V2VREF
us s
IOB[15:0] IOB[15:0]
VADREF 0.1F
100F
pl plu
VDDH(3.6V)
VDDIO 0.1 Case(3): Use external signal as AD top reference
voltage by setting P_ADC_CTRL($7015)
100 0.1 b7 =1, b8 = 1.
Note (detail see the programming guide)
un un
AVDD (3.6V)
VSSIO
AVDD
VEXTREF
VEXTREF
V2VREF
23
200~2K
SPCE061A
IOA[15:0]
U C IOA[15:0] AGC
Note : Minimal set of pin required for
spce061a downloading : 6 pin
us s
IOB[15:0] IOB[15:0] VADREF
SUNPLUS PROBE
0.1 PROBE Pin 5: VDD
VDDH(3.6V)
pl plu
100 0.1
VDDIO
VSSIO
VDD
S/N : PROBE-T-33
Pin 7: ICE
Pin 8: ICESCK
Pin 9: ICESDA
Pin 10: VSS
un un
AVDD (3.6V)
100 0.1
AVDD
ICE
1 I/O
Pin 56: VDDIO
8.7. Application Circuit - (7)
ICESDA
rS S
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
0.045*450 0.010*450
D 1
0.180 MAX.
m
0.020 MIN.
ra
Pr l
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nl ity t
O ers den
1 1
F G
E2±0.020
E1±0.003
E±0.005
E3
se iv fi
U n on
C
y
us s
0.
03
5
pl plu
U
0.070 0.070
1 E
H 2 DATUM PLANE
un un
D1±0.003
Symbol Lead Count
rS S
D±0.005 D 1.190
D1 1.153
0.026 ~ 0.032TYP. 70 TYP.
D2 1.110
D3 1.000
c
Fo
E 1.190
E1 1.153
E2 1.110
SEATING PLANE
0.050TYP. E3 1.000
0.004
D3
D2±0.020
c 0.008
1 IOB4 22 DAC2
2 IOB3 23 V2VREF
3 IOB2 24 AVSS
4 IOB1 25 AGC
5 IOB0 26 OPI
6 RESET 27 MICOUT
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7 VDD 28 MICN
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8 VCOIN 29 PFUSE
9 VSS 30 N/C
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10 N/C 31 N/C
11 N/C 32 N/C
nl ity t
O ers den
12 X32O 33 MICP
13 X32I 34 VADREF
14 TEST 35 VEXTREF
15 VDD 36 AVDD
se iv fi
16 ICE 37 VMIC
U n on
17 ICECLK 38 VSS
18 ICESDA 39 N/C
C
y
19 VSS 40 N/C
20 PVIN 41 IOA0
us s
21 DAC1 42 IOA1
pl plu
U
43 IOA2 64 IOB15
44 IOA3 65 IOB14
45 IOA4 66 IOB13
un un
46 IOA5 67 IOB12
47 IOA6 68 IOB11
rS S
48 IOA7 69 N/C
49 VSSIO 70 N/C
50 VSSIO 71 N/C
51 VDDIO 72 N/C
52 VDDIO 73 N/C
53 IOA8 74 N/C
Fo
54 IOA9 75 VDDIO
55 IOA10 76 IOB10
56 IOA11 77 IOB9
57 IOA12 78 IOB8
58 IOA13 79 IOB7
59 IOA14 80 IOB6
60 IOA15 81 IOB5
61 N/C 82 N/C
62 VSSIO 83 N/C
63 SLEEP 84 N/C
9.2.2. LQFP 80
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Pr l
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nl ity t
O ers den
se iv fi
U n on
C
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us s
pl plu
Dimension in inch
U
Symbol
Min. Typ. Max.
A - - 0.063
un un
A1 0.002 - 0.006
A2 0.053 0.055 0.057
rS S
E 0.551 BSC
E1 0.472 BSC
e 0.020 BSC
L 0.018 0.024 0.030
L1 0.039 REF
R1 0.003 - -
R2 0.003 - 0.008
S 0.008 - -
0 0 0
θ 0 3.5 7
0
θ1 0 - -
0 0 0
θ2 11 12 13
0 0 0
θ3 11 12 13
1 X32O 21 MICP
2 X32I 22 VADREF
3 TEST 23 VEXTREF
4 N/C 24 AVDD
5 VDD 25 VMIC
6 N/C 26 N/C
m
7 ICE 27 VSS
8 ICECLK 28 IOA0
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9 ICESDA 29 IOA1
Pr l
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og
10 VSS 30 IOA2
11 PVIN 31 IOA3
nl ity t
O ers den
12 DAC1 32 IOA4
13 DAC2 33 IOA5
14 V2VREF 34 IOA6
15 AVSS 35 IOA7
se iv fi
16 AGC 36 VSSIO
U n on
17 OPI 37 VSSIO
18 MICOUT 38 VDDIO
C
y
19 MICN 39 VDDIO
20 PFUSE 40 IOA8
us s
41 N/C 61 N/C
pl plu
42 N/C 62 N/C
U
43 IOA9 63 IN/C
44 IOA10 64 VDDIO
un un
45 IOA11 65 IOB10
46 IOA12 66 IOB9
rS S
47 IOA13 67 IOB8
48 IOA14 68 IOB7
49 IOA15 69 IOB6
50 N/C 70 IOB5
51 N/C 71 IOB4
52 VSSIO 72 IOB3
Fo
53 N/C 73 IOB2
54 SLEEP 74 IOB1
55 IOB15 75 IOB0
56 IOB14 76 RESET
57 IOB13 77 N/C
58 IOB12 78 VDD
59 IOB11 79 VCOIN
60 NC 80 VSS
m
ra
10. TABLE OF SPCE061/060/040 COMPARISON
Pr l
The information in this table is the different from SPCE061/060/040.
ia
og
Item SPCE040A SPCE060A SPCE061A
nl ity t
Working Voltage 3.0V ~ 3.6V @ 49.152MHz 3.0V ~ 3.6V
IO Working Voltage
O ers den 2.4V ~ 3.6V @ 40.96MHz, 32.768MHz,
24.576MHz, 20.48MHz
2.4V ~ 5.5V 3.0V ~ 5.5V
se iv fi
Memory size 24K Words ROM 32K Words ROM 32K Words Flash Memory
U n on
y
IOB13, IOB14 have the voltage No Yes
limitation smaller than 3.6V
us s
Pin 7 in LQFP80 package NC (ref LQFP80 package) ICE, the ICE Enable (ref LQFP80 package)
pl plu
U
Pin 8 in LQFP80 package Ground reference for I/O and logic pins (Vss) ICECLK, the ICE serial interface clock. 100K
(ref LQFP80 package) pull low resistor is necessary to prevent current
un un
leakage.
(ref LQFP80 package)
Pin 9 in LQFP80 package NC (ref LQFP80 package) ICESDA, the ICE serial interface data
rS S
Pin20,11 in LQFP80 package NC (ref LQFP80 package) NC in normal mode, for security using (ref.
(Pfuse, Pvin) SPCE061A datasheet)
32768 Stable time* Faster than SPCE061A —
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11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
m
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
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illustrated in this document are for reference purposes only.
Pr l
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nl ity t
O ers den
se iv fi
U n on
C
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us s
pl plu
U
un un
rS S
Fo
m
FEB. 12, 2004 0.6 Correct LVR timing diagram: from 2.2V to 2.3V in section 6.5.2 8
ra
JUN. 11, 2003 0.4 1 Correct Standby current condition 2A @ VDD = 3.6V 1
Pr l
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2 Correct “6.5.1 Low Voltage Detection (LVD) “ 8
nl ity t
3 Add “9.1 LQFP 80 and QPF84 package” 24 - 28
O ers den
0.3 1. Correct ”1. General Description “.
6
se iv fi
4. Correct “6.5.1 Low Voltage Detection (LVD) “ 8
U n on
y
7. Delete “7.5 DC Characteristics (VDD = 2.7V, VDDIO = 2.7V (PORTA&B) “ 13
NOV. 07. 2002 0.2 1. Add VDD = 3.6 / 3.3 / 2.7 /2.4 V Standby Current “ 32Khz Enable, PLL Disable(Fosc) ”. 12,13,14