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Ind. Co., Ltd. for their continuous encouragement and providing the experimental devices used in this paper. REFERENCES
[ I ] C. F. Hawkins, I. M. Soden, E. 1. Cole, Jr., and E. S. Snyder, The use of light emission in failure analysis of CMOS ICs, Int. Symp. for Trsting and Failure Analysis. pp. 5 5 4 6 , 1990. [2] N. Tsutsu, Y. Uraoka, T. Morii, and K. Tsuji, Life time evaluation of MOSFET in ULSIs using photon emission method, Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 94-99, Mar. 1992. 131 T. Ohzone and H. Iwata, Photoemission characteristics of reversebreakdown ii+-diodes with LOCOS- and trench-isolation, Proc. IEEE I n t . Conf. on Microelectronic Test Structures, pp. 177-182, Mar. 1993. [4] G. Fuse, H. Ogawa, K. Tateiwa, 1. Nakao, S. Odanaka, M. Fukumoto, H.

the parameters may be difficult because it involves the nonlinear optimization and the minima of the objective functions may not be located within reasonable number of iterations. On the other hand, the BSIM [6], [7] used a lot of redundant parameters and some of these parameters even have no any physical justification and unfortunately large errors were still found (71. The latest version of BSIM has more stronger physical basis and has several improvements [8]. However, the physical functional forms are still very complicated. In this work, we aim at the development of a simple short-channel model that is suitable for device analysis and circuit simulation. The model is developed by incorporation of some secondary effects into Pao-Sahs equation. It is a new attempt although similar treatment may be found in characterizing other parameters. A completely new form

, L

Conf. on Microelectronic Test Structures, pp. 34-38, Mar. 1992. 161 T. Ohzone and H. Iwata, Channel-width measurements of LOCOS- and trench-isolated n-MOSFETs by photoemission, Proc. IEEE Int. Con5 on Microelectronic Test Structures, pp. 269-274, Mar. 1993.

computation efficiency.
11. DEVICE EQUATION FORMULATION

According to Pao and Sah [I], current-voltage (I-V) characterthe istics for long-channel MOS transistor can be modeled by

A New Approach to Current-VoltageCharacteristics

Formation for Short-Channel MOSFETs

H. Wong

where C,,,, S i n , T i ) , and 12; are the oxide capacitance per unit area, threshold voltage, drain-to-source voltage and gate-to-source voltage, respectively. T I 7 and L are the effective channel width and channel length, respectively. The channel mobility p in (1) can be modelled by the empirical equation given below [9],

Abstract-A new approach to the current-voltage (I-V) characteristics formulation for short-channel MOSFETs by incorporating the channel length modulation, mobility degradation, drain induced harrier lowering, and threshold voltage variation into Pao4ahs equation is presented. Results show that the calculated I-V characteristics agree well with the experimental ones for devices with effective channel length in the range of 0 4 . 4 20 irm. Compared with the existing models, the model has the advantages of less number of model parameters and simpler form of the current-voltage relationship.
N

where 110 is the bulk mobility of substrate, E,,,, is the saturation electric field, and 0 is an empirical parameter. At saturation region, the I-V characteristics of MOSFET is given by (3) Supposing that the saturated I-V characteristics for the short-channel MOS transistors (IDS) not divert greatly from Pao-Sahs equation, do IDScan be approximated by

I. INTRODUCTION
As the classical device equation based on the gradual channel approximation [1]-[2] is no longer suitable for submicron MOSFETs, several complicated yet more precise models by considering the charge sharing effects in the two dimensional structure [3] or based on solving the two-dimensional Poissons equation [4], were developed. However, the complicated equation forms prohibit themselves be used for device evaluation and circuit simulation purposes, not only due to the computational overhead but also because of the difficulties in determining the model parameters with the automatic parameter extraction facilities. Then semi-empirical models were developed [SI-[7]. The accuracy of these models was improved by adding a number of empirical parameters in addition to the physical ones. However, these models are in term of some nonlinear functions and involve sophisticated measurements for extracting the model parameters [SI. Determination of the values for some of
Manuscript received May 7, 1994; revised July 20, 1994. The review of this brief was arranged by Associate Editor K. Tada. The author is with the Department of Electronic Engineering, City Polytechnic of Hong Kong, Kowloon, Hong Kong. IEEE Log Number 9405946.

IDS= IDSO 6 L . -+sr;.aIuso dL

I ID SO

dIDS0 + 611 . dp .

(4)

The change of effective channel length, be approximated by [IO],

a i , due to drain bias can

(5)

6L = --7(

J0D

+ r b - Ih,*t - 6 )

where N B , E.;,, eo and y are the substrate doping concentration, dielectric constant of silicon, permittivity in vacuum, and electron charge, respectively. O D is an empirical parameter [lo]. n~ is the free charge density in the depletion region. The minus sign in ( 5 ) represents the reduction of channel length. By equating the drift current in the depletion region to 1 ~ 5 0 ) I D can be approximated by ,

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 12, DECEMBER 1994

248 1

where TGT = Vi: - Tko, and T~ is the junction depth of drain junction. Here we have assumed that the channel thickness is much smaller than the junction depth and averaged cross-section area for the current flow will be Tt7xJ/2. The saturation drain voltage in (5) is given by [ 111,

7-

6-

z
-5

On the other hand, the threshold voltage is also sensitive to the drain bias. Considering the effect of drain induced barrier lowering [12], we have

14-

s321 0
05

where O B is the surface-inversion potential of silicon. Further considering the channel length modulation effect, we get, (9) And the change of mobility is

15

2 25 3 DRAIN VOLTAGE (V)

35

45

(a)

Substituting for IDS,

(9,(9) and (10) into (4), we have the final expression

+L b - LTDd (11) 2 + (0 + 2/EsatL)lcT F = 2fS10(208 + Lb) . C,,LT~;T (1+ % l k T ) ( I+ 2l?,T/&atL) 1 + 1 + LD/&L

x 1
L ( & D

[+ ?

&)I

It is noted that only two additional parameters, 2 and 00,are introduced into the equation for saturation current that is given in ( 1 1). Other parameters are already appeared in the ohmic region I-V characteristics. In addition, it can be readily shown that IDS (1 1) in will reduce to IDSO for long-channel devices and the saturation drain current, IDS,equal to the linear region drain current at T b = 1Dsat. is Furthermore, the drain conductance in the transition between the linear and saturation regions is continuous by considering the bias dependence of the free charge density in the depletion region.
111. RESULTS AND DISCUSSION

Fig. 1. Comparison between experimental and calculated current-voltage characteristics for n-channel MOSFET with effective channel length of (a) 0.44 pm and (b) 1.04 pm. The bottom curve in each plot corresponds to t, = 1 V and step for I & is 1 V. Same set of model parameters which were obtained from parameter extraction was used in the theoretical plots for the devices.

error in the transition region of the drain current although large error may be found in drain conductance in this region [lo]. As shown in In order to verify the validity of the new analytical model, the Fig. 1, the calculated results agree well with the experimental data calculated device characteristics are compared with the experimental bias for the transistors. Neither in the whole range of T i : and data. Fig. 1 plots the experimental (continuous lines) and calculated discontinuity nor excess error are found at the transition between (open circles) I-V characteristics for n-channel MOS transistors with triode and the pentode regions. The maximum error between the effective channel lengths of 0.44 and 1.04 pm which were fabricated using the standard polysilicon gate technology. For theoretical charac- experimental and theoretical results is about 5% for 0.44 pm long teristics, equation (1) was used for ohmic region and (11) was used device and less than 3% for devices with channel length in the range for saturation region plots. The parameters used in the theoretical of 1 20 pm. Hence, this model is valid for devices with channel plots, except for which depends on the channel length, substrate length down to 0.44 pm. However, further experimental validation is doping, and junction depth, are extracted from the I-V curves in the needed for the applicability of this model to shorter devices. Other ohmic region of the device with effective channel length of 1.04 pm. effects, e.g., punchthrough, and subthreshold conduction, and velocity The values for the parameters 0, f.at, are 0.15 V-I, 1 . 0 5 ~ 1 0 ~overshoot [13], should also be considered in deep submicron devices. po, V/cm, and 513 cm2/Vs, respectively. C,, and L Y are 0.1 pF/cm2 ~ IV. CONCLUSION and 2 x l O I 5 cmP3, respectively, which agree well with the results A simple short-channel MOSFET model has been developed by from CI measurement. For the sake of simplicity, O D is assumed to be zero in the curve fittings. This treatment only introduces a small incorporating the secondary effects into Pao-Sah equation. The

-,

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model shows good agreement with the experimental data. Most of the phenomena observed in short-channel devices, including finite conductance at saturation or channel length modulation effect, drain induced threshold shift, mobility saturation, were considered. The advantage of the newly developed model is its applicability to short channel devices without using sophisticated mathematical treatment and complicated function or a large number of empirical parameters. This model can be used for both device evaluation and circuit simulation. ACKNOWLEDGMENT The devices used in this work were fabricated in the Microelectronic Institute of Tsinghua University, China. REFERENCES
H. C. Pa0 and C. T. Sah, Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors, Solid-state Electron., vol. 9, pp. 927-937, 1966. f L. D. Yau, A simple theory to predict the threshold voltage o shortchannel IGFETs, Solid-Slate Electron., vol. 17, pp. 1059-1063, 1974. L. A. Akers and J. J. Sanchez, Threshold voltage models of short, narrow and small geometry MOSFETs: A review, Solid-Srate Electron., vol. 25, p. 621, 1982. P. S. Lin and C. Y. Wu, A new approach to analytically solving the two-dimensional Poissons equation and its application in short channel MOSFET modeling, IEEE Trans. Electron Devices, vol. ED-34, pp. 1947-1956, 1987. C. K. Park. C. Y. Lee, K. Lee, B. J. Moon, Y.H. Byun and M. Shur, A unified current-voltage model for long-channel nMOSFETs, IEEE Trans. Electron Devices, Vol. ED-38, pp. 399406, 1991. B. J. Sheu, D. L. Scharfetter, P. K. KO, and M. Jeng, BSIM: Berkeley short-channel IGFET model for MOS transistors, IEEE J. Solid-Stare Circuits, vol. SC-22, pp. 558-566, 1987. M. C. Jeng, P. M. Lee, M. M. Kuo, P. K. KO, and C. Hu, Theory, algorithms, and users guide for BSIM and SCALP, Univ. Califomia, Berkeley, memo UCB/ERL M87/35, 1987. J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. KO, and C. Hu, Robust physical and predictive model for deep-submicrometer MOS circuit simulation, Proc. IEEE 1993 Custom Integrated Circuits Con&, San Diego, 1993, p. 14.2.1. H. Q. Su, C. C. Wei, and T. P. Ma, Mobility degradation in very thin oxide p-channel MOSFETs, lEEE Trans. Electron Devices, vol. ED-32, p. 559, 1985. Y. P. Tsividis, Operation and Modeling of rhe MOS Transistor. New York: McGraw-Hill, 1987, p. 172. C. G. Sodini, P. K. KO, and J. L. Moll, The effect of high fields on MOS device and circuit performance, IEEE Trans. Electron Devices, vol. ED-31, pp. 1386-1393, 1984. T. Skotnichi and W. Marciniak, A new approach to threshold voltage modeling of MOSFETs, Solid-state Electron., vol. 29, pp. 1115-1 128, 1986. K . Sonoda, K . Taniguchi, and C. Hamaguchi, Analytical device model for submicrometer MOSFETs. IEEE Trans. Electron Devices, vol. 38, pp. 2662-2668, 1991.

An Orthogonal-Transfer CCD Imager

B. E. Burke, R. K. Reich, E. D. Savoye, and J. L. Tonry

Abstract-We describe a new two-dimensional CCD imager structure capable of transferring charge packets in all four directions, as well as experimental results on a 64 x 64-pixel prototype device. Applications include astronomical imaging where the charge shifting can be made to track the tip-tilt correction for atmospheric turbulence and thereby improve image resolution.

Conventional CCD imagers, though two-dimensional (2D) in structure, are capable of transferring a charge-packet array along a single dimension at most. A CCD which can transfer charge in all four directions could find use in imaging applications where the charge would be shifted to track a moving image and thereby eliminate blur. SCquin proposed a structure capable of true 2D transfer which had five clock phases and could be realized with five conductor levels, as well as an alternative version which used only three conductor levels [I]. From a fabrication point of view the former has the virtue of being immune to intralevel gate-gate shorts, but has the drawback of requiring more conductor levels. The latter version, on the other hand, requires gates for separate clock phases to be fabricated on the same conductor level (therefore leaving it vulnerable to intralevel shorts), and in addition requires these gates to be closely abutted. For good charge transfer the gap between these gates must be less than 1 /tm, and this exacerbates the susceptibility of this structure to intralevel shorts. The only 2D-transfer CCD demonstrated thus far has been a 32 x 32 device by Kansy that was developed as a reformatting analog memory for 2D Fourier transforms, but his structure allowed only unidirectional transfer in each of two orthogonal directions

PI.
We describe here a new 2D CCD structure, which we term an orthogonal-transfer CCD (OTCCD), that is capable of transferring charge in all four directions. In contrast to SCquins proposed structure, this device is implemented as a four-phase device in four conductor levels. It thus features immunity to intralevel shorts with one less level and can therefore be applied to large-area devices with the prospect of high yields. We also describe some initial results on a 64 x 64pixel prototype frame-transfer imager in which the OTCCD structure is used in the imaging pixels. Fig. 1 illustrates the basic features of the CCD cell, with the four gate levels, or phases, labeled G1-G4. With G1 biased low to act as a channel stop, gates (32434 can be clocked in a conventional threephase manner to transfer charge vertically. Likewise, the gates G2 can be biased low and gates G 1, G3, and G4 can be clocked to transfer charge horizontally. Conventional channel stops (such as LOCOS) are required under the intersection of the GI and G2 gates and are shown as shaded areas. Fig. 2 shows a portion of an OTCCD pixel array from the imaging section of a 64 x 64-pixel frame-transfer imager.
Manuscript received March 1, 1994; revised July 27, 1994. The review of this paper was arranged by Associate Editor W. F. Kosonocky. This work was supported by the Department of the Air Force and by the National Science Foundation under Contract Number AST 89-58065. B. E. Burke, R. K. Reich, and E. D. Savoye are with the Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02173-9 108 USA. J. I Tony is with the Department of Physics, Massachusetts Institute of . Technology, Cambridge, MA 02139-4307 USA. IEE:E Log Number 9406195.

0018-9383/94$04.00 0 1994 IEEE