Bus Structure Typically, a bus consists of 50 to hundreds of separate lines.

On any bus the lines are grouped into three main function groups: data, address, and control. There may also be power distribution lines for attached modules.

Data lines Path for moving data and instructions between modules. Collectively are called the data bus. Consists of: 8, 16, 32, 64, etc bits key factor in overall system performance Address lines Identifies the source or destination of the data on the data bus. CPU needs to read an instruction or data from a given memory location. Bus width determines the maximum possible memory capacity for the system. Control lines Used to control the access to and the use of the data and address lines. Transmits command and timing information between modules. Typical control lines include the following: Memory write: causes data on the bus to be written to the addressed memory location. Memory read: causes data from the addressed memory location to be placed on the bus. I/O write: causes data on the bus to be output to the addressed I/O port. I/O read: causes data from the addressed I/O port to be placed on the bus. Transfer ACK: indicates that data have been from or placed on the bus. Bus request: indicates that a module needs to gain control of the bus. Bus grant: indicates that a requesting module has been granted control of the bus.

Interrupt request: indicates that an interrupt is pending. Interrupt ACK: indicates that the pending interrupt has been recognized. Clock: used to synchronize operations. Reset: initializes all modules. What does a bus look like? Parallel lines on a circuit board. Ribbon cables. Strip connectors of a circuit board. PCI, AGP, PCI Express, SCSI, etc Sets of wires.
Bus Arbitration In a single bus architecture when more than one device requests the bus, a controller called bus arbiter decides who gets the bus, this is called the bus arbitration. Arbitration is mostly done in favour of a master micro processor with the highest priority.

Centralized Bus Arbitration

Centralized bus arbitration requires hardware that will grant the bus to one of the requesting devices. This hardware can be part of the CPU or it can be a separate device on the motherboard. Bus Request Line This is a wired-OR line: the controller only knows that a request has been made by a device, but doesn't know which device made the request. Bus Grant Line This line is propagated through all of the devices. When the controller sees that a bus request has been made, it asserts the Bus Grant line to the first device. If a device made a request, it will take control of the bus when it receives the asserted Bus Grant Line and will leave the Bus Grant line negated for the next device in the chain. If the device didn't request the bus, then it will assert the Bus Grant line for the next device in the chain.

If more than one device makes a request at the same time, then the device that is closer to the arbiter will get the bus. This is known as daisy-chaining. There is a discrete phase in the bus request cycle where requests can be made. Many devices can request the bus during this phase.

Centralized Two Level Bus Arbiter

This scheme is represented in Fig 3-36 (b) from the text. The lines needed are:

Bus Request: one for each level. Bus Grant: one for each level.

This helps to alleviate the problem that the closest device to the controller always gets the device. If requests are made on more than one request line during the same clock cycle, then only the highest priority is granted the bus. The advantage to this is that once the bus has been granted to a lower priority device, a higher priority device can't steal the bus. However, if a higher priority device makes a request during each cycle, then the lower priority device will never get the bus.

Decentralized Bus Arbitration

In decentralized arbitration there isn't an arbiter, so the devices have to decide who goes next. This makes the devices more complicated, but saves the expense of having an arbiter.