University of Massachusetts Dartmouth Spring 2009 CIS 273: Computer Organization & Design Laboratory #8 Design of a 4-bit Shift

t Register
Objectives

Learn VHDL statements used for describing storage elements: IF statement, PROCESS statement, and WAIT UNTIL statement. Develop a VHDL model of a four-bit shift register.

Introduction

In this lab, you will create a VHDL model for a 4-bit shift register capable of performing the following operations: (a) Parallel Load (b) Logical shift right (0 in, LSB lost) A shift register is a basic building block for the shift-and-add multiplication hardware discussed in class.

Design
The circuit below is composed of four edge-triggered D flip-flops and has a clock input that causes operations (a) or (b) above to be carried out on its rising edge. The D input to each flop-flop comes from two different sources, through multiplexers. One source is the preceding flip-flop, which is needed for the shift-register operation. The other source is the external input that corresponds to the bit that is to be loaded into the flip-flop as part of the parallel-load operation. The control signal L (load) is used to select the mode of operation. If L = 1, then the parallel input data are loaded into the register. If L = 0, then the circuit operates as a shift register. In both cases the action takes place on the positive edge of the clock.

Figure 1: Parallel-I/O shift register

VHDL code

In previous labs, you have used two types of assignment statements: 1) simple assignment statements, which involve logic or arithmetic expressions and 2) selected assignment statements, which involve signal assignment based on a selection criteria. Both these statements share the property that the order in which they appear in VHDL code does not affect the meaning of the code. Because of this property, these statements are called concurrent assignment statements. VHDL also provides a second category of statements, called sequential assignment statements, for which the ordering of the statements may affect the meaning of the code. Figure 2 gives an example of VHDL code that uses a sequential assignment statement called the IF-THEN-ELSE statement. VHDL requires that the sequential assignment statements be placed inside another type of statement, called a process statement. The process statement begins with the PROCESS keyword, followed by a parenthesized list of signals, called the sensitivity list. The process statement in Figure 2 uses an if-then-else statement to define the value of the Q output. In general there can be a number of statements inside a process. These statements are considered as follows. Using VHDL jargon, we say that when there is a change in the value of any signal in the process's sensitivity list, then the process becomes active. Once active, the statements inside the process are evaluated in sequential order. Any assignments made to signals inside the process are not visible outside the process until all of the statements in the process have been evaluated. If there are multiple assignments to the same signal, only the last one has any visible effect. The code in Figure 2 gives an example of VHDL code that has implied memory. Because the code does not specify what value the Q signal should have when the condition for the IF statement is not satisfied, the semantics specify that in this case Q should retain its current value. The code therefore describes a level triggered D flip-flop. The process sensitivity list includes both Clk and D because these signals can cause a change in the value of the Q output. library ieee; use ieee.std_logic_1164.all; entity dlatch is port (D, Clk: in std_logic; Q: out std_logic); end dlatch; architecture behavior of dlatch is begin process (D, Clk) begin if Clk = '1' then Q <= D; end if; end process; end behavior;
Figure 2: Code for level-triggered D flip-flop

Figure 3 defines another entity named dff, which is a positive-edge-triggered D flipflop. It uses a WAIT UNTIL statement with the condition Clk = 1, which means that "the value of the Clk signal has just changed, and the value is now equal to 1". The WAIT UNTIL construct implies that the sensitivity list includes only the clock signal. A process can use a WAIT UNTIL statement only if this is the first statement in the process. Because the Q output changes only as a result of a positive clock edge, the code describes a positive-edge-triggered D flip-flop. library ieee; use ieee.std_logic_1164.all; entity dff is port (D, Clk: in std_logic; Q: out std_logic); end dff; architecture behavior of dff is begin process begin wait until Clk = '1'; Q <= D; end process; end behavior;
Figure 3: Code for a positive-edge-triggered D flip-flop

Assume that we wish to write the VHDL code that represents the four-bit shift register in Figure 1. One approach is to write hierarchical code that uses four subcircuits. Each subcircuit consists of a D flip-flop with a 2-to-1 multiplexer connected to the D input. Figure 4 defines the entity named muxdff, which represents this subcircuit. The two data inputs are D0 and D1, and they are selected using the Sel input. library ieee; use ieee.std_logic_1164.all; entity muxdff is port (D0, D1, Sel, Clk: in std_logic; Q: out std_logic); end muxdff;
Figure 4: Entity declaration for a D flip-flop with a 2-to-1 multiplexer on the D input

We can now create a separate VHDL entity named shift4 for the shift register in Figure 1, which uses the muxdff entity as a subcircuit. Figure 5 gives the entity declaration for shift4. The 4-bit data are loaded from the D input when L = 1. When L = 0, shifting takes place in the left to right direction (right shift) and a 0 bit is loaded into the most-significant bit, Q(3), from the w input. The output Q(3 downto 0) is

specified to have the mode BUFFER. This allows the value of the signal to be used inside the entity, which means that in an assignment statement, the signal can appear both on the left and right sides of the <= operator. library ieee; use ieee.std_logic_1164.all; entity shift4 is port (I : in std_logic_vector (3 downto 0); L, w, Clk: in std_logic; Q : buffer std_logic_vector (3 downto 0)); end shift4;
Figure 5: Entity declaration for a 4-bit shift register

What you need to do

(1) Create a new project by first creating a folder called shift4 and make it the working directory of the project. Set the Project name and the Top-level design entity to shift4. Choose StratixTM as the target device family (2) Create a new VHDL file. Type (or paste) the declaration for the entity named muxdff in Figure 4, which represents a D flip-flop with a 2-to-1 multiplexer connected to the D input, into the Text Editor. Write a behavioral architectural body for muxdff using the WAIT UNTIL and IF-THEN-ELSE statements. If Sel = 0, then Q should be assigned the value of D0; otherwise, Q should be assigned the value of D1. In both cases, the Q output should change only as a result of a positive clock edge. Save the file using the name muxdff.vhd. Make sure to put a checkmark in the box Add file to current project. (3) Create a new VHDL file. Type (or paste) the declaration for the entity named shift4 in Figure 5 into the Text Editor. Write a structural architecture body for shift4 using the muxdff entity as a subcircuit. Save the file using the name shift4.vhd. Make sure to put a checkmark in the box Add file to current project. (4) Compile your project and perform functional simulation of the 4-bit shift register. Verify the load and logical shift right operations for the data input 1101.

Check off
To pass this lab you must demonstrate the working of your VHDL models for the shift register represented by the shift4 entity and turn in a hard copy of the following:

The complete VHDL source code (including architecture) for the entity named shift4. The results of the functional simulation described above.