Yield Enhancement for 3D-Stacked ICs:

Recent Advances and Challenges

Qiang Xu1, Li Jiang 1, Huiyun Li 2 and Bill Eklow 3
Chinese University of Hong Kong 2 Shenzhen Institutes of Advanced Technologies, CAS 3 Cisco Systems, Inc.
1 The

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l i able C o mputing L aboratory

3D-Stacked IC Roadmap
CMOS+Image Sensor
3D stacked DRAM
TSV DRAM

RD/WR

I/O Buffer PCB

Interposer-based
TSV

PFGA Die Interposer

More TSVs
Package

True 3D-stacked ICs

More Complicated

Yield must be high enough to be commercially viable!

Outline
Yield Modeling for 3D-Stacked ICs Pre-bond Testing for Stack Yield Loss Reduction Wafer/Die Matching for Stack Yield Enhancement TSV Repair for Assembly Yield Improvement Challenges and Future Research Directions

Manufacture Yield for 3D-Stacked ICs

3D-stacked IC yield [Deng TVLSI05]

Yfinal = Ystack Y Assembly(i)

i=1

Layer-1

Stack yield loss

Assembly yield loss

Normal

Misalignment

Impurity

Open Short

Leak & Void & Delaminating Break

Stack Yield Modeling

Die Yield:
Compound Poisson Model

Defect density Die Area Effect Clustering

Ydie=(1+ DAdie )-
Y =(1+ i
3D diei

Die yield in 3D-stacked IC

assuming equally partitioned into N layers

Di

( Adie + Oi )) -i N
N

2D

Stack yield: W2W Bonding Stack yield: D2D/D2W Bonding

assuming perfect pre-bond test

Ystack,W2W =Ydie
i=1

Ystack,D2D/D2W =min[Ydiei ]

Impact of Pre-bond Test Quality

Pre-bond test is not perfect
Fault Coverage

Test escape ratio for defective dies: Test escape ratio for stacked IC:

Rescape = 1 - Ydie c

1-F

N layers stack
1-Fc Ydie i i=1 N

Rescape,D2D/D2W = 1 -

Stack Yield: D2D/D2W bonding with pre-bond test

Ystack,D2D/D2 W =min[Ydiei ]

1-Fc Ydie i i=1

High-quality pre-bond test is essential to improve stack yield!

Assembly Yield Modeling

Bonding yield loss
No model exists Add keep-out area for each and every TSV

TSV Yield:

YTSV = (1 fTSV )

N TSV

Number of TSVs TSVs failure rate

Example: fTSV=0.05%, NTSV=1000, YTSV=77.8%

Effective TSV repair is crucial to improve assembly yield!

Outline
Yield Modeling for 3D-Stacked ICs Pre-bond Testing for Stack Yield Loss Reduction Wafer/Die Matching for Stack Yield Enhancement TSV Repair for Assembly Yield Improvement Challenges and Future Research Directions Summary

Pre-bond Testing is Challenging

Wafer probing difficulty
Footprint mismatch between TSV and Probe needle Extra probe force on thinned wafer
Probe Head
Probe Head

Test infrastructure design

Test access issue Disconnected clock tree and power network

Wafer Probing in Pre-Bond Test

Add extra test pad without probing TSVs Probe multiple TSVs at the same time
gated

[Noia ITC11]

Function Input

scan

chain

Contactless testing
Capacitive coupling for signal transmission [Wu VLSI-DAT06] Inductive coupling for DC voltage transmission [Yoshida ISSCC09]

Probe Head

Test Access
Die wrapper Layer Test Controller

Die 1
wrapper Core 1
BIST

wrapper
TDC TDC

IEEE 1149.1 TAP

TSV
Layer Test Controller Die wrapper wrapper

wrapper scan chain

Board
Lewis ICCAD07 Marinissen ITC10

Die 2

Test Infrastructure Design

Clock tree synthesis for pre-bond testability
Under a given skew constraints Minimizes wire length & clock power consumption [Zhao ICCAD09] Minimizes clock power and the used TSVs [Kim DAC10]

Power delivery network design for pre-bond testability

[Panth VTS11]

Pre-bond TSV Test

Built-in sense amplifier [Chen ATS09,VTS10]
Measure the I-V characteristic Detect capacitive/resistive TSV defect

Cp Ron

Outline
Yield Modeling for 3D-Stacked ICs Pre-bond Testing for Stack Yield Loss Reduction Wafer/Die Matching for Stack Yield Enhancement TSV Repair for Assembly Yield Improvement Challenges and Future Research Directions

Wafer Matching for Yield Enhancement

Wafer matching based on pre-bond testing results [Reda
VLSI09, Verbree ETS10]

Die Matching for Yield Enhancement

Parametric yield enhancement [Ferri JETC08]
CPU-to-L2 cache die stack

Inter-layer redundancy for 3D-stacked Memory [Jiang ICCAD10]

Spares Rows Bit-array

L1
D ec

TSVs

L2

od

er

Redundancy Sharing for Yield Enhancement

1 1 2 3 4 1 5 2
1 1 3 5

1R, 2C, Irreparable

0R, 3C, Reparable 2R, 1C, Reparable

2 3 5 1 2 3 4 5 6 7

3 4 5 6 7 1 1

1 2 3 4 5 6

2 3 4 5
1

Solution 2 4 4 With the same amount of resources, memory yield can be improved by redundancy sharing! 5 5

1R, 2C, Self-Reparable

Outline
Yield Modeling for 3D-Stacked ICs Pre-bond Testing for Stack Yield Loss Reduction Wafer/Die Matching for Stack Yield Enhancement TSV Repair for Assembly Yield Improvement Challenges and Future Research Directions

Neighboring TSV Repair

Signal Signal TSV Redundant TSV

Die1 Die2 Signal-Switching

[Kang JSSC10]

Signal-Shifting
[Hsieh DATE10]

Crossbar
[Loi ICCAD08]

2 Spare TSVs 4 Signal TSVs

Redundancy Ratio

1 Spare TSV N TSV Chain

1 N

M Spare TSV Rows N X N TSV Grid

M N

1 2

TSV Repair with Signal Rerouting

Switch Signal

Switch Design
TSV North West East

South Signal

Signal TSV Redundant TSV

Lend TSV to North, Lend Initialto North TSV bypass signal from west

Rerouting Scheme

Repair Channel
Repair Path

TSV W

N E Sig

M+N Spare TSVs M X N TSV Grid

M+N MxN

Outline
Yield Modeling for 3D-Stacked ICs Pre-bond Testing for Stack Yield Loss Reduction Wafer/Die Matching for Stack Yield Enhancement TSV Repair for Assembly Yield Improvement Challenges and Future Research Directions

Challenges and Future Research Directions

Yield Modeling for 3D-Stacked Ics
Model for wafer/Die matching effect Model for bonding yield

Pre-bond testing for 3D-Stacked ICs

Probing remains the biggest challenge Pre-bond TSV test cost reduction Test access for non-digital and non-CMOS circuitries Overtest/undertest due to pre-/post-bond difference More accurate TSV fault models

More effective TSV repair methodologies

Yield needs to be considered up front in the design flow for 3D-Stacked ICs!

Thank you for your attention !

hk

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