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9 Hrs
Floating point Arithmetic, Pipeline Processing-Pipeline design- Parallelism in uni-processor system parallel computer structures vector processing requirements
9 Hrs
Memory technology: Memory Device Characteristics, Random Access Memory (RAM), Serial Access Memory; memory systems: Memory Allocation virtual memory -Caches: Main features, address mapping
Text Books 1 John P Hayes, Computer architecture and organization, III edition McGraw2 2. M.M.Mano, Computer system architecture, PHI, 1982. References 1. John. L. Hennessy & David A. Patterson, Computer Architecture, Elsevier, India, 3rd Ed, 2003.
Hill, 199
2. Andrew S.Tanenbaum, Structured computer organization, PHI, 1990. 3. William Stallings, Computer organization and architecture, Addison Wrsley 5th edition, 2001. 4. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer organization, McGrawHill, 2002. 5. Kai Hwang, Advanced Computer architecture, McGraw-Hill1993.
Evaluation Procedure
Quiz 1 (5M) CAT 1 (15M) Quiz 2 (5M) CAT 2 (15M) Quiz 3 (5M) Assignment / Mini project (5M) Term End Exam 50M
ENIAC (Electronic Numerical Integrator and Computer) Designed by Mauchly and Eckert University of Pennsylvania First general-purpose electronic digital computer Response to WW2 need to calculate trajectory tables for weapons. Built 1943-1946 too late for war effort. ENIAC DetailsDecimal (not binary) 20 accumulators of 10 digits Programmed manually by switches 18,000 vacuum tubes 30 tons 15,000 square feet 140 kW power consumption 5,000 additions per second
Vacuum Tube
Vacuum tubes, 80 feet long, 8.5 feet high, several feet wide, total 18,000 BABBAGE tubes vacuum
It is for decimal number system, Which can perform A,S,M,D. To speed up addition ENIAC 1946uses operation it pipelining First Electronic tech.
Computer
IBM 7070, 7074 (1960), 7072(1961) 1959 IBM 7090, 7040 (1961), 7094 (1962) 1959 IBM 1401, 1410 (1960), 1440 (1962) FORTRAN, ALGOL, and COBOL are first standardized programming languages
1964 Control Data delivers the CDC 6600 nanoseconds telecommunications BASIC, Beginners All-purpose Symbolic Instruction Code
Generations of Computers
Vacuum tube - 1946-1957 (One bit Size of a hand) Transistor - 1958-1964
Up to 100 devices on a chip
(One bit Size of a fingernail)
INTEL PROCESSORS
Processor
Intel Intel Intel Intel 4004 8008 8080 8088
Transistor count
2,300 2,500 4,500 29,000 134,000 275,000 1,200,000 3,100,000 7,500,000 9,500,000 42,000,000 47,000,000 220,000,000 291,000,000 582,000,000 592,000,000 731,000,000 1,700,000,000 1,900,000,000 2,000,000,000 2,300,000,000
Date of introduction
1971 1972 1974 1979 1982 1985 1989 1993 1997 1999 2000 2008 2003 2006 2006 2004 2008 2006 2008 (future) (future)
Manufacturer
Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel
Intel 80286 Intel 80386 Intel 80486 Pentium Pentium II Pentium III Pentium 4 Atom Itanium 2 Core 2 Duo Core 2 Quad Itanium 2 with 9MB cache Core i7 (Quad) Dual-Core Itanium 2 Six-Core Xeon 7400 Quad-Core Itanium Tukwila 8-Core Xeon Nehalem-EX
PDP-11 (1970)
Intel
Noyce, Moore, and Andrew Grove leave Fairchild and found Intel in 1968
focus on random access memory (RAM) chips
Question: if you can put transistors, capacitors, etc. on a chip, why couldnt you put a central processor on a chip? Ted Hoff designs the Intel 4004, the first microprocessor in 1969
based on Digitals PDP-8
Microcomputers
Intel processors
CPU Year 4004 1971 8008 1972 8080 1974 8088 1980 80286 1982 80386 1985 80486 1989 Pentium1993 Data 4 8 8 8 16 32 32 64 Memory MIPS 1K 16K 64K 1M .33 1M 3 4G 11 4G 41 4G 111
1000 storage locations called words. Each word 40 bits. A word may contain: A numbers stored as 40 binary digits (bits) sign bit + 39 bit value An instruction-pair. Each instruction: An opcode (8 bits) An address (12 bits) designating one of the 1000 words in memory.
MBR: Memory Buffer Register - contains the word to be stored in memory or just received from memory. MAR: Memory Address Register - specifies the address in memory of the word to be stored or retrieved. IR: Instruction Register - contains the 8-bit opcode currently being executed. IBR: Instruction Buffer Register - temporary store for RHS instruction from word in memory. PC: Program Counter - address of next instruction-pair to fetch from memory. AC: Accumulator & MQ: Multiplier quotient - holds operands and results of ALU ops.
AC
MQ
MBR
IBR
PC
IR
MAR
AC = 3 AC 7
MEMORY 1. LOAD M(X) 500, ADD M(X) 501 2. STOR M(X) 500, (Other Ins) ..... 500. 3 501. 4
MQ
500
PC 1 2 MAR 1 501 500 2 MBR LOAD M(X) 500, ADD M(X) 501 STOR M(X) 500, (Other Ins) 4 3 IR LOADM(X) STOR M(X) ADD IBR ADD M(X) 501 (Other Ins) AC 7 3
PC = Mar PC PC = 12 MAR PC
LOAD M(X) 500, 3 ADD M(X) 501
IR
Problems
Let A = A(1), A(2), , A(1000) and B= B(1), B(2), , (1000) be two vectors (one dimensional arrays) comprising 1000 numbers each that are to be added to form an array C such that C(I) = A(I) + B(I) for I = 1, 2, , 1000. Using the IAS instruction set, write a program for this problem. Ignore the fact that the IAS was designed to have only 1000 words of storage.
Solution:
2. On the IAS, what would the machine code instruction look like to load the contents of memory address 2? Solution: Load M(X), Opcode 00000001 Address 000000000010 Machine code instruction: 00000001 000000000010 3. How many trips to memory does the CPU need to make to complete this instruction during the instruction cycle? Solution: To fetch the instruction 1st trip, to fetch the operand from the given address in the instruction 2nd trip. So, totally trips to memory
4. On the IAS, describe in English the process that the CPU must undertake to read a value from memory and to write a value to memory in terms of what is put into the MAR, MBR, address bus, data bus, and control bus. Solution: Read:
CPU puts the address of the value it wants into MAR. Read control signal is generated CPU puts the address on the address bus Memory puts the corresponding data onto data bus This data is then transferred to MBR.
Write:
CPU puts the address of the value it wants into MAR. CPU places the data onto the data bus It asserts write control signal Places the address onto the address bus. Memory transfers the data on the data bus into the corresponding memory location.
Size of
AC 40 bits MQ 40 bits MBR 40 bits IBR 20 bits IR 8 bits MAR 12 bits PC 12 bits
Quiz
MBR MAR AC IBR IR PC MQ IAS What is Computer Architecture? What is Computer Organization? Number of words in IAS machine? Number of bits per word in IAS machine? Data is represented in ____________ form in IAS machine Explain Stored program concept.
References
http://www.computersciencelab.co m/ComputerHistory/HistoryPt1.htm W. Stallings, Computer organization and architecture, Prentice-Hall,2000