INTELLIGENT TRAIN ENGINES

By:

Anjali Sharma Prerna Kanchan Priya Singh Surabhi Parikh

Department of Applied Electronics And Instrumentation Engineering

Shri Ram Murti Smarak Womens College of Engineering & Technology Bareilly Gautam Buddh Technical University, Lucknow. April, 2012

INTELLIGENT TRAIN ENGINES

By: Anjali Sharma Prerna Kanchan Priya Singh Surabhi Parikh

Submitted to the Department of Applied Electronics And Instrumentation Engineering in partial fulfillment of the requirements for the degree of Bachelor of Technology in Applied Electronics and Instrumentation Engineering

Shri Ram Murti Smarak College of Engineering & Technology Bareilly Gautam Buddh Technical University, Lucknow. April, 2012

TABLE OF CONTENTS
DECLARATION CERTIFICATE ACKNOWLEDGEMENT ABSTRACT LIST OF FIGURES CHAPTER 1- INTRODUCTION iv v i ii iii

1.1 APPLICATION 1.2 FEATURES 1.3 FLOW CHART CHAPTER 2- ARCHITECTURE

3 3 5

2.1 BLOCK DIAGRAM 2.2 MAIN BLOCK 2.2.1 FUNCTIONALITY 2.2.2 CONTROL SIGNALS 2.3 RECEIVER BLOCK 2.3.1 FUNCTIONALITY 2.3.2 CONTROL SIGNALS 2.3.3 RECEIVER CONTROL UNIT 2.3.3.1 FUNCTIONALITY 2.3.3.2 CONTROL SIGNALS 2.3.4 RECEIVER FIFO

10 10

11 11

12 12

2.3.4.1 FUNCTIONALITY 2.3.4.2 CONTROL SIGNALS 2.3.5 RECEIVER SHIFTER 2.3.5.1 FUNCTIONALITY 2.3.5.2 CONTROL SIGNALS 2.3.6 RECEIVER DATA COUNTER 2.3.6.1 FUNCTIONALITY 2.3.6.2 CONTROL SIGNALS 2.3.7 RECEIVER PARITY COUNTER 2.3.7.1 FUNCTIONALITY 2.3.7.2 CONTROL SIGNALS 2.3.8 RECEIVER INPUT REGISTER 2.3.8.1 FUNCTIONALITY 2.3.8.2 CONTROL SIGNALS 2.4 CPU INTERFACE UNIT 2.4.1 FUNCTIONALITY 2.4.2 CONTROL SIGNALS

13 13

14 14

15 15

15 16

16 16

17 17

CHAPTER 3- INTRODUCTION TO SIMULATION TOOLS 3.1 MODELSIM SIMULATION ENVIRONMENT 3.1.1 BASIC SIMULATION FLOW 3.1.2 PROJECT FLOW 3.1.3 MULTIPLE LIBRARY FLOW 3.1.4 DEBUGGING TOOLS 3.2 BASIC SIMULATION FLOW 19 20 20 21

3.2.1 CREATION OF WORKING DESIGN LIBRARY 3.2.2 COMPILATION OF DESIGN UNITS 3.2.3 LOADING THE DESIGN 3.2.4 RUNNING THE SIMULATION CHAPTER 4-MODULE DESCRIPTION TRANSMITTER BLOCK 4.1 FUNCTIONALITY 4.2 CONTROL SIGNALS 4.3 WITHIN THE BLOCK 4.3.1 TRANSMITTER CONTROL UNIT 4.3.3.1 FUNCTIONALITY 4.3.3.2 CONTROL SIGNALS 4.3.2 TRANSMITTER FIFO 4.3.2.1 FUNCTIONALITY 4.3.2.2 CONTROL SIGNALS 4.3.3 TRANSMITTER SHIFTER 4.3.3.1 FUNCTIONALITY 4.3.3.2 CONTROL SIGNALS 4.3.4 TRANSMITTER DATA COUNTER 4.3.4.1 FUNCTIONALITY 4.3.4.2 CONTROL SIGNALS 4.3.5 TRANSMITTER PARITY COUNTER 4.3.5.1 FUNCTIONALITY 4.3.5.2 CONTROL SIGNALS 4.3.6 TRANSMITTER OUTPUT REGISTER

22 23 24 26

29 29

30 30

31 31

32 32

33 33

33 34

4.3.6.1 FUNCTIONALITY 4.3.6.2 CONTROL SIGNALS 4.4 CODING 4.4.1 TRANSMITTER BLOCK 4.4.2 TRANSMITTER CONTROL UNIT 4.4.3 TRANSMITTER FIFO 4.4.4 TRANSMITTER SHIFTER 4.4.5 TRANSMITTER PARITY COUNTER 4.4.6 TRANSMITTER OUTPUT REGISTER 4.5 OUTPUT WAVEFORM

34 34

35 37 40 42 44 45 46

CHAPTER 5- CONCLUSION 5.1 FUTURE ASPECTS APPENDIX REFERENCES 48 49 65

DECLARATION

I hereby declare that this submission is my own work and that, to the best of my knowledge and belief , it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher learning, except where due acknowledge has been made in the text.

Signature: Name : Anjali Sharma Roll No.: 0845035405 Date:

Signature: Name: Prerna Kanchan Roll No.:0701431059 Date:

Siganture: Name: Priya Singh Roll No.:0845035018 Date:

Signature: Name: Surabhi Parikh Roll No.:0845035026 Date:

CERTIFICATE

This is to certify that Project Report entitled INTELLIGENT TRAIN ENGINE which is submitted by Anjali Sharma,Prerna Kanchan.Priya Singh and Surabhi Parikh in partial fulfillment of requirement for the award of degree B.Tech in Applied electronics And Insrumentation of U.P. Technical University is a record of the candidates own work carried out by them under my supervision. The matter embodied in this thesis is original and has been submitted for the award of any other degree.

Date:

Supervisor Ms. Nazia Parveen

ACKNOWLEDGEMENT

It gives us a great sense of pleasure to present the report of B.Tech Project undertaken during B.Tech Final Year. We owe special debt of gratitude to ms. Nazia Parveen Department of EC & AEI, Shri Ram Murti Smarak Womens College of Engineering & Technology, Bareilly for her constant support and guidance throughout the course of our work. Her sincerity, thoroughness and perseverance have been a constant source of inspiration for us. It is only her cognizant efforts that our endeavors have seen light of the day. We also take the opportunity to acknowledge the contribution of Mr Ashish Gangwar , Head of Department, Applied Electronics And Instrumentation, Shri Ram Murti Smarak Womens College of Engineering & Technology, Bareilly for his full support and assistance during the development of the project. We also do not miss the opportunity to acknowledge the contribution of all faculty member of the department for their kind assistance and cooperation during the development of our project. Last but not the least, we acknowledge our friends for their contribution in the completion of the project. Signature: Name : Anjali Sharma Roll No.: 0845035405 Date: Signature: Name: Prerna Kanchan Roll No.:0845035012 Date:

Signature: Name: Priya Singh Roll No.:0845035018 Date:

Signature: Name: Surabhi Parikh Roll No.:0845035026 Date:

ABSTRACT

We know that the railway network of India is the biggest in south Asia and perhaps the most complicated in all over the world. There are so many different types of trains local, fast, super fast, passenger, goods. etc. and their so many multiple routs. Although the time table is perfect it is not at all possible to maintain it. And thats why the train accidents are becoming more and more usual. So why not we add a kind of intelligence to the train engines itself so that it tries to avoid accidents.

The idea is whenever any engine observes a red signal on its track it will start decreasing its speed gradually and stops automatically at some distance from the signal pole. After then when it gets green signal the driver can manually start the train and go on. In the mean time when train has not stopped yet and a red signal becomes green then it crosses the signal pole with low speed and then driver can slowly increase the speed.

So now before the driver observes the red signal the engine itself observes it and automatically starts decreasing speed and then stops. The driver can feel relax in driving because he doesnt have to take care about red signal. Even if he forgets to take any action on red signal then also we can avoid accidents by the implementation of this idea.

LIST OF FIGURES
FIGURES
Figure 1.1 Asynchronous Communication Figure 1.2 Flow Chart Figure 2.1 UART Structure Figure 2.2 Block Diagram Figure 2.3 Main Block Control Signals Figure 2.4 Rx Unit Control Signals Figure 2.5 Rx Control Unit Control Signals Figure 2.6 Rx Fifo Control Signals Figure 2.7 Rx Shifter Control Signals Figure 2.8 Rx Data Counter Control Signals Figure 2.9: Rx Parity Counter Control Signals Figure 2.10: Rx Input Register Control Signals Figure 2.11: CPU I Unit Control Signals Figure 3.1: Basic Simulation Flow Figure 3.2: Project Flow

PAGE
2 7 9 10 11 12 13 14 15 16 17 17 18 20 21

Figure 3.3: Multiple Library Flow Figure 3.4: The Create a New Library Dialog Figure 3.5: Work library added to a Library Window Figure 3.6: Compile Source Files Dialog Figure 3.7: Verilog Modules Compiled Into Work Library Figure 3.8: Loading Design with Start Simulation Dialog Figure 3.9: The Design hierarchy Figure 3.10: The Object Window and Processes Window Figure 3.11: Using The Popup Menu Figure 3.12: Waves Drawn in Wave Window Figure 4.1 Tx Unit Control Signals Figure 4.2 Tx Control Unit Control Signals Figure 4.3 Tx Fifo Control Signals Figure 4.4 Tx Shifter Control Signals Figure 4.5 Tx Data Counter Control Signals Figure 4.6: Tx Parity Counter Control Signals Figure 4.7: Tx Input Register Control Signals Figure 4.8: Output Waveform

22 23 24 24 25 26 26 27 28 28 30 31 32 33 34 35 35 36

CHAPTER 1
INTRODUCTION

INTRODUCTION

What we have to do is we have to attach a transmitter with signal pole which will start transmitting signals only when the red light is on. If there is green light no transmission. The engine has a receiver which catches these transmitted signals and takes desire actions. Both the transmitter and receiver are of RF type with minimum range of 2 Km. so that train can get enough time to decrease its speed and stop before the signal pole with minimum swapping distance of 100-200 mt. Here in our project we have used IR transmitter and receiver instead of RF for demo purpose. But same idea can be easily implemented with RF also with a little more cost.

1.1 Application Wayside track sensors are installed to provide route integrity information. This technology can also be used in other vehicle not only in train . Using PTC systems will improve railway safety by significantly reducing the probability of collisions between trains, casualties to workers, and over speed accidents. Intelligent weather systems

1.2 Features
1. .

1.3 Flow Chart

Figure 1.2: Flow Chart

CHAPTER 2
ARCHITECTURE

ARCHITECTURE

The basic architecture of our project comprises the following blocks: Transmitter Unit Receiver Unit

These two units are incorporated within the Main Block in our project. Within each of these units are a number of blocks performing unique functions that carry the data bits at different stages. MAIN BLOCK

TRANSMITTER UNIT
IC 555 IR LEDS Darlington Pairs RC Components

RECEIVER UNIT
IR sensor TSOP 1738 Microcontroller 89C51 Current driver chip ULN2003A Voltage regulator ICs (78XX series)

Figure 2.1: Structure

2.1 Block Diagram

Figure 2.2: Block Diagram

2.2 Main Block

2.2.1 Functionality The train engine runs on 24V DC motor so that we can easily vary its speed by varying applied voltage. The switching voltage is applied in step of 18 V, 15 V, 12 V and 9 V (min speed). The 230 VAC is step-down to 24 VAC by 12-0-12, 2 Ampere step down transformer. As shown in figure this 24 VAC line runs parallel with track at the top of the train. Movable tapping are taken from this line and fed to the internal circuit of engine. These tapping slides as the train runs on the track and give continuous supply to circuit. The IR sensor is placed at the top of the engine, senses the signals transmitted by IR transmitter attached to signal pole. Train track is straight and 20 ft long. Signal pole is placed at the end of track and train starts from farther end.

2.3 Receiver Block

2.3.1 Functionality The receiver is housed in engine which senses the IR signals and takes suitable action.

2.4 Transmitter Block

2.4.1 Functionality The transmitter is housed in signal pole and it is activated only when red light is ON.

CHAPTER 3
MODULE DESCRIPTION

MODULE DESCRIPTION TRANSMITTER MODULE

4.1 Functionality
. The heart of the circuit is IC555. The main component of the circuit is only IC555.

Connections: Both ICs are connected in astable mode. The frequency of U2 is 0.5 Hz and U1 is 38 KHz. This is decided by RC components connected with it. The output of U2 is connected with reset pin (4) of U1. Thus the output of U2 controls the operation of U1 means it will switch on or off the output of U1. The output of U1 is fed to two IR LEDs through Darlington pair made up of Q1, Q2 and R5. The 9V DC battery is connected with circuit through SPDT switch SW1 as shown.

Figure 2.4: Transmitter Block Diagram

RECEIVER MODULE

POWER SUPPLY:

Power supply is a reference to a source of electrical power. A device or system that supplies electrical or other types of energy to an output load or group of loads is called a power supply unit or PSU. The term is most commonly applied to electrical energy supplies, less often to mechanical ones, and rarely to others.Here in our application we need a 5v DC power supply for all electronics involved in the project. This requires step down transformer, rectifier, voltage regulator, and filter circuit for generation of 5v DC power. Here a brief description of all the components is given as follows:

TRANSFORMER:

A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors the transformer's coils or "windings". Except for air-core transformers, the conductors are commonly wound around a single iron-rich core, or around separate but magnetically-coupled cores. A varying current in the first or "primary" winding creates a varying magnetic field in the core (or cores) of the transformer. This varying magnetic field induces a varying electromotive force (EMF) or "voltage" in the "secondary" winding. This effect is called mutual induction.

If a load is connected to the secondary circuit, electric charge will flow in the secondary winding of the transformer and transfer energy from the primary circuit to the load connected in the secondary circuit.

The secondary induced voltage VS, of an ideal transformer, is scaled from the primary VP by a factor equal to the ratio of the number of turns of wire in their respective windings:

By appropriate selection of the numbers of turns, a transformer thus allows an alternating voltage to be stepped up by making NS more than NP or stepped down, by making it BASIC PARTS OF A TRANSFORMER In its most basic form a transformer consists of:

A primary coil or winding. A secondary coil or winding. A core that supports the coils or windings.

Refer to the transformer circuit in figure as you read the following explanation: The primary winding is connected to a 60-hertz ac voltage source. The magnetic field (flux) builds up (expands) and collapses (contracts) about the primary winding. The expanding and contracting magnetic field around the primary winding cuts the secondary winding and induces an alternating voltage into the winding. This voltage causes alternating current to flow through the load. The voltage may be stepped up or down depending on the design of the primary and secondary windings.

THE COMPONENTS OF A TRANSFORMER Two coils of wire (called windings) are wound on some type of core material. In some cases the coils of wire are wound on a cylindrical or rectangular cardboard form. In effect, the core material is air and the transformer is called an AIR-CORE TRANSFORMER. Transformers used at low frequencies, such as 60 hertz and 400 hertz, require a core of low-reluctance magnetic material, usually iron. This type of transformer is called an IRON-CORE TRANSFORMER. Most power transformers are of the iron-core type. The principle parts of a transformer and their functions are:

The CORE, which provides a path for the magnetic lines of flux. The PRIMARY WINDING, which receives energy from the ac source. The SECONDARY WINDING, which receives energy from the primary winding and delivers it to the load. The ENCLOSURE, which protects the above components from dirt, moisture, and mechanical damage.

BRIDGE RECTIFIER

A bridge rectifier makes use of four diodes in a bridge arrangement to achieve full-wave rectification. This is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally.

BASIC OPERATION According to the conventional model of current flow originally established by Benjamin Franklin and still followed by most engineers today, current is assumed to flow through electrical conductors from the positive to the negative pole. In actuality, free electrons in a conductor nearly always flow from the negative to the positive pole. In the vast majority of applications, however, the actual direction of current flow is irrelevant. Therefore, in the discussion below the conventional model is retained. In the diagrams below, when the input connected to the left corner of the diamond is positive, and the input connected to the right corner is negative, current flows from the upper supply terminal to the right along the red (positive) path to the output, and returns to the lower supply terminal via the blue (negative) path.

When the input connected to the left corner is negative, and the input connected to the right corner is positive, current flows from the lower supply terminal to the right along the red path to the output, and returns to the upper supply terminal via the blue path.

In each case, the upper right output remains positive and lower right output negative. Since this is true whether the input is AC or DC, this circuit not only produces a DC output from an AC input, it can also provide what is sometimes called "reverse polarity protection". That is, it permits normal functioning of DC-powered equipment when batteries have been installed backwards, or when the leads (wires) from a DC power source have been reversed, and protects the equipment from potential damage caused by reverse polarity. Prior to availability of integrated electronics, such a bridge rectifier was always constructed from discrete components. Since about 1950, a single four-terminal component containing the four diodes connected in the bridge configuration became a standard commercial component and is now available with various voltage and current ratings.

OUTPUT SMOOTHING For many applications, especially with single phase AC where the full-wave bridge serves to convert an AC input into a DC output, the addition of a capacitor may be desired because the bridge alone supplies an output of fixed polarity but continuously varying or "pulsating" magnitude (see diagram above).

The function of this capacitor, known as a reservoir capacitor (or smoothing capacitor) is to lessen the variation in (or 'smooth') the rectified AC output voltage waveform from the bridge. One explanation of 'smoothing' is that the capacitor provides a low impedance path to the AC component of the output, reducing the AC voltage across, and AC current through, the resistive load. In less technical terms, any drop in the output voltage and current of the bridge tends to be canceled by loss of charge in the capacitor. This charge flows out as additional current through the load. Thus the change of load current and voltage is reduced relative to what would occur without the capacitor. Increases of voltage correspondingly store excess charge in the capacitor, thus moderating the change in output voltage / current. The simplified circuit shown has a well-deserved reputation for being dangerous, because, in some applications, the capacitor can retain a lethal charge after the AC power source is removed. If supplying a dangerous voltage, a practical circuit should include a reliable way to safely discharge the capacitor. If the normal load cannot be guaranteed to perform this function, perhaps because it can be disconnected, the circuit should include a bleeder resistor connected as close as practical across the capacitor. This resistor should consume a current large enough to discharge the capacitor in a reasonable time, but small enough to minimize unnecessary power waste.

Because a bleeder sets a minimum current drain, the regulation of the circuit, defined as percentage voltage change from minimum to maximum load, is improved. However in many cases the improvement is of insignificant magnitude. The capacitor and the load resistance have a typical time constant = RC where C and R are the capacitance and load resistance respectively. As long as the load resistor is large enough so that this time constant is much longer than the time of one ripple cycle, the above configuration will produce a smoothed DC voltage across the load. In some designs, a series resistor at the load side of the capacitor is added. The smoothing can then be improved by adding additional stages of capacitorresistor pairs, often done only for sub-supplies to critical high-gain circuits that tend to be sensitive to supply voltage noise. The idealized waveforms shown above are seen for both voltage and current when the load on the bridge is resistive. When the load includes a smoothing capacitor, both the voltage and the current waveforms will be greatly changed. While the voltage is smoothed, as described above, current will flow through the bridge only during the time when the input voltage is greater than the capacitor voltage. For example, if the load draws an average current of n Amps, and the diodes conduct for 10% of the time, the average diode current during conduction must be 10n Amps. This non-sinusoidal current leads to harmonic distortion and a poor power factor in the AC supply. In a practical circuit, when a capacitor is directly connected to the output of a bridge, the bridge diodes must be sized to withstand the current surge that occurs when the power is turned on at the peak of the AC voltage and the capacitor is fully discharged. Sometimes a small series resistor is included before the capacitor to limit this current, though in most applications the power supply transformer's resistance is already sufficient. Output can also be smoothed using a choke and second capacitor. The choke tends to keep the current (rather than the voltage) more constant. Due to the relatively high cost of an effective choke compared to a resistor and capacitor this is not employed in modern equipment. Some early console radios created the speaker's constant field with the current from the high voltage ("B +") power supply, which was then routed to the consuming circuits, (permanent magnets were then too weak for good performance) to create the speaker's constant magnetic field. The speaker field coil thus performed 2 jobs in one: it acted as a choke, filtering the power supply, and it produced the magnetic field to operate the speaker.

REGULATOR IC (78XX)

It is a three pin IC used as a voltage regulator. It converts unregulated DC current into regulated DC current.

Normally we get fixed output by connecting the voltage regulator at the output of the filtered DC (see in above diagram). It can also be used in circuits to get a low DC voltage from a high DC voltage (for example we use 7805 to get 5V from 12V). There are two types of voltage regulators 1. fixed voltage regulators (78xx, 79xx) 2. variable voltage regulators (LM317) In fixed voltage regulators there is another classification 1. +ve voltage regulators 2. -ve voltage regulators POSITIVE VOLTAGE REGULATORS This include 78xx voltage regulators. The most commonly used ones are 7805 and 7812. 7805 gives fixed 5V DC voltage if input voltage is in (7.5V, 20V).

The CAPACITOR FILTER The simple capacitor filter is the most basic type of power supply filter. The application of the simple capacitor filter is very limited. It is sometimes used on extremely high-voltage, lowcurrent power supplies for cathode ray and similar electron tubes, which require very little load current from the supply. The capacitor filter is also used where the power-supply ripple frequency is not critical; this frequency can be relatively high. The capacitor (C1) shown in figure 4-15 is a simple filter connected across the output of the rectifier in parallel with the load.

Full-wave rectifier with a capacitor filter. When this filter is used, the RC charge time of the filter capacitor (C1) must be short and the RC discharge time must be long to eliminate ripple action. In other words, the capacitor must charge up fast, preferably with no discharge at all. Better filtering also results when the input frequency is high; therefore, the full-wave rectifier output is easier to filter than that of the half-wave rectifier because of its higher frequency. For you to have a better understanding of the effect that filtering has on Eavg, a comparison of a rectifier circuit with a filter and one without a filter is illustrated in views A and B of figure 4-16. The output waveforms in figure 4-16 represent the unfiltered and filtered outputs of the half-wave rectifier circuit. Current pulses flow through the load resistance (R L) each time a diode conducts. The dashed line indicates the average value of output voltage. For the halfwave rectifier, Eavg is less than half (or approximately 0.318) of the peak output voltage. This value is still much less than that of the applied voltage. With no capacitor connected across the output of the rectifier circuit, the waveform in view A has a large pulsating component (ripple) compared with the average or dc component. When a capacitor is connected across the output (view B), the average value of output voltage (Eavg) is increased due to the filtering action of capacitor C1. UNFILTERED

Half-wave rectifier with and without filtering.

FILTERE

The value of the capacitor is fairly large (several microfarads), thus it presents a relatively low reactance to the pulsating current and it stores a substantial charge. The rate of charge for the capacitor is limited only by the resistance of the conducting diode, which is relatively low. Therefore, the RC charge time of the circuit is relatively short. As a result, when the pulsating voltage is first applied to the circuit, the capacitor charges rapidly and almost reaches the peak value of the rectified voltage within the first few cycles. The capacitor attempts to charge to the peak value of the rectified voltage anytime a diode is conducting, and tends to retain its charge when the rectifier output falls to zero. (The capacitor cannot discharge immediately.) The capacitor slowly discharges through the load resistance (RL) during the time the rectifier is non-conducting. The rate of discharge of the capacitor is determined by the value of capacitance and the value of the load resistance. If the capacitance and load-resistance values are large, the RC discharge time for the circuit is relatively long. A comparison of the waveforms shown in figure 4-16 (view A and view B) illustrates that the addition of C1 to the circuit results in an increase in the average of the output voltage (E avg) and a reduction in the amplitude of the ripple component (Er) which is normally present across the load resistance.

Now, let's consider a complete cycle of operation using a half-wave rectifier, a capacitive filter (C1), and a load resistor (RL). As shown in view A of figure 4-17, the capacitive filter (C1) is assumed to be large enough to ensure a small reactance to the pulsating rectified current. The resistance of RL is assumed to be much greater than the reactance of C1 at the input frequency. When the circuit is energized, the diode conducts on the positive half cycle and current flows through the circuit, allowing C1 to charge. C1 will charge to approximately the peak value of the input voltage. (The charge is less than the peak value because of the voltage drop across the diode (D1)). In view A of the figure, the heavy solid line on the waveform indicates the charge on C1. As illustrated in view B, the diode cannot conduct on the negative half cycle because the anode of D1 is negative with respect to the cathode. During this interval, C1 discharges through the load resistor (RL). The discharge of C1 produces the downward slope as indicated by the solid line on the waveform in view B. In contrast to the abrupt fall of the applied ac voltage from peak value to zero, the voltage across C1 (and thus across RL) during the discharge period gradually decreases until the time of the next half cycle of rectifier operation. Keep in mind that for good filtering, the filter capacitor should charge up as fast as possible and discharge as little as possible. Figure 4-17A. - Capacitor filter circuit (positive and negative half cycles). POSITIVE HALFCYCLE

Figure 4-17B. - Capacitor filter circuit (positive and negative half cycles). NEGATIVE HALF-CYCLE

Since practical values of C1 and RL ensure a more or less gradual decrease of the discharge voltage, a substantial charge remains on the capacitor at the time of the next half cycle of operation. As a result, no current can flow through the diode until the rising ac input voltage at the anode of the diode exceeds the voltage on the charge remaining on C1. The charge on C1 is the cathode potential of the diode. When the potential on the anode exceeds the potential on the cathode (the charge on C1), the diode again conducts, and C1 begins to charge to approximately the peak value of the applied voltage. After the capacitor has charged to its peak value, the diode will cut off and the capacitor will start to discharge. Since the fall of the ac input voltage on the anode is considerably more rapid than the decrease on the capacitor voltage, the cathode quickly become more positive than the anode, and the diode ceases to conduct. Operation of the simple capacitor filter using a full-wave rectifier is basically the same as that discussed for the half-wave rectifier. Referring to figure 4-18, you should notice that because one of the diodes is always conducting on. either alternation, the filter capacitor charges and discharges during each half cycle. (Note that each diode conducts only for that portion of time when the peak secondary voltage is greater than the charge across the capacitor.) Figure 4-18. - Full-wave rectifier (with capacitor filter).

Another thing to keep in mind is that the ripple component (E r) of the output voltage is an ac voltage and the average output voltage (Eavg) is the dc component of the output. Since the filter capacitor offers relatively low impedance to ac, the majority of the ac component flows through the filter capacitor. The ac component is therefore bypassed (shunted) around the load resistance, and the entire dc component (or Eavg) flows through the load resistance. This statement can be clarified by using the formula for XC in a half-wave and full-wave rectifier. First, you must establish some values for the circuit.

As you can see from the calculations, by doubling the frequency of the rectifier, you reduce the impedance of the capacitor by one-half. This allows the ac component to pass through the capacitor more easily. As a result, a full-wave rectifier output is much easier to filter than that of a half-wave rectifier. Remember, the smaller the XC of the filter capacitor with respect to the load resistance, the better the filtering action. Since

the largest possible capacitor will provide the best filtering.

Remember, also, that the load resistance is an important consideration. If load resistance is made small, the load current increases, and the average value of output voltage (Eavg) decreases. The RC discharge time constant is a direct function of the value of the load

resistance; therefore, the rate of capacitor voltage discharge is a direct function of the current through the load. The greater the load current, the more rapid the discharge of the

capacitor, and the lower the average value of output voltage. For this reason, the simple capacitive filter is seldom used with rectifier circuits that must supply a relatively large load current. Using the simple capacitive filter in conjunction with a full-wave or bridge rectifier provides improved filtering because the increased ripple frequency decreases the capacitive reactance of the filter capacitor.

CHAPTER 5
CONCLUSION

CONCLUSION
The application of UART employs the programming of each of the units within it.The programming is done in Verilog because Verilog employs gate level programming. The gate level programming is the easiest among the four level of programming .Moreover the syntax for Verilog is quite simple and similar in structure to C. The use of Modelsim simulator ensures that all the programs for the respective modules are simulated and the errors are detected. The ensuing waveform gives the functioning of the respective module. The UART functioning can be studied through these codes for the modules and visualized through Modelsim. It is the software implementation of data conversion between CPU and any external device.

5.1. Future Aspects

This project deals with the software implementation of UART. The future advancements in this field can be the implementation of a Dual UART. This is done by implementing two UARTs on a single chip. Moreover there can be an improvement in the Baud Rate of the transmitting and receiving modules.

APPENDIX

Receiver Block
module receiver(clk16, xrst, xcs, xrd, rx_rdy, rx_d, perr, data_out); input clk16, xrst, xcs, xrd, rx_d; output rx_rdy, perr; output [7:0] data_out; wire fifo_en, fifo_wr, fifo_rd, fifo_full, fifo_empty, receive, shift_en, parallel_out, in_reg_en, in_reg_data, stb_dcc, stb_dci, stb_pcc, stb_pci, perr_out, perr_data; wire [7:0] shift_out, fifo_in; wire [3:0] dc_out; rx_fifo R1 (.fifo_in(shift_out), .clk16(clk16), .fifo_en(fifo_en), .fifo_wr(fifo_wr),

.fifo_rd(fifo_rd), .xcs(xcs), .xrst(xrst), .fifo_full(fifo_full), .fifo_empty(fifo_empty), .fifo_out(data_out)); rx_shifter S1(.clk16(clk16), .parallel_out(parallel_out), .receive(receive), .shift_en(shift_en), .xcs(xcs), .xrst(xrst), .stb_dcc(stb_dcc), .stb_dci(stb_dci), .dc_out(dc_out), .shift_in(in_reg_data), .shift_out(fifo_in)); input_reg O1(.clk16(clk16), .xcs(xcs), .in_reg_out(in_reg_data), .in_reg_en(in_reg_en), .rx_d_in(rx_d)); rx_parity_counter P1 (.perr_in(perr_data), .clk16(clk16), .stb_pcc(stb_pcc), .stb_pci(stb_pci), .xcs(xcs), .xrst(xrst), .perr_out(perr_out)); rx_control RU1 (.clk16(clk16), .xrst(xrst), .xcs(xcs), .xrd(xrd), .in_reg_out(in_reg_out), .in_reg_en(in_reg_en), .shift_en(shift_en), .fifo_en(fifo_en), .fifo_wr(fifo_wr), .fifo_rd(fifo_rd), .fifo_full(fifo_full), .fifo_empty(fifo_empty), .parallel_out(parallel_out), .receive(receive), .stb_dcc(stb_dcc), .stb_dci(stb_dci), .stb_pcc(stb_pcc), .stb_pci(stb_pci), .dc_out(dc_out),

.perr_data(perr_data), .perr_out(perr_out), .perr(perr), .rx_d(in_reg_data), .rx_rdy(rx_rdy)); endmodule

Receiver Control Unit

module rx_control(clk16, xrst, xcs, xrd, in_reg_out, in_reg_en, shift_en, fifo_en, fifo_wr, fifo_rd, fifo_full, fifo_empty, parallel_out, receive, stb_dcc, stb_dci, stb_pcc, stb_pci, dc_out, perr_data, perr_out, perr, rx_d, rx_rdy); input clk16, xrst, xcs, xrd, in_reg_out, fifo_full, fifo_empty, perr_out, rx_d; input [3:0] dc_out; output reg fifo_en, fifo_wr, fifo_rd, in_reg_en, shift_en, receive, parallel_out, stb_dcc, stb_dci, stb_pcc, stb_pci, rx_rdy,

perr_data, perr; reg start_bit, stop_bit; integer count; always@(posedge clk16) begin start_bit=1'd1; stop_bit=1'd0; if(xrst==1'd1) begin shift_en=1'd0; in_reg_en=1'd0; fifo_en=1'd0; stb_pcc=1'd1; stb_dcc=1'd1; count=0; start_bit=1'd1; stop_bit=1'd0; end else if(xrd==1'd0) begin if(fifo_empty==1'd0) begin fifo_en=1'd1; fifo_rd=1'd1; end else rx_rdy=1'd1; end else if(xrd==1'd1 ) begin if (rx_d==1'd1) count=count+1; else if(count>0 && count<9) begin in_reg_en=1'd1; shift_en=1'd1; receive=1'd1; stb_pci=1'd1; stb_dci=1'd1; perr_data=rx_d; count=count+1;

end else if(count==9) begin in_reg_en=1'd1; if(rx_d==perr_out) perr=1'd1; else perr=1'd0; count=count+1; end else if(count==10 && rx_d==1'd0) begin parallel_out=1'd1; fifo_en=1'd1; fifo_wr=1'd1; count=0; end end end endmodule

Receiver Fifo
module rx_fifo(fifo_in, clk16, fifo_en, fifo_wr, fifo_rd, xcs, xrst, fifo_full, fifo_empty, fifo_out); input clk16, fifo_en, fifo_wr, fifo_rd, xcs, xrst; input [7:0] fifo_in; output reg [7:0] fifo_out; output reg fifo_full, fifo_empty; reg [7:0] fifo [7:0]; integer wr,rd;

always@(posedge clk16) begin if(xrst==1'd1) begin fifo[0]=8'd0; fifo[1]=8'd0; fifo[2]=8'd0; fifo[3]=8'd0; fifo[4]=8'd0; fifo[5]=8'd0; fifo[6]=8'd0; fifo[7]=8'd0; wr=0; rd=0; end else if(fifo_en==1'd1) begin if(fifo_wr==1'd1 && wr<7)

begin fifo[wr]=fifo_in; wr=wr+1; end else if(fifo_wr==1'd1 && wr==7) fifo_full=1'd1; else if(fifo_rd==1'd1 && rd>0) begin fifo_out=fifo[rd]; rd=rd-1; end else if(fifo_rd==1'd1 && rd==0) fifo_empty=1'd1; end end endmodule

Receiver Shifter
module rx_shifter(clk16, parallel_out, receive, shift_en, xcs, xrst, stb_dcc, stb_dci, dc_out, shift_in, shift_out); input clk16, parallel_out, receive, xcs, xrst, stb_dci, stb_dcc, shift_en; input shift_in; reg [7:0] temp; output reg [7:0] shift_out; output reg [3:0] dc_out; reg [3:0] i; always@(posedge clk16) begin if(xcs==1'd1) begin if (xrst==1'd1) begin temp=8'd0; shift_out=8'd0; i=4'd0; end else if(shift_en==1'd1) begin if(parallel_out==1'd1) shift_out=temp; else if(receive==1'd1 && i<8) begin temp[i]=shift_in; i=i+1;

if(stb_dcc==1'd1) dc_out=4'd0; else if(stb_dci==1'd1) dc_out=i; end else if(receive==1'd1 && i==8) begin i=4'd0; if(stb_dcc==1'd1) dc_out=4'd0; else if(stb_dci==1'd1) dc_out=i; end end end end endmodule

Receiver Parity Counter

module rx_parity_counter(perr_in, clk16, stb_pcc, stb_pci, xcs, xrst, perr_out); input clk16, stb_pcc, stb_pci, xcs, xrst;

input perr_in; reg temp; output perr_out; reg p; always@(posedge clk16) begin if(xrst==1'd1) begin temp=1'd0; p=1'd0; end else if(stb_pcc==1'd1) begin p=1'd0; end else if(stb_pci==1'd1) begin temp=perr_in; p=p^temp; end end assign perr_out=(p==1)?1'd0:1'd1; endmodule

Receiver Input Register

module input_reg(clk16, xcs, in_reg_out, in_reg_en, rx_d_in); input clk16, xcs, in_reg_en, rx_d_in; output in_reg_out; reg temp; always@(posedge clk16) begin if(in_reg_en==1'd1) temp=rx_d_in; end assign in_reg_out=(xcs==1'd1)?temp:1'dz; endmodule

CPU Interface Block

CPU Interface Unit
module cpu_iu(rxfifo_out, clk16, perr, rx_rdy, tx_rdy, xcs, xrst, xrd, xwr, txfifo_out, xcs1, xint, x_rd, x_wr, data_buff_reg); input clk16, perr, rx_rdy, tx_rdy, xcs, xrst, xrd, xwr; input [7:0] rxfifo_out; reg [2:0] en_reg ; reg [2:0] st_reg ;

output reg x_rd, x_wr, xcs1, xint; output reg [7:0] txfifo_out; reg [7:0] temp; inout [7:0] data_buff_reg; always@(posedge clk16) begin if(xcs==1'd1) xcs1=1'd1; else if(xrst==1'd1)

begin st_reg=3'd0; en_reg=3'd0; temp=8'd0; end else if(xwr==1'd1) begin x_wr=1'd1; x_rd=1'd1; txfifo_out=temp; end else if(xrd==1'd1) begin x_wr=1'd0; x_rd=1'd0; temp= rxfifo_out; end end assign data_buff_reg=temp; always@(posedge clk16) begin st_reg[0]= rx_rdy; st_reg[1]= tx_rdy; st_reg[2]= perr; if(xwr==1'd1) begin case(st_reg) 3'b001:en_reg=3'b000; 3'b000:en_reg=3'b001; 3'b101:en_reg=3'b100; endcase end else if(xrd==1'd1) begin case(st_reg) 3'b010:en_reg=3'b000; 3'b000:en_reg=3'b010; endcase end if(en_reg==3'b010 || en_reg==3'b100 || en_reg==3'b001) xint=1'd1; else xint=1'd0; end endmodule

Main Block
module main_block(clk16, rx_d, xcs, xrd, xrst, xwr, tx_d, xint, cpu_data); input clk16, rx_d, xcs, xrd, xrst, xwr; output tx_d, xint; inout [7:0] cpu_data; wire perr, tx_rdy, rx_rdy, x_wr1, x_rd1, xrst, x_cs1, tx_d, rx_d; wire [7:0] rxfifo_out, data_out, txfifo_out, data_in; cpu_iu C1 (.rxfifo_out(data_out), .clk16(clk16), .perr(perr), .rx_rdy(rx_rdy), .tx_rdy(tx_rdy), .xcs(xcs), .xrst(xrst), .xrd(xrd), .xwr(xwr), .txfifo_out(data_in), .xcs1(x_cs1), .xint(xint), .x_rd(x_rd1), .x_wr(x_wr1),

.data_buff_reg(cpu_data)); transmitter T1 (.data_in(txfifo_out), .clk16(clk16), .xcs(x_cs1), .xrst(xrst), .xwr(x_wr1), .tx_d(tx_d), .tx_rdy(tx_rdy)); receiver R1 (.clk16(clk16), .xrst(xrst), .xcs(x_cs1), .xrd(x_rd1), .rx_rdy(rx_rdy), .rx_d(rx_d), .perr(perr), .data_out(rxfifo_out)); endmodule

REFERENCES
1. Palnetkar, Sameer, Verilog HDL- A Guide to Verilog Design And Synthesis, Mumbai: SunSoft Press,1996

2. Verilog design and Synthesis, Vol.Verilog, Networking Site, 1993

3. Archer, H.Y., Applied Simulation Processes , Journal Of Softwares,Vol.46, pp-2328; 1979