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A Voltage-Sensorless Control Method to Balance the Input Currents of a Three-Wire Boost Rectier Under Unbalanced Input Voltages Condition
Souvik Chattopadhyay and V. Ramanarayanan, Member, IEEE
AbstractThis paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectier under unbalanced input voltage condition. The control objective is to operate the rectier in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefcients of scaling and shifting functions are determined by two closed-loop prportionalintegral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instruments digital signal processor TMS320F240F is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectier under nominal and unbalanced input voltage conditions. Index TermsBoost rectier, current-mode control, highpower-factor rectiers, input current unbalance, input voltage unbalance, power-factor correction.

I. INTRODUCTION OR three-phase high-power-factor rectication, boost-type pulsewidth-modulation (PWM) converters are very widely used. The methods normally used for controlled rectication are based either on regulation of active and reactive current components in the synchronously rotating reference frame or on direct control of active and reactive power components by hysteresis type of controllers [1], [2]. Some of the proposed power-factor-correction methods are input voltage sensorless [3], [4]. Using these methods the output dc voltage of the rectier can be regulated and unity-power-factor operation with near-sinusoidal input current can be achieved. However, it is assumed in these methods that the input voltages both in terms of
Manuscript received December 30, 2003; revised February 13, 2004. Abstract published on the Internet January 13, 2005. S. Chattopadhyay is with the Department of Electrical Engineering, Indian Institute of Technology, Chennai 600036, India (e-mail: souvikc@ee.iitm.ernet.in. V. Ramanarayanan is with the Department of Electrical Engineering, Indian Institute of Science, Bangalore 560012, India (e-mail: vram@ee.iisc.ernet.in). Digital Object Identier 10.1109/TIE.2005.843917

Thevenin equivalent voltages and output impedances are balanced. If the input voltages of such a three-phase three-wire system, as shown in Fig. 1, are not balanced then they cause abnormal even harmonics in the output dc voltage and odd harmonics in the input line currents [5]. A few methods have been proposed [6][8] to solve the problem of harmonics under unbalanced input voltage condition. The objective of the method proposed in [6] is to balance the input currents. For that the input voltages are decomposed into symmetrical components so that the detected negative-sequence components can be added to the positive-sequence control voltages for balancing the currents. This method performs well, however, it requires input voltage sensing and the current balance function is basically executed in the open loop. Another method proposed in [7] computes the second-order harmonics in the dc bus and generates three independent current references that will cancel the even harmonics. In this method the input currents need not be balanced. It also needs input voltage sensing and the implementation is based on variable-switching-frequency operation. The method proposed in [8] is complex and achieves reduction instead of elimination of harmonics in the input current. In this paper a closed-loop input current balance control method for a three-phase three-wire boost rectier is proposed. The control objective is to operate the rectier in the high-power-factor mode under normal operating condition but to give overriding priority to the current balance function in case of unbalance in the input voltages. This control algorithm provides high performance with a much simpler control structure than the methods mentioned above. It does not require sensing of input voltages and is based on operation at xed switching frequency. It is suitable for digital implementation with the sampling frequency of the currents being equal to the switching frequency of the converter. The input impedances of the boost rectier need not be balanced as two independent closed-loop proportionalintegral (PI) controllers are used to balance the phase currents both in magnitude and in phase. The conditions for high-power-factor operation under unbalanced input voltage condition are given in Section II. The proposed digital control algorithm for balancing the input currents of a three-phase boost rectier is derived in Section III. The method for determination of scaling and phase shifting constants is given in Section IV. The simulation results are presented in Section V. Implementation of the algorithm in digital signal processor (DSP) TMS320F240 is described in Section VI. The experimental results of the three-phase boost

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Fig. 1 Circuit schematic of the digitally controlled three-phase high-power-factor boost rectier. Two input currents and the output dc voltage are sensed for current balance control. Input voltages are not sensed.

rectier are available in Sections VII and VIII is used for conclusion. II. HIGH-POWER-FACTOR OPERATION AND VOLTAGE UNBALANCE The schematic of a three-phase three-wire boost rectier is shown in Fig. 1. The phase voltages and the corresponding phase currents are indicated in the same gure as and , respectively. For high-power-factor operation phase currents should be made proportional to the phase voltages. The power-factor-correction objective in terms of space phasor quantities is dened as (1) where is the constant of proportionality representing the is the emulated resistance of the rectier. Mathematically, phasor of the input phase voltages, and is the phasor of the input phase currents. These quantities can be expressed as (2) (3) The components of input voltage and input current on the stareference frame are tionary and orthogonal and . We can use these variables to recast the control objective of (1) by two scalar equations (4) (5) It may be noted that if the phase voltages , and are and are phase shifted balanced then the components by 90 and their peak magnitudes are also equal. However, in and components case of unbalance, the corresponding will not retain the magnitude and phase relationship mentioned above. reference frame implementation of (4) and (5) In the and are by a current controller ensures that the currents
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Fig. 2. High-power-factor operation in balanced (v ; i ) and unbalanced (v voltage conditions.

;i

and

) (chosen arbitrarily) input

 -axes

variables under

and irrespective of the naproportional to the voltages ture of unbalance in the input voltages. The high-power-factor operation in - and -axes variables under balanced and unbalanced (chosen arbitrarily) input voltage conditions are shown in the space phasor diagram of Fig. 2. It can be noted that . Since for a three-phase three-wire system the input currents are given by

(6) (7) (8)

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Fig. 3. Block diagram of the input current balance controller.

TABLE I GENERATION OF RECTIFIED CURRENT VARIABLES

Fig. 4. Functional block diagram of the three-phase high-power-factor boost rectier represented by two independent single-phase rectiers in current-mode-control structure. Fig. 5. Voltage vectors produced by the PWM converter of Fig. 1 and the corresponding denition of Sectors.

The right-hand sides of (6)(8) show that the implementation of pro(4) and (5) will not make the phase currents because in general portional to the phase voltages .

This paper proposes a modication of the current control structure and adds the function of input current balance in the outer control loop. The current balance function in the controller

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     Fig. 6. Mapping of P ; Q; R; S vectors into M in Sector 1 of positive alphabeta axis for solution of T1 and T2. For example: A  vector Q.

and A

for

gets priority over the inner loop control objective of powerfactor correction. The block diagram of the closed-loop controller in shown in Fig. 3. The control method will be discussed in more detail in subsequent sections. With the implementation of current balance function the peak values of the phase currents will be equal in magnitude and their zero crossings will have 120 phase shift. It can simultaneously achieve unity-power-factor operation if the unbalanced phase voltages are at least balanced in phases, i.e., phase shifted by 120 ; in all other cases of unbalance unity-power-factor operation is not possible.

TABLE II ACTIVE VECTOR SELECTION CHART IN SECTORS 1, 3, 4, 6

of power-factor correction. The derivation of the control method is given below. The input voltages are assumed to be sinusoidal but unbalanced. Therefore, (9)

III. DIGITAL CONTROL ALGORITHM FOR BALANCING THE INPUT CURRENTS The objective of this section is to describe a voltage-sensorless digital current-mode control technique that would balance the input currents of a three-phase three-wire boost rectier under unbalanced phase voltage condition. The block diagram of the controller is shown in Fig. 3. It is inherently a current controller for high-power-factor operation. The objective of the inner such that they become loop is to shape the currents and then generate switching pulses proportional to by space-vector-modulation strategy. The digital current-mode control technique used here is input voltage sensorless and has been discussed in detail in [9]. The difference is that instead , as in [9], a scaled and phase-shifted current is of . This is done in order to balance made proportional to the input currents. The function of the outer loop of this controller is to make sure that the input currents are equal in magnitude and also phase shifted by 120 , irrespective of the kind of unbalance present in the phase voltages. Two closed-loop PI controllers impose the conditions for input current balance and, as a conseand under steady state. quence, produce two constants These constants are used to generate the current reference that is to be given as an input to the inner loop for making it . It can be seen that the structure of the conproportional to troller is such that under unbalanced condition the task of balancing the input currents gets priority over the default function

where (10) where is the phase difference between and . The phase voltages are unbalanced, therefore, in general, , and . The control objective of the input current balance controller is to satisfy (11) and (12) simultaneously (11) (12) In order to balance the input phase currents and still retain the basic function of power-factor correction the controller makes and a new variable , instead of , proportional to and , respectively, as in (13) is then given by (14) can be expressed as a linear combination of the currents and

(15)

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     Fig. 7. Mapping of A; B; C ; D vectors into N in Sector 2A of positive alphabeta axis for solution of T1 and T2. For example: A   vector A whereas A = V and A = V for Vector B mode controller.

= V and A

= V for

where (16) (17) and are obtained from the outputs of the two PI controllers that impose the conditions of current balance. and are constants under steady state. It may be noted that under and . balanced input voltage condition . This implies that Therefore, it follows from (13) that the closed-loop PI controllers will output and under balanced input voltage condition and will result in high-power-factor operation. The digital controller proposed in this paper calculates from the currents and using (15). For the th switching can, therefore, be expressed as period (18) where currents and and can be calculated from the sensed phase

TABLE III ACTIVE VECTOR SELECTION CHART IN SECTORS 2A, 2B, 5A, 5B

Fig. 8. Sequence of sector change to be followed to eventually synchronize with the location of voltage vector: for example if the voltage vector is in sector 5B and the initial assumption of sector is 3 then 3, 4, and 5A will not produce acceptable solution but the modulator will lock at sector 5B (A-B-C).

(19) (20) The control objective for the input current balance controller can be expressed in the sampled form as (21) (22) This, in essence, means that we can functionally represent a three-phase boost rectier by two independent single-phase boost rectiers as shown in Fig. 4. Using continuous-conduction-mode voltage conversion relationships of the boost
Fig. 9. Time phasor diagram of the control variables under three different ;i ); 2: unbalanced operating conditions. 1: Balanced input voltage (i ;i ); input voltage but without current balance function activated (i and 3: unbalanced input voltage but with current balance function activated (i ; i ; i ).

converters and in (21) and (22), the control law can be made input voltage

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Fig. 10. Flowchart of the control algorithm implemented in TMS320F240 DSP for current balance control on the outer loop of a resistor emulator-type input current-shaping controller.

sensorless. The duty ratios and converter switches

and of the two boost are given by (23) (24)

where is the output of the voltage error amis the current sense resistance as shown in Fig. 4. plier and It may be noted that and are positive quantities and obtained after rectication of the control variables . We generate and based on the sector information, as shown in Table I. It is well known that symmetric space-vector PWM technique is one of the convenient ways of producing switching signals for a three-phase PWM converter. Therefore, we have to convert the duty ratio information given by (23) and (24) to the space-vector PWM signals of

individual switches. For that purpose the voltage vectors and the corresponding sectors are dened as in Fig. 5. and , we have to nd out the time duraFrom and , for the two active vectors and tions to effectively produce the same volt-seconds on each axis as demanded by the independent boost rectier controllers. The reof the period should be used for the null maining time . From Fig. 6, it can be noted that if the active vecvector and for Sectors 1, 3, 4, and 6 are identied as in tors and , needed Table II, then the corresponding time for synthesis of any vector ( , or ) with an angle with respect to the axis of the segment, can be obtained by solving the following simultaneous equations: (25) (26)

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Fig. 11. Simulation results under balanced input voltage condition. The input current balance controller is active. (a) Scaled (0.1) v (b) Scaled (0.1) v ; v and i ; i . (c) K ; K .

;v

;v

and i

;i

;i

Similarly, for Sectors , and , as shown in Fig. 7, Table III gives the selection of vectors. The following simultaand : neous equations can be used to solve for

(27) (28)

and . Similarly, for the modulator to operate in the unsaturated region. When any one of these conditions is not satised, the next sector in sequence is chosen, as shown in Fig. 8. and we need to compute the time durations From , and by using (29)(33) of

(29) It can be seen that the input voltages need not be sensed for and . However, the sector information computation of should be known for appropriate selection of active vectors. This controller implements self-synchronization of the converter switching with respect to line voltage based on the following logic: as long as the sector selection is correct, the - and -axes modulators will produce duty ratios less than 1, i.e., (30) (31) (32) (33)

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Fig. 12.
i ;i ;i

Simulation results under unbalanced input voltage condition. The input current balance controller is not active. (a) Scaled (0.1) . (b) Scaled (0.1) v ; v and i ; i .

;v

;v

and

We will need the timing values computed above for DSP TMS320F240based implementation of the algorithm. This will be discussed in Section VI. IV. DETERMINATION OF
AND

The mathematical model of the three-phase converter circuit shown in Fig. 1 is based on the following equations: (34)

(35) It can be seen from (18) that the constants and should be known for the computation of . The conditions neces(36) and are imposed on two independent sary for balancing and . This closed-loop controllers in order to determine (37) is shown in the block diagram of Fig. 3. Under balanced con, over a line cycle, where dition peak value of the -axis current, , has to be equal to the peak value of the axis . This condition is imposed on one of the PI concurrent, (38) . trollers in order to determine (39) is obtained in a similar manner from the output of another (40) PI controller that basically imposes the phase balance condition. . It is dened as the -axis The input to this PI controller is (41) current sampled at the instant when the -axis current attains its positive peak value in a line cycle. Under balanced condiif Sw is ON and if Sw is OFF (42) should be zero, and this is dened as the zero-phase tion condition for . If due to some reason is positive in a increases as the integrator increments with a if Sw is ON and line cycle then if Sw is OFF (43) has to move positive slope, as a result of which the phase of toward 0 in subsequent cycles in order to satisfy (18). The nominal operating condition of the simulation model is Fig. 9 shows the time phasor diagram of , and to given below illustrate the action of the phase current balance controller. The owchart of the digital controller is shown in Fig. 10. V(rms) V. SIMULATION RESULTS The proposed input current balance controller for a threephase three-wire boost rectier is simulated on a MATLABSIMULINK (Version 5.3) platform. The simulation model of the digital controller is based on (18)(33) described in Section III of this paper. V(dc-regulated) mH s

It can be noted that the control function to balance the input currents of the rectier remains active all the time in the outer

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Fig. 13. Simulations result under unbalanced input voltage condition. The input current balance controller is active. (a) Scaled (0.1) v (b) Scaled (0.1) v ; v and i ; i (c) K ; K .

;v

;v

and i

;i

;i

TABLE IV TMS320F240 CMP REGISTER TIMING CHART

Fig. 14. Generation of symmetric PWM pulses in the Event Manager Module of DSP TMS320F240.

loop of the control structure. It does not interfere with the power-factor-correction objective of the inner control loop if

the input voltages are balanced. This is shown in Fig. 11(a) , and in Fig. 11(a) and and in and (b), as Fig. 11(b) are balanced in magnitude and phase. It can be seen and , the constants that are the from Fig. 11(c) that outputs of two independent PI controllers, achieve steady-state values that are nearly equal to 0 and 1, respectively, implying . that

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Fig. 15. Experimental results with the current balance controller under normal input voltage condition. (a) v (Ch4: 300 V/div) and i ; i ; i (Ch1, Ch2, Ch3: 3.2 A/div). (b) v (Ch4: 300 V/div), i ; i (Ch1, Ch2: 8 A/div) and V (Ch3: 270 V/div). (c) v (Ch1: 300 V/div) and K ; K (Ch2, Ch3: 1/div). (d) i ; i (Ch1, Ch2: 8 A/div) and Sector (Ch3: 4/div).

In this simulation the unbalanced input voltages are chosen arbitrarily as . Under such a condition if the current balance control is not used then Fig. 12(a) shows the waveforms of scaled input voltages and input currents , and Fig. 12(b) shows the waveforms of scaled -axes voltages and the currents . It can be seen that although unbalanced -axes voltages and currents satisfy high-power-factor operation, the input phases currents are not proportional to the input voltages. The simulation results shown in Fig. 13(a) and (b) are obtained with the current balance controller activated. It can be seen that although the voltages are unbalanced the phase currents ( , and ) are balanced. The PI controllers

and that are different from 0 and 1, produce values of respectively. This is shown in Fig. 13(c). The magnitude of the phase-shifted current is determined by the dc voltage error amplier. VI. IMPLEMENTATION IN DSP TMS320F240 The calculated timing values of (29)(33) are required for loading the compare registers of TMS320F240a DSP controller that is for implementation of the current balance control algorithm as described above. The Event Manager Module (EVM) in the peripheral library of TMS320F240 provides necessary hardware support for the generation of PWM pulses for the switching devices of the three-phase boost rectier.

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Fig. 16. Experimental results without the current balance controller under unbalanced input voltage condition. (a) v Ch2, Ch3: 3.2 A/div). (b) v (Ch4: 300 V/div), i ; i (Ch1, Ch2: 8 A/div) and V (Ch3: 270 V/div).

(Ch4: 300 V/div) and i

;i

;i

(Ch1,

The generation of switching signals for individual devices is shown as an example in Fig. 14. It corresponds to the Sector 1 of the space-vector modulation. The general-purpose (GP) timer 1 of the Event Manager Module [10] is congured in the initialization part of the program to work in the continuous updown counting mode for the generation of symmetric PWM waveforms. In this implementation the timer 1 is clocked by CPU clock CPUCLK at 20 MHz. The timer 1 in the updown counting mode generates a triangle waveform of frequency 10 kHz. For that, the timer 1 period register T1PR is loaded with a constant , corresponding to 50 s. The execution of the control loop is initiated by the GP timer 1 underow interrupt while counting down, i.e., when the timer counter reaches 0000H. In each underow interrupt the dual 10-bit analog-to-digital converter module (ADC) of the TMS320F240 measures two phase currents. The current conversions are simultaneous in the two ADCs, thus requiring a total conversion time of s. The outer loop consisting of two PI controllers for the determination of and another PI controller for regulation of are executed in the ratio of 1 : 10 to the inner control loop. The values that need to be loaded to the three compare registers CMP1, CMP2, and CMP3 for the entire line cycle of the input voltage waveform are given in Table IV. Necessary adjustments to the basic ON and OFF times of each switch are performed in the Dead Band units. The switch dead time is controlled by dead-time control register DBTCON. The output PWM pulses are obtained by comparison of values in timer 1 counter register T1CNT and the compare registers CMPR1-2-3. The Output Logic units of the Event Manager Module determine the logic level, i.e., active high or active low, of each PWM output. The six output signals are available on dedicated PWM output pins PWM1PWM6. If an odd-numbered pin is used for driving the top device then the corresponding even-numbered pin should be used for the bottom device.

VII. EXPERIMENTAL RESULTS The nominal operating point of the experimental boost rectier when the phase voltages are very nearly balanced is as follows: phase V rms star V dc regulated mH s

It may also be assumed that the per-phase boost inductances are very nearly equal. The experimental results of the rectier under balanced input voltage condition are shown in Fig. 15. are balFig. 15(a) shows that the phase currents -axes currents in Fig. 15(b). anced, and so are is well regulated Fig. 15(c) shows that the output dc voltage at reference value. We expect that high-power-factor operation should be possible under balanced input voltage condition and and waveforms shown in Fig. 15(a) this is proved by the that are in phase. Fig. 15(d) shows the steady-state values of and the sequence of Sector change. As the constants expected, the constants are 0 and 1, respectively, and each step of the sector change waveform is equal indicating that the phase voltages are balanced. These results demonstrate that the current balance controller does not interfere with the power-factor-correction objective under balanced input voltage condition. In order to verify the effectiveness of the current balance controller we create an unbalance in the input phase voltages by changing the equivalent Thevenin impedance of one of the input source voltages. In this experimental unit we have added and mH in sean impedance made of ries with the phase- supply line of the rectier. At rst, we do not activate the current balance controller. Under such condition Fig. 16(a) and (b) shows that the currents and are unbalanced. By observing and we can infer that the power factor is not unity.

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Fig. 17. Experimental results with the current balance controller under unbalanced input voltage condition. (a) v (Ch4: 300 V/div) and i ; i ; i (Ch1, Ch2, Ch3: 3.2 A/div). (b) v (Ch4: 300 V/div), i ; i (Ch1, Ch2: 8 A/div) and V (Ch3: 270 V/div). (c) v (Ch1: 300 V/div) and K ; K (Ch2, Ch3: 1/div). (d) i ; i (Ch1, Ch2: 8 A/div) and Sector (Ch3: 4/div). (e) i ; i , and i (Ch1, Ch2, Ch3: 8 A/div).
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We then activate the current balance controller in the outer loop of the control structure. The experimental results of Fig. 17(a) are now balanced, show that the phase currents but, as expected, the power factor is not unity in phase . -axes currents are also balanced Fig. 17(b) shows that and is regulated. Fig. 17(c) shows that the constants have changed due to the actions of the PI controllers in order to balance the input currents. We expect that the internal current but it should not should be in phase with variable , as shown by the waveforms of be equal in magnitude to Fig. 17(d). In the same gure it can be noted that Sector change steps are not equal, indicating that the input voltages are unbalanced. Fig. 17(e) shows the currents together for easy comparison of magnitudes. These results validate the analysis of unbalance. VIII. CONCLUSION This paper has proposed a simple control method that can balance the input currents of a three-phase three-wire boost rectier under unbalanced input voltage condition. The controller performs high-power-factor rectication under balanced input voltage condition. However, if the input voltages are unbalanced then priority is given to the implementation of the current balance function. The controller has two basic functional loops. The inner loop implements resistor emulator-type current-shaping strategy on , and on the scaled and phase-shifted current . The outer loop scales and phase shifts the -axis current in order to , supplied as a reference to the inner loop curproduce and . The rent-shaping controller, using the coefcients scaling and phase-shifting coefcients are determined by two closed-loop PI controllers that impose the conditions of input current balance as PI references. The control technique is input voltage sensorless and suitable for xed-switching-frequency digital implementation. It is computationally simplethe execution time of the control loop is less than 40 s on a TMS320F240 that is clocked at 20 MHz and this 40 s includes the ADC conversion time of 13.2 s. The proposed control method, being a closed-loop current balance method, is insensitive to the unbalance in the circuit component valueslike boost inductance in each phase. In conclusion, it can be said that the method proposed in this paper for balancing the input currents of a three-phase three-wire boost rectier is simpler in implementation compared to other input current balance methods but provides equal or better performance. REFERENCES
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Souvik Chattopadhyay received the B.E. degree from Bengal Engineering College, Howrah, India, in 1988, and the M.Sc.(Eng.) and Ph.D. degrees from the Indian Institute of Science, Bangalore, India, in 1990 and 2002, respectively. He is currently an Assistant Professor in the Department of Electrical Engineering, Indian Institute of Technology, Chennai, India. Between 19911995, he was with M/s Crompton Greaves Ltd., Bombay, India, as a Research and Development Engineer in the Power Electronics Group of R&D (Electricals). Between 19961998, he was with M/s Cegelec India Ltd., Delhi, India, as a Project EngineerIndustrial Drives. He was a part of the commissioning team for phase IV modernization of the TISCO Hot Strip Mill, Jamshedpur, India. His research interests include design, analysis, control, and modeling of power converters for PFC circuits and active lter systems.

V. Ramanarayanan (M05) received the B.E. degree from the University of Madras, Madras, India, in 1970, the M.E. degree from the Indian Institute of Science, Bangalore, India, in 1975, and the Ph.D. degree from California Institute of Technology, Pasadena, in 1986. He is a Professor and Chairman of the Department of Electrical Engineering, Indian Institute of Science, Bangalore, India. He has held positions in industry as a Senior Design Engineer and Chief of R&D with M/s Larsen and Toubro Ltd. (19701979) and NGEF Ltd. (19791982). His areas of interest are power electronics, industrial drives, switched-mode power conversion, and power quality issues. He is a Consultant to several industries in related areas.

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