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ENCOUNTER TEST

AIM:
Aim of the experiment is to :
1. Launch the encounter test
2. Generate the fault models and to verify the percentage of fault coverage i.e., the
number of faults detected and undetectable faults
3. Generate the test vectors in verilog format and store the generated test vectors in
test results.

PROCEDURE:
1. Launch the encounter test by typing et & in the present working directory.
2. A new pop up window opens from where we can create encounter test
environment
3. The following steps are to be followed :
File > new > <working directory>
File > new > <top module name>
4. First go for the verification in which we could choose built model and then
model
Verification > built model > model
5. A new pop up window opens in which we should browse the top module name
and typical.v file.
home/11mvd0056/lab1/asiclab
home/07mvd/rclabs/library/typical.v
6. Next is to go for verification in which we could choose built model and then
test mode is selected from it.
Verification >built model >testmode
7. A new pop up window opens in which we could select the type of scan and the
.atpg file
name > FULLSCAN
pin assignment file > home/11mvd0056/lab1/asiclab.atpg
8. Next step is to go for verify in which we could select the test structures
Verify > test structures
9. A new pop up window opens in which we could select the effort level as
medium
10. For generating the test vectors and verifying the fault coverage the following
steps are to be followed:
ATPG > create tests >specific structures > scan chain
ATPG > create tests >specific structures > logic
11. For generating the test vectors in verilog format ,this step is for generating
patterns for simulation verification. It can be with committed patterns or just
experiments that have been
run and not committed.
o Pulldown menu APTG -> Write Vectors
o Test mode name : FULLSCAN

o Vectors to write : UnCommitted Vectors input Experiment name


Select the Experiment name from the pull down and you will see that logic is the
only one available.
o Language : Verilog
o Notice you can select the Scan format of serial or parallel. This controls how the
scan chains are loaded during simulation. Parallel load format is much faster.

RESULTS:
Testmode statistics prior to commit_tests
#Faults #Tested
TotalStatic 1155
0
TotalDynamic 1092
0

#Untested %TCov %ATCov


1152
0.00
0.00
1092
0.00
0.00

%PCov %APCov
0.00
0.00
0.00
0.00

Testmode statistics after commit_tests


#Faults #Tested #Untested %TCov %ATCov
Total Static
1155
233
922
20.17 20.17
Total Dynamic 1092
0
1092
0.00
0.00

%PCov %APCov
20.17 20.17
0.00
0.00

Statistics for faults that are not active in any test modes and
maximum test coverage attainable with the current set of test modes:
Total
Total Static
Total Dynamic
Collapsed
Collapsed Static
Collapsed Dynamic
Pin
Pin Static
Pin Dynamic
Collapsed Pin
Collapsed Pin Static
Collapsed Pin Dynamic
PI
PI Static
PI Dynamic
PO
PO Static
PO Dynamic
Pattern
Shorted Net
Drvr/Rcvr

#Faults
2314
1162
1152
1745
779
966
2314
1162
1152
1745
779
966
44
22
22
79
41
38
0
0
0

#Active #Inactive %Active


2247
67
97.10
1155
7
99.40
1092
60
94.79
1678
67
96.16
772
7
99.10
906
60
93.79
2247
67
97.10
1155
7
99.40
1092
60
94.79
1678
67
96.16
772
7
99.10
906
60
93.79
42
2
95.45
22
0
100.00
20
2
90.91
79
0
100.00
41
0
100.00
38
0
100.00

Circuit Summary
--------------Hierarchical Model:
1018 Blocks
3083 Pins
1777 Nets

Flattened Model:
455 Blocks
455 Nodes

Primary Inputs:
12 Input Only
0 Input/Output
12 Total Inputs

Primary Outputs:
22 Output Only
0 Input/Output
22 Total Outputs

Tied Nets:
1
9
0
10

Dotted Nets:
0 Two-State
0 Three-State
0 Total Dotted Nets

Tied to 0
Tied to 1
Tied to X
Total Tied Nets

Selected Primitive Functions:


0 Clock Chopper (CHOP) primitives
0 RAMs
0 ROMs
0 TSDs
0 Resistors
0 Transistors
15 MUX2s
0 Latches
22 Flip-Flops
Optimization removed logic for 2 of 29 cells in this design.
Optimization removed a total of 60 tied Latch Ports.
Optimization removed a total of 97 non-controlling inputs.
Optimization removed a total of 325 dangling logic nodes.
Build Model - Flat Model Build completed.

Testmode contains 99.78% active logic,0.22% inactive logic and


0.00% constraint logic.
There are 1 scan chains which are controllable and observable.

Generated test vectors in verilog format:


100 // Encounter(R) Test and Diagnostics 9.1.103 Jun 29, 2010 (linux26
ET911)
100 // FILE CREATED..............March 20, 2012 at 13:43:30
203 Z
900 3.1.1.1.1.1
200 110XXXXXXXXX
201 XX0XXXXXXXXX
400
900 3.1.1.2.1.1
600 1 1 1
300 1 0101101101001001011011
600 1 2 22

900
900
900
200
400
901
200
202
400
200
400
900
200
400
901
200
202
400
200
400
900
200
400
901
200
202
400
200
400
900
200
400
901
200
202
400
200
400
900
200
400
901
200
202
400
200
400
900
200
400
901
200
202
400
200
400
900

3.1.1.2.1.2
3.1.1.2.1.3
3.1.1.2.1.4
111000000001
3.1.1.2.1.4
110111011111
0111111001001011011011
111111011111
3.1.1.2.1.5
111111101111
3.1.1.2.1.5
110110011100
0111111010010010110111
111110011100
3.1.1.2.1.6
111001000110
3.1.1.2.1.6
110111100100
0000110110100100101100
111111100100
3.1.1.2.1.7
111101011011
3.1.1.2.1.7
110111001001
0111111101101001001011
111111001001
3.1.1.2.1.8
111111011001
3.1.1.2.1.8
110100000011
0111111011011010010011
111100000011
3.1.1.2.1.9
111111111010
3.1.1.2.1.9
110010101010
0000110010110110100100
111010101010
3.1.1.2.1.10

200
400
901
200
202
400
200
400
900
900
200
600
301
300
901
600

111101001100

900
900
200
400
900
200
400
900
900
900
200
400
200
400
901
200
202
400
900
200
400
200
400
901
200
202
400
900
200
400
200
400
901
200
202
400
900
200
400
200
400

3.1.1.3.1.2
3.1.1.3.1.3
110001010101

3.1.1.2.1.10
110010011111
0000110100101101101000
111010011111
3.1.1.2.1.11
3.1.1.3.1.1
110010011111
1 1 1
1 0101101101001001011011
1 0111000111000111000111
3.1.1.2.1.11
1 2 22

3.1.1.3.1.4
111110001001
3.1.1.3.1.5
3.1.1.3.1.6
3.1.1.3.1.7
111110100000
111000101001
3.1.1.3.1.7
110110100011
0111111110001110001111
3.1.1.3.1.8
111110100011
111011111110
3.1.1.3.1.8
110101101111
0000110011100011100010
3.1.1.3.1.9
111101101111
111000110001
3.1.1.3.1.9
110101010010
0111111000111000111001
3.1.1.3.1.10
111101010010
111010110101

901
200
202
400
900
200
400
200
400
901
200
202
400
900
200
400
900
200
600
301
901
600

3.1.1.3.1.10
110111010011
0111111110001110001111
3.1.1.3.1.11
111111010011
111101110110
3.1.1.3.1.11
110101101101
0000110011100011100010
3.1.1.3.1.12
111101101101
3.1.1.3.1.13
110101101101
1 1 1
1 0111000111000111000111
3.1.1.3.1.13
1 2 22

200 11010110110X
400

RESULT:
The encounter test (et ) was launched ,fault models were generated and the percentage of
fault coverage i.e., the number of faults detected and undetectable faults was verified..Test
vectors in verilog format was generated and the generated test vectors in test results