CD54HC151, CD74HC151, CD54HCT151, CD74HCT151

Data sheet acquired from Harris Semiconductor SCHS150C

September 1997 - Revised October 2003

High-Speed CMOS Logic 8-Input Multiplexer

Description
The HC151 and HCT151 are single 8-channel digital multiplexers having three binary control inputs, S0, S1 and S2 and an active low enable (E) input. The three binary signals select 1 of 8 channels. Outputs are both inverting (Y) and non-inverting (Y).

Features
Complementary Data Outputs

[ /Title (CD74H C151, CD74H CT151) /Subject (High Speed CMOS Logic 8Input Multi-

Buffered Inputs and Outputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs Alternate Source is Philips/Signetics HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH

Ordering Information
PART NUMBER CD54HC151F3A CD54HCT151F3A CD74HC151E CD74HC151M CD74HC151MT CD74HC151M96 CD74HCT151E CD74HCT151M CD74HCT151MT CD74HCT151M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufx 96 denotes tape and reel. The sufx T denotes a small-quantity reel of 250.

Pinout
CD54HC151, CD54HCT151 (CERDIP) CD74HC151, CD74HCT151 (PDIP, SOIC) TOP VIEW
I3 1 I2 2 I1 3 I0 4 Y 5 Y 6 E 7 GND 8 16 VCC 15 I4 14 I5 13 I6 12 I7 11 S0 10 S1 9 S2

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2003, Texas Instruments Incorporated

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Functional Diagram

4 3 2 I2 1 I3 15 I4 14 I5 13 I6 12 I7 S0 S1 S2 7 E GND = 8 VCC = 16 11 10 9 6 Y 5 Y

I0 I1

TRUTH TABLE SELECT INPUTS S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X DATA INPUTS I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H ENABLE E H L L L L L L L L L L L L L L L L OUTPUT Y H H L H L H L H L H L H L H L H L Y L L H L H L H L H L H L H L H L H

H = High Voltage Level, L = Low Voltage Level, X = Dont Care

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151

Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA

Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151

DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

VCC (V)

-4

4.5

3.98

3.84

3.7

0.02

4.5

0.1

0.1

0.1

4.5

0.26

0.33

0.4

0 0 -

5.5 5.5 4.5 to 5.5

100

0.1 8 360

1 80 450

1 160 490

A A A

HCT Input Loading Table

INPUT Select Data Enable UNIT LOADS 1.5 0.45 0.3

NOTE: Unit Load is ICC limit specied in DC Electrical Table, e.g., 360A max at 25oC.

Switching Specications Input tr, tf = 6ns

TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

PARAMETER HC TYPES Propagation Delay (Figure 1) Any Data Input to Y

SYMBOL

tPLH, tPHL CL = 50pF

2 4.5

14 -

170 34 29

215 43 37

255 51 43

ns ns ns ns

CL =15pF CL = 50pF

5 6

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151

Switching Specications Input tr, tf = 6ns
(Continued) 25oC VCC (V) 2 4.5 CL =15pF CL = 50pF Any Select to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Any Select to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Enable to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Enable to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay (Figure 2) Any Data Input to Y tPLH, tPHL CL = 50pF CL =15pF Any Data Input to Y tPLH, tPHL CL = 50pF CL =15pF Any Select to Y tPLH, tPHL CL = 50pF CL =15pF Any Select to Y tPLH, tPHL CL = 50pF CL =15pF Enable to Y tPLH, tPHL CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 17 18 12 16 15 38 36 41 43 29 45 51 54 36 48 57 54 62 65 44 ns ns ns ns ns ns ns ns ns ns CIN CPD 5 MIN TYP 15 15 17 11 12 59 MAX 185 37 31 185 37 31 205 41 35 140 28 24 145 29 25 75 15 13 10 -40oC TO 85oC MIN MAX 230 46 39 230 46 39 255 51 43 175 35 30 180 36 31 95 19 16 10 -55oC TO 125oC MIN MAX 280 56 48 280 56 48 310 62 53 210 42 36 220 44 38 110 22 19 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF

PARAMETER Any Data Input to Y

SYMBOL

TEST CONDITIONS

tPLH, tPHL CL = 50pF

CD54HC151, CD74HC151, CD54HCT151, CD74HCT151

Switching Specications Input tr, tf = 6ns
(Continued) 25oC VCC (V) 4.5 5 4.5 5 MIN 15 TYP 58 MAX 36 15 10 -40oC TO 85oC MIN MAX 46 19 10 -55oC TO 125oC MIN MAX 54 22 10 UNITS ns ns ns pF pF

PARAMETER Enable to Y

SYMBOL

TEST CONDITIONS

CL = 50pF CL = 50pF CL =15pF CL =15pF

Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES:

tTLH, tTHL CL = 50pF CIN CPD -

3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Test Circuit and Waveform

tr = 6ns ENABLE SELECT In tTHL Y OUTPUT tPLH tPHL Y OUTPUT tTHL tTLH tPLH tPHL VS tTLH tf = 6ns INPUT LEVEL 90% VS 10% GND 90% VS 10%

FIGURE 1.

PACKAGE OPTION ADDENDUM

www.ti.com

5-Sep-2011

PACKAGING INFORMATION
Orderable Device 5962-9065201MEA CD54HC151F3A CD54HCT151F3A CD74HC151E CD74HC151EE4 CD74HC151M CD74HC151M96 CD74HC151M96E4 CD74HC151M96G4 CD74HC151ME4 CD74HC151MG4 CD74HC151MT CD74HC151MTE4 CD74HC151MTG4 CD74HCT151E CD74HCT151EE4 CD74HCT151M CD74HCT151M96 CD74HCT151M96E4 CD74HCT151M96G4 Status
(1)

Package Type Package Drawing CDIP CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC J J J N N D D D D D D D D D N N D D D D

Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Package Qty 1 1 1 25 25 40 2500 2500 2500 40 40 250 250 250 25 25 40 2500 2500 2500

Eco Plan TBD TBD TBD

(2)

Lead/ Ball Finish Call TI A42 A42

MSL Peak Temp Call TI N / A for Pkg Type N / A for Pkg Type

(3)

Samples (Requires Login)

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Sep-2011

Orderable Device CD74HCT151ME4 CD74HCT151MG4 CD74HCT151MT CD74HCT151MTE4 CD74HCT151MTG4

Status

(1)

Package Type Package Drawing SOIC SOIC SOIC SOIC SOIC D D D D D

Pins 16 16 16 16 16

Package Qty 40 40 250 250 250

Eco Plan

(2)

Lead/ Ball Finish

MSL Peak Temp

(3)

Samples (Requires Login)

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC151, CD54HCT151, CD74HC151, CD74HCT151 :

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

5-Sep-2011

Catalog: CD74HC151, CD74HCT151 Military: CD54HC151, CD54HCT151

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC D D 16 16

SPQ

Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 16.4 16.4

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm) 8.0 8.0

W Pin1 (mm) Quadrant 16.0 16.0 Q1 Q1

CD74HC151M96 CD74HCT151M96

2500 2500

6.5 6.5

10.3 10.3

2.1 2.1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device CD74HC151M96 CD74HCT151M96

Package Type SOIC SOIC

Package Drawing D D

Pins 16 16

SPQ 2500 2500

Length (mm) 333.2 333.2

Width (mm) 345.9 345.9

Height (mm) 28.6 28.6

Pack Materials-Page 2

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