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Design and Analysis of a SwitchedCapacitor-Based Step-Up DC/DC Converter With Continuous Input Current
Henry Shu-hung Chung, Member, IEEE
Abstract This paper presents the use of the current control scheme in switched-capacitor (SC)-based step-up dc/dc converter. It not only includes all positive characteristics of previous SC converters, including small size, lightweight, high power density, and the amenability to IC hybridization, but also has the prominent features of continuous input current waveform and better regulation capability than the traditional SC converters. The problem of conducted electromagnetic interference with the supply network, which generally exists in previous SC converters, is highly suppressed. The concept of energy transfer is achieved by using dual SC step-up converter cells operating in antiphase. Each cell is switching between two topologies for same duration. The dc voltage conversion ratio is controlled by the current control scheme in order to adjust the charging prole of the capacitors. A generalized n-stage converter is presented and is analyzed by a simplied third-order state-space equation set. The static and dynamic behaviors and the design constraints of the converter are derived. A prototype of the 30 W 5 V=12 V twostage converter has been built, giving an overall efciency of 78% with power density of 15 W=in3 . Its stability of operation is also presented. Index Terms DCDC power conversion, switched capacitor circuits, switched mode power supplies.

I. INTRODUCTION HERE is an increasing demand for converters of small size lightweight, high efciency, and high power density. Recently, a new class of converters for low-power applications is proposed [1][14] where conversion of an unregulated input to a regulated output is accomplished by using switchedcapacitor (SC) circuits. They do not require any inductive element, but contain semiconductor switches (MOSFETs and diodes) and capacitors only, making it amenable to monolithic integration [12][14]. Starting from the prime idea of applying the basic SC cell [15] for power conversion, many methodologies of operating the switches and the capacitors, and the control schemes have been proposed. Each capacitor is basically going through a charging process from the supply and/or other capacitors and a discharging process to the load and/or other capacitors, periodically. Although SC converters exhibit many implementation advantages, they have some common drawbacks: 1) the input current is pulsating; 2) the regulation capability is weak since
Manuscript received February 4, 1997; revised October 20, 1998. This paper was recommended by Associate Editor A. Ioinovici. The author is with the City University of Hong Kong, Hong Kong. Publisher Item Identier S 1057-7122(99)04753-4.

the output voltage varies with the input voltage accordingly; and 3) the dc voltage conversion ratio is usually predetermined by circuit structure [16]. Lately, regulation capability of SC converters has improved [8][10]. The charging time of the capacitors is controlled by a pulse-width-modulated (PWM) control scheme, providing an adjustable voltage conversion ratio. However, the input current is still pulsating. The switches are under high current stress of short duration during the charging period. This aspect, in particular, causes conducted electromagnetic interference (EMI) with the supply network [17]. Moreover, when the load is light and/or the output voltage is low, the charging duration will be very short, which is practically difcult to implement. Recently, a new SC-based step-down dc/dc converter was proposed in [11]. The operation is based on a new SC converter cell, namely the quasi-switched-capacitor (QSC) step-down converter cell. It not only features all the positive characteristics of classical SC converters, but also provides continuous input current waveform and better regulation capability than the previous ones. The input current is controlled by a MOSFET operating in the saturation region [18] in each cell in order to control the charging trajectory of the capacitors. Moreover, the duty time of all switches is xed at half of the switching period, thus avoiding the practical problem of short capacitor charging time in the PWM control scheme. In order to achieve voltage regulation, an on-resistance control scheme was used in [3]. The MOSFET is driven into the triode region during the charging phase, forming a voltage-controlled resistor. However, the input charging current is still pulsating, but with much lower current stress than classical SC converters. In [11] the MOSFET is operated in the saturation region. It provides a drain current whose value is independent of the drain voltage, forming a voltagecontrolled current source (VCCS) [18]. If the gate-source voltage is kept constant, the drain current will remain constant. Finally, the dc voltage conversion ratio of the converters in [3] is xed and is dependent on the circuit structure. This paper presents the use of the current control scheme in [11] for SC step-up converters. It integrates the advantages of [11] in providing adjustable voltage conversion ratio and continuous input current waveform and keeps all superior features of classical SC step-up converters [10], [19]. The principles of operation of an -stage converter are presented in Section II. For simplifying mathematical analysis [20] a third-order state-space equation set is derived. By applying

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Fig. 1. Basic structure of the n-stage step-up DC/DC converter cell.

Fig. 2. Complete realization of an SC-based step-up dc=dc converter.

the state-space averaging technique [21], the steady-state and small-signal dynamic behaviors, the selection of capacitor value, and the maximum attainable output voltage are presented in Section III. Section IV shows the experimental results of a 5 V 12 V two-stage step-up converter prototype. Section V gives the conclusions. II. SC-BASED STEP-UP DC/DC CONVERTER A. Basic -Stage QSC Step-Up Converter Cell and Its Control Philosophy Fig. 1 shows the structure of an -stage step-up dc/dc capacitors ( to ), converter cell consisting of MOSFET switches ( to and QS to QS ), and diodes ( to and ). All capacitors are similar with and equivalent series resistance (ESR) of the value of . to are operated as static switches. QS to QS , namely the quasi-switch in [11], are operated in the saturation region. As discussed in [18], when a MOSFET is operating in the saturation region the relationship between the gate-source and the drain current can be expressed by the voltage following large-signal model: (1) is the process transconductance parameter, which is deand are the termined by the fabrication technology. aspect ratio and the threshold voltage of the MOSFET channel, with respect to respectively. The small-signal variation of can be studied by introducing perturbations the changes of and , thus into (1) with (2) and (3)

The saturated MOSFET behaves as an ideal current source whose value is controlled by according to the square-law relationship in (2) [18]. The two types of MOSFETs (i.e., QS to QS and to ) are in complementary triggering. Within a switching , their duty cycles are xed at 0.5. Thus, the cell period is composed of two main topologies. In the rst topology, to are open. to QS to QS are in operation and are linearly charged by a constant current, determined by to . In QS to QS from the supply voltage through to are the second topology, QS to QS are open and closed. All capacitors are connected in series with the input source supplying to the output load. The major advantages of the proposed converter cell over the previous ones lie in its constant input current waveform during the charging phase and xed charging and discharging times. Compared to the classical ones, the proposed cell can lower the conducted EMI with input network because of avoiding instantaneous input current peak [17] and can offer better regulation capability because of the equal duty cycle for all switches. B. Realization of a -Stage Step-Up DC/DC Converter A complete converter is realized by connecting two cells in parallel (Fig. 2) operating in antiphase. Fig. 3 shows the theoretical waveforms. It goes through two topologies in one cycle (Fig. 4). In Topology 1, all capacitors in cell 1 (i.e., to ) are linearly charged by a constant current , which is determined by the QSs. At the end of this topology, all cell-1 capacitors will have voltage slightly higher than (4) in order to compensate the parasitic losses in Topology 2. The parasitic losses include the voltage drops across the on, the ESR of the capacitors resistance of the switches , and the diode voltage drop on . All cell-2

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Fig. 3. Theoretical waveforms of the converter.

capacitors (i.e., to ) are connected in series with through to supplying to the output load . Thus, is higher than . The operations of cell 1 and cell 2 are interchanged in Topology 2. It can be seen from the above that the input current includes all charging currents of the capacitors in one cell and the output current (5) and As the magnitude of current becomes continuous. is slightly constant, the input

C. Comparisons with Previous SC-Based Converters Compared to the previous SC converters, the following major aspects can be distinguished in their performance characteristics. 1) The input current waveform of previous converters contains high current peak in the charging process while the input current of the proposed one is theoretically

constant (5). Thus, the input current waveform is improved and the conducted EMI problem is subsequently suppressed [17]. 2) For achieving voltage regulation, the capacitor charging time [8][10] is controlled by a PWM controller. It will be short at light load or at a low output voltage condition and is practically hard to be implemented. For the proposed converter, the duty cycle of all MOSFETs is xed at 0.5, which improves the regulation capability. 3) The conversion efciency of the proposed circuit will be proved to be same as those in [10] and [19] in Section III. This gives the same performance index as the previous converter, but presents better behaviors that have been discussed in 1) and 2). III. ANALYSIS
OF THE

SC STEP-UP DC/DC CONVERTER

The converter is analyzed by applying the state-space averaging technique [21]. As all the capacitors within the same

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(a)

(b) Fig. 4. The two topologies in a switching cycle. (a) Topology 1. (b) Topology 2.

cell undergo same charging and discharging mechanism, their voltage trajectories will behave identically. If each capacitor is treated by an individual state variable as in [20], the dimension . It will then of the state matrix will be require considerable time in the analysis. In order to simplify the calculation, each cell is simply represented by a single state variable for all capacitor voltage in that cell. For example, represents the capacitor voltage in cell 1 and represents the capacitor voltage in cell 2 in the following derivations. A third-order averaged state-space equation set can be formulated for the two topologies in Fig. 4 (6) where

A. Formulation of the Steady-State Characteristics The steady-state value of the output voltage into (6). Therefore obtained by substituting can be

(7) where

and

and

The above order-reduction method is valid for parallel-series SC converters, provided that the capacitors are similar and not lossy or, alternatively, capacitance and ESR are inversely proportional numbers.

Hence, provided that all QS switches are operating in the is independent of the input voltage saturation region, and the forward voltage drop of the diodes and is merely determined by the drain current of the QSs and the parasitic resistance of the components. The independence of the input voltage can be explained physically by considering a condition when the input voltage is slightly increased from the steady state. In the charging phase, the capacitor is charged by a with an incremental voltage (which constant current is independent of the input voltage). As the input voltage is increased, the output voltage (and hence the capacitor discharging current) will be increased in the discharging phase. . Thus, The capacitor voltage will decrease for more than the overall capacitor voltage is decreased in one switching cycle. This process will be repeated for several switching . The output cycles until the output current is equal to voltage is then maintained at a constant level, provided that the MOSFETs are operated in the saturation region. This physical phenomenon is also applicable when the input voltage is decreased.

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By substituting (2) into (7) it is also possible to appreciate can be regulated by controlling where how (8) is generally dictated from the feedback In a regulator, with a reference voltage. Although circuit after comparing is in nonlinear relationship with , is relatively constant in every switching cycle because the output of the feedback circuit is generally slow varying as compared to the switching frequency. B. Determination of the Conversion Efciency If and and are assumed to be similar, they give in (7). Thus (9a) and (9b) The conversion efciency to be of the converter can be shown and is identity matrix. Thus, the open-loop small-signal model of the converter can be expressed as (13) (10) The expression is the same as that obtained in [19]. equals , which is the case of minimum one when energy losses. It demonstrates that the efciency characteristic of SC converters is independent of the control scheme, but on the input and output voltages. Thus, the proposed converter gives similar conversion efciency as previous SC converters, but presents better performance characteristics, which have been discussed in Section II-C. C. Formulation of the Dynamic Characteristics of the Converter The small-signal dynamic behaviors of the converter around the operating point is studied by introducing small-signal on its steady-state value variation in the charging current and in the input voltage on its steady-state value of . A small-signal output voltage variation will be of . By separating the superimposed on its steady-state value small-signal component and neglecting the innitesimal terms of the second-order and higher order disturbances, the open] and loop input-to-output transfer function [i.e., ] are control-to-output transfer function [i.e., obtained [21] (11) and (12) A small-signal model for a closed-loop system is shown in Fig. 5, where the transfer function of the feedback error ] is included. The closed-loop smallamplier [i.e., can be shown to be signal transfer functions

Fig. 5. Small-signal model of the closed-loop system.

(14) where system [22]. D. Selection of Capacitor Value The capacitor value in each cell is chosen by considering . Since all the maximum output ripple voltage capacitors within their cell are connected in series during the can discharging phase (Fig. 4), an equivalent capacitor be used to represent the whole connected capacitor string and . That is is the loop gain of the

(15) if . For a stable and continuous dc output current approximated by (9a) it can be

(16)

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Fig. 6. Theoretical relationships between

vout;max

and

n:

COMPONENT VALUES

OF THE

TABLE I PROTOTYPE CONVERTER

Referring to Fig. 4, the discharging period of all capacitors is . In order to simplify the calculation the designed xed at will be selected in such a way that value of

increases with since (19) at the bottom of this page . However, if tends to innity, applies if will go to a value of (20) Fig. 6 shows the relationship between the value of and . The values are based on the component values as tabulated in Table I. It can be observed from (20) that is not only determined by , but also on the parasitic resistance of the components and the load resistance. The smaller the and , the higher will be the maximum values of by increasing . attainable IV. EXPERIMENTAL PROTOTYPE A 5 V 12 V 30 W two-stage step-up regulator with power density of 15 W/in has been built in the laboratory. It is shown in Fig. 7. Fig. 8 shows the schematics of the feedback circuit with its input connecting to the output of the SC converter for the QSs. Using the and its output is used to provide method described in [22], the test setup for the measurement ] is also illustrated using a gainof the loop gain [i.e., phase analyzer HP4194A. When the switch SW is at position A, the circuit is in normal operation. When SW is at position B, the loop gain measurement is performed. The test point is equivalent to point X in Fig. 5. The component values of the converter are tabulated in Table I. The capacitors are a surfacemounted multilayer ceramic type. The converter is operating at

(17)

where

is the switching frequency. with Respect to

E. Derivation of Maximum

For a given input voltage , will be maximum when during the all capacitors in each cell are fully charged to charging phase. During the discharging phase, the maximum (denoted by ) is value of

(18)

(19)

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Fig. 7. Hardware implementation of a two-stage step-up converter. (a)

(b)

Fig. 8. Schematics of the feedback circuit with the test setup for the loop gain measurement.

220 kHz and its overall efciency is 78% at the rated condition (including the required power for the driving circuit). Fig. 9 shows the experimental waveforms of the output voltage, the input current, and the capacitor voltage of one cell at the rated condition. It can be seen that the input current is continuous and does not contain pulsating peaks. The waveforms are obtained from the oscilloscope, LeCroy 9304A, and the current probe, Tektronix TM502A. The regulation capability of the converter is illustrated in Fig. 10. Fig. 10(a) is changed shows the output voltage of the converter, when is kept at 4.8 . It can be observed from 3.5 V to 8 V and is larger that the output voltage can maintain at 12 V when

(c) Fig. 9. Experimental waveforms. (a) Output voltage (timebase: 1 s=div, voltage scale: 2 V=div). (b) Input current (timebase: 1 s=div, current scale: 2.5 A=div). (c) Capacitor voltage of one cell (timebase: 1 s=div, voltage scale: 1 V=div).

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(a) (a)

(b) Fig. 11. Overall efciency of the prototype converter. (a) Efciency versus input voltage. (b) Efciency versus output load. (b) Fig. 10. Regulation capability of the proposed circuit. (a) For the variation in the input voltage at rated output load. (b) For the variation in the output load with rated input voltage.

than 4.5 V. Fig. 10(b) shows the output voltage, when the output current varies from 0.5 A to 2.5 A (by changing the ). The input voltage is kept at 5 V. It can be seen value of that the output voltage can be regulated within this operating range. The theoretical and experimental results of the overall efciency (including the driving circuit) versus the input is maintained voltage is shown in Fig. 11(a), where constant. It can be observed that the efciency decreases as the input voltage increases. The results are consistent with (10) and [19]. The overall efciency versus the output load power is shown in Fig. 11(b), where the input voltage is kept constant. Theoretically, based on (10), the efciency should be about 80% for all output power. However, the practical efciency is low at low output power since the power to the driving circuit becomes a signicant portion of the input power. When the output power is increased, the driving power can be neglected. Thus, the overall efciency increases with the output load. , the theoretical and experimental By varying the value of output ripple voltage at different output current is shown in Fig. 12. The output voltage is maintained constant at 12 V. The maximum ripple voltage is less than 1%. The theoretical predictions are obtained by using (17). Fig. 13(a) shows the measurement results of the loop gain ]. The gain and phase margin were found to be [i.e., 23 dB and 55 , respectively, showing stable operation. The

Fig. 12. Output ripple voltages versus the output current.

results are compared to the theoretical predictions. Moreover, by using (14), the theoretical prediction and experimental measurements of the small-signal closed-loop input-to-output frequency responses are shown in Fig. 13(b). It can be observed that the theoretical results agree well with the experimental ones at the low-frequency range. At high frequencies, the experimental values deviate from the expected ones since the analyzer becomes susceptible to the common-mode noise. Nevertheless, the differences are within an acceptable range. Theoretically, Topology 1 and Topology 2 have to be , in order to obtain continuous input operated for exactly current waveform. However, practical MOSFET has nite turn-on and turn-off time. Thus, a short dead time is added between the gate signals applying to QSs and s in the respective cell in order to avoid overlap of the two topologies.

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(a)

(b)

Fig. 13. Small-signal frequency characterizations of the prototype converter. (a) Loop gain OL . (b) Closed-loop input-to-output transfer characteristics og;CL .

In this prototype, a dead time of 60 ns is added and a small capacitor of 10 nF is added across the input in order to smooth the input current. V. CONCLUSION A generalized -stage SC-based step-up dc/dc converter which uses no magnetic element was designed and analyzed. The design criteria, constraints of operation, and the control philosophy were given. The converter presents all the positive characteristics of previous SC converters. It can also provide the adjustable voltage conversion ratio, which is independent on circuit structure and gives better input current waveform and regulation capability than previous SC converters. A two-stage 5 V 12 V step-up converter prototype has been built at a nominal output power of 30 W. The use of only MOSFET switches and multilayer ceramic capacitors and no inductor/transformer assures small size, light weight, and high power density realization. Further research will be dedicated to the development of ac/dc and dc/ac converters by applying the principle of this paper. REFERENCES
[1] Z. Singer, A. Emanuel, and M. S. Erlicki, Power regulation by means of a switched capacitor, Proc. Inst. Electr. Eng., 1972, vol. 119, no. 2, pp. 149153. [2] D. Midgley and M. Sigger, Switched capacitors in power control, Proc. Inst. Electr. Eng., 1974, vol. 121, no. 7, pp. 703704.

[3] F. Ueno, T. Inoue, T. Umeno, and I. Oota, Analysis and application of switched-capacitor transformers by formulation, Electron. Commun. Japan Pt. IIElectron., vol. 73, no. 9, pp. 91103, Sept. 1990. [4] T. Umeno, K. Takahashi, F. Ueno, T. Inoue, and I. Oota, A new approach to low ripple-noise switching converters on the basis of switched-capacitor converters, in Proc. IEEE Int. Symp. Circuits Systems, June 1991, pp. 10771080. [5] F. Ueno, T. Inoue, and I. Oota, Realization of a switched-capacitor ACDC converter using a new phase controller, in Proc. IEEE Int. Symp. Circuits Systems, June 1991, pp. 10571060. [6] F. Ueno, T. Inoue, I. Oota, and I. Harada, Power supply for electroluminescene aiming integrated circuits, in Proc. IEEE Int. Symp. Circuit Systems, May 1992, pp. 19031906. [7] R. Marusarz, A switches capacitor, inductorless DC to AC voltage stepup power converters, in Proc. IEEE Power Electron. Special Conf. Rec., June 1989, pp. 99103. [8] S. V. Cheong, S. H. Chung, and A. Ioinovici, Development of power electronics converters based on switched-capacitor circuits, in Proc. IEEE Int. Symp. Circuits Systems., May 1992, pp. 19071910. [9] S. V. Cheong, S. H. Chung, and A. Ioinovici, Inductorless dc-to-dc converter with high power density, IEEE Trans. Ind. Electron., vol. 41, pp. 208215, Apr. 1994. [10] O. C. Mak, Y. C. Wong, and A. Ioinovici, Step-up dc power supply based on a switched-capacitor circuit, IEEE Trans. Ind. Electron., vol. 42, pp. 9097, Feb. 1995. [11] H. Chung, B. O, and A. Ioinovici, Switched-capacitor-based dc-to-dc converter with improved input current waveform, in Proc. IEEE Int. Symp. Circuits Systems, May 1996, pp. 541544. [12] Principles and applications of the ICL 7660 CMOS voltage converter, in Intersil Applications Handbook, 1988. [13] Applications of the LTC 1144, in Linear Technology Handbook, 1993. [14] MAX828/829 switched-capacitor voltage inverter, in Maxim Applications Databook, 1997. [15] R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog Filters: Passive, Active RC, and Switched Capacitor. Englewood Cliffs, NJ: Prentice-Hall, 1990. [16] M. S. Makowski, Realizability conditions and bounds on synthesis of switched-capacitor dc-dc voltage multiplier circuits, IEEE Trans. Circuit Systs. I, vol. 44, pp. 684691, Aug. 1997. [17] H. Ott, Noise Reduction Techniques in Electronic Systems. New York: Wiley, 1989. [18] A. S. Sedra and K. C. Simth, Microelectronic Circuits, 4th ed. London, U.K.: Oxford Univ. Press, 1998. [19] G. Zhu and A. Ioinovici, Switched-capacitor power supplies: DC voltage ratio, efciency, ripple, regulation, in Proc. IEEE Int. Symp. Circuits Systems, May 1996, pp. 553556. [20] K. D. T. Ngo and R. Webster, Steady-state analysis and design of a switched-capacitor dc-dc converter, IEEE Trans. Aerosp. Electron. Syst., vol. 30, pp. 92101, Jan. 1994. [21] R. D. Middlebrook and S. Cuk, A general unied approach to modeling switching-converter power stages, in Proc. IEEE Power Electron. Spec. Conf. Rec., June 1976, pp. 1834. [22] K. K. Sum, Switch Mode Power Conversion: Basic Theory and Design. New York: Marcel Dekker, 1984.

Henry Shu-hung Chung (S92M95) received the B.Eng. (with First Class Honors) and the Ph.D. degrees in electrical engineering from the Hong Kong Polytechnic University, Hong Kong, China, in 1991 and 1994, respectively. Since 1995 he has been with the City University of Hong Kong, where he is currently an Associate Professor in the Department of Electronic Engineering. His research interests include time- and frequency-domain analysis of power electronic circuits, switched-capacitor-based converters, randomswitching techniques, and soft-switching converters. He has authored over 85 technical papers in his current research area. Dr. Chung was the recipient of the China Light and Power Prize and was awarded the Scholarship and Fellowship of the Sir Edward Youde Memorial Fund in 1991 and 1993, respectively. He is currently Chairman of the Council of the Sir Edward Youde Scholars Association and is an IEEE student branch counselor. He was Track Chair of the technical committee on power electronics circuits and power systems of the IEEE Circuits and Systems Society in 19971998.