Conditional-Sum Adder and its VHDL Implementation

The conditional-sum adder is developed by Sklansky. Figure 1 illustrates the addition of two 16 bit numbers using conditional sum.

i Xi Yi S0 C0 S1 C1 S0 C0 S1 C1 S0 C0 S1 C1 S0 C0 S1 C1 Si

15 14 13 12 11 10 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 0

9 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0

8 1 1 0 1 1 1 0 1 0 1 1 1 1

7 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1

6 1 0 1 0 0 1 1 0 0 0 0

5 1 1 0 1 1 1 0 1 1 1 0 1 1

4 0 1 1 0 0 1 1 0 1 0 0

3 1 0 1 0 0 1 0 1 0 1 0 1

2 1 1 0 1 1 1 0 1 0

1 0 1 1 0 0 1 1 0

0 1 Level 0 1 0 1

1 2

1 3

1 4

Ci+1 0 Fig.1: 16-bit Conditional Sum Adder S0 Sum with Cin = 0; C0 Carry with Cin = 0; S1 Sum with Cin = 1; C1 Carry with Cin = 1

At level 1, all conditional sums and carries of the ith pair of input bits are generated. Note that the outputs S0, C0, S1, C1 are generated at each bit position independent of other bit positions. This is because S0 and C0 are sum and carry outputs that assume the previous carry to be zero and S1 and C1 are sum and carry outputs that assume the previous carry to be 1. Level 2 bits are determined from level 1. First, all level 1 bits are paired up (in groups of two columns as shown in Fig.1 and the visible vertical line in the figure divides the pair). The least significant carry is used to select which sum and carry of the next bit position will be brought down to level 2.
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Similarly, level 3 sum and carry output bits are determined form level 2 outputs. Level 2 bits are grouped into 4 bit groups as shown in Fig.1. The least significant carry in each group is used to select which of the next two bit positions are brought down to level 3. This continues until all the sums and carries are resolved by level 5. Note that only one level is added for each power of two increase in wordlength. Hence, a 32 bit adder would require 6 levels, and a 64 bit adder 7 levels. A conditional sum adder can be built using conditional adder cells and muxes. The conditional adder cells generate the signals S0, C0, S1, C1 for each bit position. The muxes are used to resolve the correct sum and carry signals. In addition, buffer cells are needed to drive the large minces. Fig.2 shows the architecture of a 16 bit conditional sum adder. VHDL Implementation:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Adder_CS_16bit is port (a, b: in std_logic_vector(15 downto 0); cin: in std_logic; sum: out std_logic_vector(15 downto 0); cout: out std_logic); end Adder_CS_16bit; architecture behavioral of Adder_CS_16bit is signal s10: std_logic_vector(15 downto 0) := "0000000000000000"; signal s11: std_logic_vector(15 downto 0) := "0000000000000000"; signal c10: std_logic_vector(15 downto 0) := "0000000000000000"; signal c11: std_logic_vector(15 downto 0) := "0000000000000000"; signal s20: std_logic_vector(15 downto 0) := "0000000000000000"; signal s21: std_logic_vector(15 downto 0) := "0000000000000000"; signal c20: std_logic_vector(15 downto 0) := "0000000000000000"; signal c21: std_logic_vector(15 downto 0) := "0000000000000000"; signal s30: std_logic_vector(15 downto 0) := "0000000000000000"; signal s31: std_logic_vector(15 downto 0) := "0000000000000000"; signal c30: std_logic_vector(15 downto 0) := "0000000000000000"; signal c31: std_logic_vector(15 downto 0) := "0000000000000000"; signal s40: std_logic_vector(15 downto 0) := "0000000000000000"; signal s41: std_logic_vector(15 downto 0) := "0000000000000000"; signal c40: std_logic_vector(15 downto 0) := "0000000000000000"; signal c41: std_logic_vector(15 downto 0) := "0000000000000000"; signal P: std_logic := '0'; signal G: std_logic := '0';

begin -- construct Conditional Sum Adder Cell (Level - 1) process (a, b) begin P <= a(0) xor b(0); G <= a(0) and b(0); end process; process (a, b, P, G, cin) begin s10(0) <= P xor cin; c10(0) <= G or (P and cin); for i in 1 to a'length - 1 loop s10(i) <= a(i) xor b(i); c10(i) <= a(i) and b(i); c11(i) <= a(i) or b(i); end loop; end process; process (s10) begin s11 <= not s10; end process; -- Level - 2 process (s10, s11, c10, c11) begin s20(0) <= s10(0); if c10(0) = '1' then s20(1) <= s11(1); c20(1) <= c11(1); elsif c10(0) = '0' then s20(1) <= s10(1); c20(1) <= c10(1); end if; for i in 2 to a'length - 1 loop if (i mod 2 = 0) then s20(i) <= s10(i); s21(i) <= s11(i); if c10(i) = '1' then s20(i+1) <= s11(i+1); c20(i+1) <= c11(i+1); elsif c10(i) = '0' then s20(i+1) <= s10(i+1); c20(i+1) <= c10(i+1); end if; if c11(i) = '0' then s21(i+1) <= s10(i+1); c21(i+1) <= c10(i+1); elsif c11(i) = '1' then s21(i+1) <= s11(i+1); c21(i+1) <= c11(i+1); end if; end if; end loop;

end process; -- Level 3 process (s20, s21, c20, c21) begin s30(1 downto 0) <= s20(1 downto 0); if c20(1) = '1' then s30(3 downto 2) <= s21(3 downto 2); c30(3) <= c21(3); elsif c20(1) = '0' then s30(3 downto 2) <= s20(3 downto 2); c30(3) <= c20(3); end if; for i in 4 to a'length - 1 loop if (i mod 4 = 1) then s30(i downto i-1) <= s20(i downto i-1); s31(i downto i-1) <= s21(i downto i-1); if c20(i) = '1' then s30(i+2 downto i+1) <= s21(i+2 downto i+1); c30(i+2) <= c21(i+2); elsif c20(i) = '0' then s30(i+2 downto i+1) <= s20(i+2 downto i+1); c30(i+2) <= c20(i+2); end if; if c21(i) = '0' then s31(i+2 downto i+1) <= s20(i+2 downto i+1); c31(i+2) <= c20(i+2); elsif c21(i) = '1' then s31(i+2 downto i+1) <= s21(i+2 downto i+1); c31(i+2) <= c21(i+2); end if; end if; end loop; end process; -- level - 4 process (s30, s31, c30, c31) begin s40(3 downto 0) <= s30(3 downto 0); if c30(3) = '1' then s40(7 downto 4) <= s31(7 downto 4); c40(7) <= c31(7); elsif c30(3) = '0' then s40(7 downto 4) <= s30(7 downto 4); c40(7) <= c30(7); end if; for i in 11 to a'length - 1 loop if (i mod 8 = 3) then s40(i downto i-3) <= s30(i downto i-3); s41(i downto i-3) <= s31(i downto i-3); if c30(i) = '1' then s40(i+4 downto i+1) <= s31(i+4 downto i+1); c40(i+4) <= c31(i+4); elsif c30(i) = '0' then s40(i+4 downto i+1) <= s30(i+4 downto i+1);

c40(i+4) <= c30(i+4); end if; if c31(i) = '0' then s41(i+4 downto i+1) <= s30(i+4 downto i+1); c41(i+4) <= c30(i+4); elsif c31(i) = '1' then s41(i+4 downto i+1) <= s31(i+4 downto i+1); c41(i+4) <= c31(i+4); end if; end if; end loop; end process; -- level - 5 process (s40, s41, c40, c41) begin sum(7 downto 0) <= s40(7 downto 0); if c40(7) = '1' then sum(15 downto 8) <= s41(15 downto 8); cout <= c41(15); elsif c40(7) = '0' then sum(15 downto 8) <= s40(15 downto 8); cout <= c40(15); end if; end process; end behavioral;