EXPERIMENT NO.

12

Title- To study the characteristics of various types of flip-flops Objective To study the characteristic of SR flip-flop, D flip-flop, JK flipflop, T flip-flop.

Apparatus Required- IC 7476, IC 7404, IC 7408, IC 7402, Experimental Kit,

Connecting wires.

Theory- The basic one bit parity memory circuit is known as flip-flop. It can
have either the 1 state or the 0 state. A flip-flop is also known as bistable multivibrator. Thus we can say a flip-flop can store one bit information, so it is called one bit memory element. Sometimes flip-flop is also called synchronous bistable device because output changes when state only at a specified point on a triggered input called clock (i.e either at positive edge or negative edge). Flipflops are classified according to the number of inputs they process and the manner in which the input affect their output state. There are 1) 2) 3) 4) SR Flip-Flop D Flip-Flop JK Flip-Flop T Flip-Flop

The SR Flip-FlopThe circuit is similar to SR latch except enable signal is replaced by Clock pulse (CLK). This circuit responds on the positive edge of the clock pulse to the input S and R. The truth table of Flip-flop refers to the operational characteristics of the flip-flop. But in designing sequential circuits, we often face situations where the present state and the next state of the flip-flop is specified, and we have to find out the input conditions that must prevail for the desired output condition. The present state means the condition before the clock pulse and next state means the condition after the clock pulse. For example the output of an SR flipflop before the clock pulse is Qn = 1 and it is desired that the output does not change (Qn+1 = 1), when the clock pulse is applied. Truth Table of SR Flip-Flop CLK 0 1 1 1 S X 0 0 1 R X 0 1 0 Q Q NC 0 1 Q Q NC 1 0

The D Flip-FlopFrom the truth table of SR FLIP-FLOP we see that the outputs of RS flip-flop is in unpredictable state when the inputs are same (i.e. when SR =00) then no change and when SR- 11 then invalid or intermediate). In many practical applications, these input conditions are not required. These input conditions can be avoided by making then complement of each other. Thus, the modified Clocked SR flip-flop is known as D flip-flop. The functional behavior of a latch or flip-flop can be described by a characteristic equation that specifies the latch or flip-flop next state as function of its current state ( or present state, Q n) and input. From the truth table , we see that the output of D- flip flop depends on the present input, therefore D flip-flop is also known as Delay flip-flop. Because the single D input is also inverted to provide the signal to reset the latch, this latch circuit cannot experience a race condition caused by all inputs being at logic 1 simultaneously. Therefore D latch can be safely used in any circuit. Except for change in input circuitry, a D flip-flop works just like the RS flipflop.

Truth Table of D Flip-Flop CLK 0 1 1 1 S X 0 0 1 R X 0 1 0 Q Q NC 0 1 Q Q NC 1 0

JK flip-flopTo prevent any possibility of both the S and R input of SR flip-flop to be at logic 1 when the CLK input falls from logic 1 to logic 0, we must somehow prevent one of inputs from having an effect on the circuit. At the same time we will want the flip-flop to be able change state on each falling edge of the CLK input, if the input logic signal call for this. Therefore, the S or R input to be disabled on the circuit state of the latch outputs. The Inputs are designated as J (instead of S) and K (instead of R). The entire circuit is known as a JK flip-flop. Since one of the two logic inputs is always disabled according to the input output state of the overall flip-flop, the latch cannot change state back and forth while the CLK input is at logic 1. Instead, the enabled input can change the state of the master latch once, after which this latch will not change again. This was not true in the RS flip-flop.

Truth Table of JK Flip-Flop PRE L H L H H H H CLR H L L H H H H CLK X X X H H H H J X X X L H L H K X X X L L H H Qn+1 H L H Qn H L Toggle Qn+1 L H H Qn L H Toggle

T Flip-FlopThe flip-flop is a modification of the JK flip-flop. If both the J and K inputs of the JK flip-flop are held at logic 1 and the CLK signal continues to change, the Q and Q outputs will simply change state with each rising edge of the CLK signal. The T flip-flop must be edge triggered. Because of the feedback connection in the JK or T flip-flop, a clock pulse (CLK) that remains in the 1 state while both J=K=1 Or T=1 will cause the output to complement again and repeat complementing until the pulse goes back to 0. To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the flip-flop. This is the only way to ensure that the flip-flip will change state only once on any given clock pulse.

Truth Table of T Flip-Flop CLK L H H T X L H Qn+1 Qn Qn Qn

Observation Tables for Flips flops

1) SR Flip flop
CLK 0 1 1 1 S X 0 0 1 R X 0 1 0 Q LED Q (Red) NC (Red) 0 (Green) 1 (Red) Q LED Q ( Green) NC (Green) 1 (Red) 0 (Green)

2) D Flip flop
CLK 0 0 1 1 D 0 1 0 1 Q NC NC 1 0 LED NC NC Red Green

3) JK Flip flop
PRE L H L H H H H CLR H L L H H H H CLK X X X H H H H J X X X L H L H K X X X L L H H Qn+1 (LED) H (Red L (Green) H (Red) Qn (Red) H (Red) L (Green) Toggle Qn+1 L (Red) H (Green) H (Green) Qn (Red) L (Green) H (Red) Toggle

4) T Flip Flop
CLK L H H T X L H Qn+1 Qn Qn Qn LED

Result - we have found the same result of truth table as in the theory, Thus truth table is verified. Precaution:- 1) Experimental kit should be handled with care. 2) All the connection should be Right and Tight.