PHYSICAL LAYER DESIGN OF OFDM TRANSMITTER AND RECEIVER DESIGN

1. INTRODUCTION

1.1 Overview of Wireless LANs

A Wireless Local Area Network (WLAN) is a system of (usually mobile) nodes that access a common wireless channel within the same frequency band, for transferring data amongst each other, within a limited geographical area. Wireless LANs have quickly become a significant niche in the LAN market. As adjuncts to traditional wired LANs, they satisfy mobility, relocation, and ad hoc networking requirements and provide a way to cover locations that are difficult to wire [1]. Before advent of higher data rate modes of WLANs, few organizations used wireless LANs because they cost too much, low data rates, they posed occupational safety problems because of concerns about the health effects of electromagnetic radiation, and the spectrum used required a license. Today, however, these problems have largely diminished, and wireless LAN popularity is skyrocketing. Wireless LAN products first appeared in the late 1980s, marketed as substitutes for traditional wired LANs. The motivation behind using a wireless LAN is to avoid the cost of installing LAN cabling and ease the task of relocating or otherwise modifying the networks structure. For instance, building with large open areas such as manufacturing plants, stock exchange trading floors, and warehouses [1], make wired LANs awkward to install because of limited choices for cable placement. Also historical buildings often have insufficient twisted-pair cabling and prohibit drilling holes for new wiring. Finally, small offices often find it uneconomical to install and maintain wired LANs. In most cases, an organization already has a wired LAN to support servers and some stationary workstations. For example, a manufacturing facility typically has an office area that is physically separate from the factory floor but must be linked to it for networking. Therefore, organizations will commonly link a wireless LAN into a wired LAN on the same premises. This kind of application, or LAN extension, can be achieved through one or more Control Modules (CM) in single or multiple cell configurations.
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PHYSICAL LAYER DESIGN OF OFDM TRANSMITTER AND RECEIVER DESIGN

Fig. 1.1 shows the single-cell configuration, a simple wireless LAN strategy typical of many environments. It is so named because all the wireless end systems are within range of a single control module.

Fig 1.1 Single-cell wireless LAN Configuration

A backbone wired LAN, such as Ethernet, supports servers, workstations, and one or more bridges or routers to link with other networks. A control module (CM) acts as an interface to a wireless LAN. The module includes either bridge or router functionality to link the wireless LAN to the backbone and some sort of access control logic, such as a polling or token-passing scheme, to regulate access from the end systems. Some of the end systems are stand-alone devices, such as a workstation or a server. Hubs or other user modules (UMs) that control several stations off a wired LAN may also be part of the configuration.

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Another common configuration is a multiple-cell wireless LAN, in which a wired LAN connects multiple control modules [1]. Each control module supports wireless end systems within its transmission range. An infrared LAN, for example, limits transmission to a single room, so each room in an office building would need one cell.

In a Nomadic Access configuration, the wireless LAN links a LAN hub and a mobile data terminal equipped with an antenna, such as a laptop or notepad computer. Thus, for example, an employee returning from a trip can transfer data from a personal portable computer to an office server. Nomadic access is also useful in an extended environment such as a campus or a business operating from a cluster of buildings. In both cases, users can move around with their portable computers and access the servers on a wired LAN from various locations.

In an Ad hoc network configuration, a network is set up temporarily to meet some immediate need. It has no centralized server. Thus, in meetings, a group of employees, each with a laptop or palmtop computer, can link their computers in a network that lasts just as long as the meeting.

The IEEE 802.11 standard for wireless LANs is presently the dominant standard for Wireless LANs. It specifies the implementations of the Medium Access Control (MAC) and physical (PHY) layers.

1.2 The IEEE 802.11 Architecture

The smallest building block of a wireless LAN is a basic service set, which consists of stations that execute the same MAC protocol and compete for access to the same shared wireless medium [1, 2]. A basic service set may be isolated or, as shown in Fig. 1.2, connected to a backbone distribution system through an access point (AP), which functions as a bridge and is implemented as part of a station. A central coordination function housed in the access point controls the MAC protocol or the protocol may be fully distributed. The basic service set generally corresponds to a cell. The distribution
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system can be a switch, wired network, or wireless network. The portal integrates the IEEE 802.11 architecture with a traditional wired LAN. The portal logic is implemented in a device, such as a bridge or router, which is part of the wired LAN and attached to the distribution system. These extensions to the Basic Service Set constitute an Extended Service Set as shown in Fig. 1.2, in which a distribution system connects two or more basic service sets. Typically, the distribution system is a wired backbone LAN, but it can be any communications network. The extended service set appears as a single logical LAN to the logical link control (LLC) level. The access point is the logic within a station that provides access to the distribution system by providing services in addition to acting as a station.

Fig 1.2 IEEEs 802.11s Extended Service Set Architecture

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1.3 IEEE 802.11 Protocol Layers

Fig. 1.3 shows the standards layered protocol architecture [1, 2, 3, 4, 5]. The lowest (physical) layer defines the frequency band, data rate, and other details of the actual radio transmission. Above the physical layer is the medium access control (MAC) layer, which regulates access to the shared radio frequency band so that station transmissions do not interfere with one another [1]. The MAC layer has two sub layers. The lower one is the distributed coordination function, which uses an Ethernet-style contention algorithm that provides access to all traffic. Ordinary asynchronous traffic uses this coordination function. The upper MAC sub layer is the point coordination function, a centralized MAC algorithm that provides contention-free service by polling stations in turn. Higher priority traffic, traffic with greater timing requirements, uses this coordination function. Finally, the logical link control layer provides an interface to higher layers and performs basic link-layer functions such as error control shown in Fig 1.3.

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1.4 IEEE 802.11 PHY Specifications

The IEEE issued the physical layer for 802.11 in four stages. The first part, issued in 1997, is called simply IEEE 802.11 [2]. As Fig. 1.3 shows, it includes the MAC layer and three physical layer specifications, all operating at data rates of 1 and 2 Mbps: Direct-sequence spread spectrum (DS-SS), operating in the 2.4-GHz ISM (Industrial, Scientific, and Medical) band; Frequency-hopping spread spectrum (FHSS), operating in the 2.4-GHz ISM band; and Infrared, operating at a wavelength between 850 and 950 nm.

Most of the early 802.11 networks used the FHSS scheme, which is simpler. Networks that used the DS-SS scheme were more effective, but all the original 802.11 products had data rates of at most 2 Mbps, which limited their usefulness. In 1999, the IEEE issued the second and third physical layers, IEEE 802.11a and IEEE 802.11b, at roughly the same time. IEEE 802.11a operates in the 5-GHz band at data rates up to 54 Mbps. IEEE 802.11b operates in the 2.4-Ghz band at 5.5 and 11 Mbps. Because 802.11b is easier to implement, it has yielded products first. IEEE 802.11b extends the IEEE 802.11 DS-SS scheme, providing data rates of 5.5 and 11 Mbps through the use of a more complex modulation technique Complementary Code Keying (CCK). Although 802.11b is successful to some degree, the data rate is still too low for applications that need a truly high speed LAN. IEEE 802.11a targets this specific need. Unlike the other 802.11 standards, it specifies the 5-GHz band, and it replaces the spreadspectrum scheme with the faster orthogonal frequency-division multiplexing. OFDM, also called multi-carrier modulation, uses up to 52 carrier signals at different frequencies, sending some of the bits on each channel. Possible data rates are 6, 9, 12, 18, 24, 36, 48, and 54 Mbps.In 2003, the IEEE issued the fourth physical layer std. IEEE 802.11g. IEEE 802.11g PHY operates in 2.4 GHz band and the possible data rates are 1 and 2 Mbps (using DSSS), 5.5 and 11 (using DSSS/CCK), 6, 9, 12, 18, 24, 36, 48, and 54 Mbps (using OFDM).
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2: LITERATURE SURVEY
2.1 Evolution of WLAN Standards
The first wireless Ethernet standard, IEEE 802.11, was adopted in 1997 [6]. This standard provided for three physical layer (PHY) specifications including infrared, 1-2 Mbps frequency hopping spread spectrum (FHSS) and 1-2 Mbps direct sequence spread spectrum (DSSS) in the 2.4 GHz ISM band. Because wired Ethernet LANs at the time were capable of speeds up to 10 Mbps and early products were quite pricey, the original 802.11 standard had limited success in the market.

Two years later, the original 802.11 standard evolved along two paths. The 802.11b specification increased data rates well beyond the critical 10 Mbps mark, maintained compatibility with the original 802.11 DSSS standard and incorporated a more efficient coding scheme known as complimentary code keying (CCK) to attain a top-end data rate of 11 Mbps . A second coding scheme, Packet Binary Convolutional Code (PBCC), was included as an option for higher performance in the form of range at the 5.5 and 11 Mbps rates, as it provided for a 3 decibel (dB) coding gain.

The second offshoot of 802.11 was designated as 802.11a. It ventured into a different frequency band, the 5 GHz U-NII band, and was specified to achieve data rates up to 54 Mbps. Unlike 802.11b, which is a single carrier system, 802.11a utilized a multi-carrier modulation technique known as orthogonal frequency division multiplexing (OFDM). By utilizing the 5 GHz radio spectrum, 802.11a is not interoperable with either 802.11b, or the initial 802.11 WLAN standard.

In March 2000, the IEEE 802.11 Working Group formed a study group to explore the feasibility of establishing an extension to the 802.11b standard for higher data rates greater than 20 Mbps. In July 2000, this study group became a full task group, Task Group G (TGg), with a mission to define the next standard for higher rates in the 2.4 GHz band. The new standard was which came into existence in July 2003 is named as IEEE 802.11g and operates into 2.4 GHz ISM band and the data rate is up to 54 Mbps.
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For basic rate of 1 and 2 Mbps, IEEE 802.11g uses DSSS scheme, for 5.5 and 11 data rates IEEE 802.11g uses CCK encoding scheme, and for 6, 12 and 24 Mbps data rates IEEE 802.11g uses OFDM scheme. Theses all are mandatory modes for IEEE 802.11g PHY. Table 2.1 shows all the mandatory and optional modes for IEEE 802.11b, IEEE 802.11g, and IEEE 802.11a. Table 2.1 Data Rates for All Modes

802.11b (2.4 GHz) Rate,

802.11g (2.4 GHz)

802.11a (5 GHz) Mandatory Optional

Single/ Mandatory Optional Mandatory Optional

Mbps multi carrier 1 2 5.5 6 9 Single Single Single Multi Multi Barker Barker CCK PBCC Barker Barker CCK OFDM PBCC CCK-OFDM OFDM, CCK-OFDM 11 12 18 Single Multi Multi CCK PBCC CCK OFDM PBCC CCK-OFDM OFDM, CCK-OFDM 22 24 33 36 Single Multi Single Multi OFDM PBCC CCK-OFDM PBCC OFDM, CCK-OFDM 48 Multi OFDM, CCK-OFDM 54 Multi OFDM,CCKOFDM OFDM OFDM OFDM OFDM OFDM OFDM OFDM OFDM

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802.11g achieves the high 54 Mbps data rates (Table 2.1) of 802.11a in the 2.4 GHz band thereby maintaining compatibility with installed 802.11b equipment.

2.2 Wireless Local Area Networks (WLANs) PHY

The 802.11 physical layer (PHY) is the interface between the MAC and the wireless media where frames are transmitted and received. The PHY provides three functions. First, the PHY provides an interface to exchange frames with the upper MAC layer for transmission and reception of data. Secondly, the PHY uses signal carrier and spread spectrum modulation to transmit data frames over the media. Thirdly, the PHY provides a carrier sense indication back to the MAC to verify activity on the media.

2.2.1 Original IEEE 802.11 PHY

The original IEEE 802.11 provides three different PHY definitions: Frequency Hopping Spread Spectrum (FHSS), Direct Sequence Spread Spectrum (DSSS), and Infrared [2]. Both Frequency Hopping Spread Spectrum (FHSS) and Direct Sequence Spread Spectrum (DSSS) support 1 and 2 Mbps data rates.

2.2.1.1 Frequency Hopping Spread Spectrum (FHSS)

Frequency Hopping utilizes a set of narrow channels and "hops" through all of them in a predetermined sequence. For example, the 2.4 GHz frequency band is divided into 70 channels of 1 MHz each. Every 20 to 400 msec the system "hops" to a new channel following a predetermined cyclic pattern. There are 3 hopping sequence set with 26 hopping sequences per set. The minimum hope rate is 2.5 hops per second. The 802.11 Frequency Hopping Spread Spectrum (FHSS) PHY uses the 2.4 GHz radio frequency band, operating with at 1 or 2 Mbps data rate. The basic access rate of 1 Mbps uses a two level Gaussian Minimum Shift Keying (GMSK) while the enhanced access rate of 2 Mbps uses a 4 level GMSK.

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2.2.1.2 Direct Sequence Spread Spectrum (DSSS)

The principle of Direct Sequence is to spread a signal on a larger frequency band by multiplexing it with a signature or code to minimize localized interference and background noise. To spread the signal, each bit is modulated by a code. In the receiver, the original signal is recovered by receiving the whole spread channel and demodulating with the same code used by the transmitter. The 802.11 Direct Sequence Spread Spectrum (DSSS) PHY also uses the 2.4 GHz radio frequency band. The basic access rate of 1 Mbps is encoded using Differential Binary Phase Shift Keying (DBPSK) while the enhanced 2 mbps rate is encoded using Differential Quadrature Phase Shift Keying (DQPSK).

2.2.1.3 Infrared
The Infrared PHY utilizes infrared light to transmit binary data either at 1 Mbps (basic access rate) or 2 Mbps (enhanced access rate) using a specific modulation technique for each. For 1 Mbps, the infrared PHY uses a 16-pulse position modulation (PPM). The concept of PPM is to vary the position of a pulse to represent different binary symbols. Infrared transmission at 2 Mbps utilizes a 4 PPM modulation technique. This specification was designed for indoor use only.

2.3 OFDM Principals

Orthogonal Frequency Division Multiplexing (OFDM) system takes a serial data stream and splits it into N parallel data streams. Each parallel stream of data is then modulated into a subcarrier at a unique frequency and then the subcarriers are combined to produce a serial stream of transmitted signal [17]. For example, if a 100 subcarriers system were used, a signal data stream with a rate of 20 Mbps would be converted into 100 streams of 200Kbps. By creating a slower parallel data streams, the bandwidth of the modulation symbol is effectively decrease by a factor of 100, or, in another words, the duration of the modulation symbol is increased by a factor of 100. Proper selection of the design parameter such as the number of sub-carriers, sub-carriers spacing can greatly reduce or
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even eliminate ISI because the delay spread will then be shorted than the symbol period. This also eliminates the needs for a complex multi-tap time domain equalizers [17]. OFDM actually combine the data and transmit them in block. The size of each block is determined by the number of sub-carriers used to convert the serial stream of data to parallel stream

2.4 The OFDM system

A detailed explanation of the OFDM system was given in the previous chapter, in which different building blocks of an OFDM communication system were discussed. Following is a brief review of those concepts. In 1971 Discrete Fourier Transform (DFT) was used in baseband modulation/

demodulation in order to achieve orthogonality. Since DFT has heavy computational requirements, therefore, Fast Fourier Transform (FFT) was utilized. For an N point discrete Fourier Transform the required number of computations is N2, but that for FFT is Nlog (N), which is much lesser than DFT. In this way the problem of bandwidth inefficiency due to the placement of guard bands between sub-channels was solved and a new technique Orthogonal Frequency Division Multiplexing came into being. As OFDM is a multi-carrier modulation technique, therefore, the input data is split and mapped onto different sub-carriers. Each carrier is modulated using one of the singlecarrier modulation techniques discussed above. The OFDM system successfully avoids any inter-channel interference (ICI) because the carriers are kept orthogonal. In addition, a cyclic prefix (CP) is added before the start of each transmitted symbol to act as a guard period preventing inter-symbol interference (ISI), provided that the delay spread in the channel is less than the guard period . This guard period is specified in terms of the fraction of the number of samples that make up a symbol.

2.5 Advantages and dsadvantages of OFDM:

Another advantage of OFDM is its resilience to Multipath, which is the effect of multiple reflected signals hitting the receiver. This results in interference and frequency-selective

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fading which OFDM is able to overcome by utilizing its parallel, slower bandwidth nature. This makes OFDM ideal to handle the harsh conditions of the mobile wireless environment. The introduction of cyclic prefix made OFDM system resistant to time dispersion . OFDM symbol rate is low since a data stream is divided into several parallel streams before transmission. This make the fading is slow enough for the channel to be considered as constant during one OFDM symbol interval. Cyclic prefix is a crucial feature of OFDM used to combat the inter-symbol interference (ISI) and inter-channel-interference (ICI) introduced by the multi-path channel through which the signal is propagated . The basic idea is to replicate part of the OFDM timedomain waveform from the back to the front to create a guard period. The duration of the guard period should be longer than the worst-case delay spread of the target multipath environment. The use of a cyclic prefix instead of a plain guard interval, simplifies the channel equalization in the demodulator. In wire system, OFDM system can offer an efficient bit loading technique It enables a system to allocate different number of bits to different sub channels based on their individual SNR. Hence, an efficient transmission can be achieved. One of the major disadvantages of OFDM is its requirement for high peak-to average power ratio (PAPR). This put high demand on linearity in amplifiers. Second, the synchronization error can destroy the orthogonality and cause interference. Phase noise error and Doppler shift can cause degradation to OFDM system . A lot of effort is required to design accurate frequency synchronizers for OFDM. OFDMs high spectral efficiency and resistance to Multipath make it an extremely suitable technology to meet the demands of wireless data traffic. This has made it not only ideal for such new technologies like WiMAX and Wi-Fi but also currently one of the prime technologies being considered for use in future fourth generation (4G) networks.

2.6 Applications of OFDM

Initially, OFDM applications are scarce because of their implementation complexity. Now, OFDM has been adopted as the new European digital audio broadcasting (DAB)

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standard and for terrestrial digital video broadcasting (DVB) .In fixed-wire applications, OFDM is employed in asynchronous digital subscriber line (ADSL) and high bit-rate digital subscriber line (HDSL) systems. It has been proposed for power line communications systems as well due to its resilience to dispersive channel and narrow band interference. It has been employed in WiMAX a well.

2.7 Verilog Hardware Description Language

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDL allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. Verilog can be used to describe designs at four levels of abstraction: (i) Algorithmic level (much like c code with if, case and loop statements). (ii) Register transfer level (RTL uses registers connected by Boolean equations). (iii) Gate level (interconnected AND, NOR etc.). (iv) Switch level (the switches are MOS transistors inside gates). The language also defines constructs that can be used to control the input and output of simulation.. Some Verilog constructs are not synthesizable. Also the way the code is written will greatly affect the size and speed of the synthesized circuit.

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3: OVERVIEW OF PHYSICAL LAYER OF 802.11A

In this paper, we demonstrate that it is possible to generate efficient hardware for wireless protocol, namely 802.11a written in verilog. This work has grown out of studying the implementation of physical layer of 802.11a wireless protocol, its area-power tradeoffs in the design, the design problem of multi-radios. Modern cell phones usually contain multiple radios, typically three, but sometimes as many as seven, all of which are implemented as special hardware blocks. It would be beneficial to share not only the design cost of such radios but even the actual hardware blocks among those radios that do not operate concurrently. Based on these discussions we focused on OFDM based protocols and built a set of highly reusable IP blocks, which can be instantiated with different parameters for different protocols. Though the development of such modules requires domain expertise, we think the use of such modules in designing and implementing new protocols requires considerably less knowledge. We hope this paper demonstrates how the cost of hardware design, i.e., ASIC blocks, and the time-to-market can be reduced dramatically by reusable

Fig 3.1 OFDM Transceiver block diagram

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3.1 Transmitter Pipeline

TX Controller: Receives information from the MAC and generates the control and data for all the subsequent blocks. Scrambler: Randomizes the data bit stream to remove repeated patterns, like long sequences of zeros and ones. This enables better results for Forward Error Correction (FEC). A scrambler is usually implemented with linear feedback shift registers (LFSR). An LFSR has two algorithmic settings: the size of the shift register and the linear function, e.g., x7 + x4 + 1, for generating the feedback. FEC Encoder: Encodes data and adds redundancy to the bit stream to enable the receiver to detect and correct errors. Both protocols use convolutional coding, however, 802.16 also requires Reed-Solomon encoding before the data is passed to the convolutional encoder. Both protocols also use a technique known as puncturing to reduce the transmitted number of bits. For higher transmission rates in low-noise channels, the encoded data is punctured by deleting bits before transmission and replacing them with fixed values on reception. This reduces the number of bits to be carried over the channel and depends on the decoder to correctly reconstruct the data. Interleaver: Rearranges blocks of data bits by mapping adjacent coded bits into nonadjacent subcarriers to protect against burst errors. The block size is the same as the number of bits that are coded in a single OFDM symbol. The symbol size itself is determined by the number of data subcarriers and the modulation scheme employed. Mapper: Passes interleaved data through a serial to parallel converter, mapping groups of bits to separate carriers, and encoding each bit group by frequency, amplitude, and phase. The output of the Mapper contains only the values of data subcarriers for an OFDM symbol. Pilot/Guard Insertion: Adds the values for pilot and guard subcarriers. The subcarrier indices are protocol-specific. Both protocols use scramblers to generate values for the pilots and use null values for the guard subcarriers. IFFT: Converts symbols from the frequency domain to the time domain. The size of the IFFT is determined by the number of subcarriers used by the given OFDM protocol.

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CP Insertion: Copies some samples from the end of the symbol to the front to add some redundancy to the symbols. These duplicated samples are known as a cyclic prefix (CP). The purpose of the cyclic prefix is to avoid Inter-Symbol Interference (ISI) caused by multipath propagation. This block also adds a preamble before the first transmitted symbol. A preamble is a collection of predefined complex numbers known by the receiver so that it can detect the start of new transmission. The preambles for the two protocols have similar structure. After CP insertion, the symbol are converted into analog signals by D/A converter and transmitted through the air.

3.2 Receiver Pipeline

The functionality of the blocks in the receiver is roughly the reverse of the functionality of their corresponding blocks in the transmitter. However, since the receiver has to recover data from a degraded signal, some receiver blocks have to do more processing and consequently require more implementation effort. When the antenna detects the signal, it amplifies the signal and passes it to the A/D converter to generate baseband digital samples. Synchronizer: Detects the starting position of an incoming packet based on preambles. It is extremely important for the synchronizer to correctly estimate the OFDM symbol boundaries so that subsequent blocks process appropriate collection of samples together. In many implementations, the synchronizer also detects and corrects carrier frequency offset that is caused by the difference in the oscillator frequencies at transmitter and receiver or due to the Doppler Effect. The synchronizer uses the preamble to perform timing and frequency synchronization. There are many different implementations of the synchronizer, most of which involve auto-correlation and cross-correlation. For the synchronizer to support different protocols, it needs to know the preamble structure, the symbol size and the CP size of the protocol. Serial to Parallel (S/P): Removes the cyclic prefix (CP) and then aggregates samples into symbols before passing them to the FFT. It also propagates the control information from the RX Controller to subsequent blocks. FFT: Converts OFDM symbols from the time domain back into the frequency domain.
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Channel Estimator: Uses the information from pilots to estimate and compensate for frequency-dependent signal degradation. The channel estimator estimates and corrects the errors caused by multipath interference. Similar to the synchronizer, there are many different algorithms for channel estimation. Many of them use either the preambles or the pilots to estimate the effect of the interference on each data subcarrier. We parameterize the channel estimator by protocol-specific preamble and pilot values. Demapper: Demodulates data and converts samples to encoded bits, which are used by the FEC decoder. The number of encoded bits generated per sample is determined by the specific modulation scheme. The parameters of this block are modulation schemes supported and the functions for converting samples to decisions. Deinterleaver: Reverses the interleaving performed by transmitter and restores the original arrangement of bits. FEC Decoder: Uses the redundant information that was introduced at the transmitter to detect and correct any errors that may have occurred during transmission. Both 802.11a and 802.16 use the Viterbi algorithm [13] to decode convolutionally encoded data. To support multiple protocols, the decoder uses the same parameter settings as the convolutional encoder at the transmitter side. Since 802.16 also uses Reed-Solomon encoding, corresponding Reed-Solomon decoder that supports appropriate profiles is used in the receiver side. Descrambler: Reverses the scrambling performed by the transmitter. RX Controller: Based on the decoded data received from Descrambler, the RX Controller generates the control feedback to S/P block.

3.3 Project Objective

The objective of this project is to carry out an efficient implementation of the OFDM system (i.e. transmitter and receiver) using Field Programmable Gate Array (FPGA). FPGA has been chosen as the target platform because OFDM has large arithmetic processing requirements which can become prohibitive if implemented in Hardware description language i.e in Verilog. However, the highly pipelined nature of much of the processing lends itself well to a hardware implementation. In addition, FPGA implementation has the added advantage of allowing late modifications in response to real world performance evaluation.
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3.4 Specifications are listed below:

OFDM with 64 sub-carriers (all data sub-carriers) All the sub-carriers are modulated using QPSK IFFT: 64-point. Implemented using FFT radix 22 algorithm Channel coding: Reed Solomon code + Convolution code Reed Solomon Encoder: RS (15, 9) Convolution Encoder: m=1, n=2, k=7. Code rate = Block Interleaver and 1/8 Cyclic Prefix

3.5 Project Design Flow

The design procedure consists of following steps:

Literature survey of complete Physical layer design of OFDM transmitter and receiver

Creating a top level design of the complete system Determining the basic operation of each block and creating the appropriate logic I/O integration of the various logic blocks Description of design functionality using Verilog hardware description language CADENCE and XILINX are used to simulate the design functionality and to report errors in desired behavior of the design

Synthesis of the defined hardware is done which includes slack optimization, Power optimizations followed by placement and routing

FPGA bit stream file is fed to the hardware

3.6 Project scope

Factors such as data rate, allowable bit rate of the input, code rate of the Forward Error correction stage and noise immunity can well define the scope of this project.

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4. Scrambler
Overview of Scrambler
2.1 Introduction of Serial Scrambler Scramblers are a class of substitution ciphers and have been found to be suitable for various security requirements such as those used by cable and satellite TV operators and mobile phone service providers. A Scrambler is a coding operation which basically randomizes the data streams. In addition to its use as a stream cipher, a scrambler is commonly used to avoid long strings of 0s and 1s which are responsible for DC wander and synchronization problems in communication circuits. Scramblers are very popular for their use to encrypt video and audio signals for broadcasting and many other applications. The low cost and complexity, high speed of operation and easy to use are the main features of scramblers. The scrambler is built as a shift register with stages depending on the given characteristic equations. There is feedback taken from stages according to the polynomials listed in the characteristic equation. On the transmit side the scrambler may be started with a preload of a specific data content. This is important later on when we talk about testing. This preload is also called seed. With a known seed and a known input pattern the scrambler output is deterministic, which means the output of the scrambler can be calculated. On the receive side the de-scrambler synchronizes automatically from the incoming data. Once pretty obvious data meaning a sequence of data with known a pattern and easily recognizable is sent through a scrambler, it is no longer meaningful to the human eye. Even a repetitive pattern will no longer be periodic as the scrambling adds the total history to the current data stream. So any periodic or specifics inside the patterns cannot be seen inside a scrambled stream. It needs to be de-scrambled again. At present high-speed transmission or networking specifications, there are serial scramblers in it. Serial scrambler consists of several registers and modulo-2 adders (XOR gates), and interconnected in serial form. Its architecture consists of a shift

register with feedback path which perform modulo-2 addition using the outputs of some registers, which is also called Linear Feedback Shift Register (LFSR), Pseudo-Random Bit Sequences (PRBS) generator and Pseudo noise (PN) generator, etc.. The
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scrambler produces scrambling sequences to perform the operation of modulo-2 addition with input data. The characteristic of scrambler depends on its interconnection. That is to say different feedback connections will produce different output sequences. The output sequences are pseudo-random, which means the sequences are not really random data. It repeats the same sequences after one period, but output sequences within the period are very close to random data. Thus the period is longer, the output sequences are more random. The period of scrambler output sequences is determined by the number of shift register and feedback period of taps. A N-stage scrambler has the maximal

-1 as long as it interconnects properly. The maximal period is also

called Maximal Length Sequences (m-sequences).For example, the period of a 3-stage scrambler, as shown in Fig. 2-2(a), has maximal period 7 ( ), but the period of Fig.

2-2(b) is only 4. The number in the bracket is the output of register that connects to the XOR gate. If the feedback taps connect improperly, it would not produce msequences and its period is shorter. We can describe scrambler by a mathematic equation, which is called Characteristic Polynomial. expression For instance, scrambler of IEEE802.3ae has polynomial ( ) (2-1)

Eqn. (2-1) means that the output of the 7th and 6th register performs XOR operation and the result of operation is fed back to the first register as input, as shown in Fig. 2-3. Whenever the transmission frame starts, all registers of serial scrambler reset to initial condition and then scrambles with input data repeatedly. By this operation, the scrambled output data becomes pseudo-random data and transmitted to the channel. The probability of 1 or 0 of the scrambled output sequences is almost equal ( ( ) ( ) ) and the number of 0 differs from the number of 1 by
( )

one. That is to say the number of 1 is

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The Advantages of Scrambling The input data is scrambled by performing the XOR operation with the scrambler output sequences. Thus, the scrambled data becomes pseudo-random data no matter what the original input data is. It is good to transmit pseudo-random data in the channel for the communication system. It has three advantages for transmitting pseudorandom data and using the scrambler circuit, which will be discussed in details in the following section.

2.2.1

Spread the Spectrum

There are many channels that are used to transmit data simultaneously in communication system. If one of the channels produces large amounts of noise to interfere other channels, it would be troublesome. Actually, if the channel transmitted repetitive sequences of data, from the spectrum point of view, it could have large

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amounts of energy concentrated at some frequencies. These large amounts of energy could lead to electromagnetic impulse (EMI) to affect other channels. However, after scrambling, it becomes random data in time domain and the probability of 1 or 0 is equa1. On the other hand, the transmitted energy is spread more uniform across the transmission frequency band and minimizes the EMI damage to other channels. Data Transitions The transmission format of signal can be classified into two categories: Non-Return to Zero (NRZ) and Return to Zero (RZ).The former is that when data is 1 in high level, it will not change level to low level until data is 0. The latter is on the contrary. When the data is 1 in high level, it will change level to low level after half interval of one bit time, as shown in Fig. 2-5.Thus, the RZ format has more transitions than NRZ in the same transmitted data, and it is beneficial for receiver to synchronize with transmitter by these data transitions. However, the bandwidth requirement of RZ is twice that of NRZ. Therefore, scrambler can be used to make the same effect on NRZ format

for synchronization purpose. If the transmitted data bytes or control signals are long term 0 or 1 during

transmission, after scrambling, the scrambled data will have more transitions and become more random. It can avoid the generation of transmitting a constant control signal for long periods. Encryption The scrambled data is the result of XOR operation on the input data and scrambler output sequences, the scrambled data is quite different from the input data. By doing so, the data transmitted in channel is random and correlation of this sequence is very close to zero. It is random data until the receiver is descrambled, so it is like to encrypt the original data, as shown in Fig.2-6. coder and a descrambler is a decoder.\ In other words, a scrambler can be viewed as a

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4.1 Design of scrambler/descrambler:

A simple implementation of the Scrambler consists of 7 shift registers and 2 XORs as shown in Figure 4.1. The Scrambler is of length-127, meaning it repeatedly generates a 127-bit sequence for a given pseudo-random initial state. Each incoming data bit is XORed with the current bit in the 127-bit sequence. The first 7 bits to be sent into the Scrambler are the beginning of the SERVICE parameter. These 7 bits are re-written with the initial state of the Scrambler so descrambling can be done in the receiver. In order to support various protocols, it is important that our implementations be as flexible as possible. We achieve this by parameterizing the implementation for both data types and widths. We illustrate this by describing the implementation of the scrambler module. The scrambler randomizes the input bit stream by XORing each bit with a pseudo-random binary sequence (PRBS) generated by a linear feedback shift register (LFSR). For example, for the linear function x7 + x4 + 1, we first compute the feedback bit by XORing the 4th and 7th bit of the random number in lfsr. Then, we generate the output bit by XORing inData with the feedback bit. Finally, we compute the new random number by shifting the feedback bit into the current random number. For higher performance, we can process up to steps bits of inData at a time.

Scrambler is designed for the polynomial x7 + x4 + 1 With the initial state 1000000 .

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Fig 4.1 Scrambler circuit diagram Verilog code for implementation of scrambler : module scramblerr(clk,rst,in,sout,lfsr1); input clk,rst,in; output sout; output[6:0]lfsr1; reg [6:0]lfsr; always@(posedge clk or negedge rst ) begin if(!rst) lfsr=7'b1010000; else lfsr={in,lfsr[6:1]}; end assign sout=lfsr[0]^lfsr[4]^in; assign lfsr1=lfsr; endmodule

Descrambler

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Fig 4.2 Scrambler circuit diagram

Verilog code for implementation of descrambler: module descrambler(clk,rst,in,desout,lfsr2); input clk,rst,in; output [6:0]lfsr2; output desout; reg [6:0]lfsr3; reg desout1; always@(posedge clk or negedge rst) begin if(!rst) lfsr3=7'b1010000; else begin desout1=in^lfsr3[4]^lfsr3[0]; lfsr3={desout1,lfsr3[6:1]}; end end assign lfsr2=lfsr3;
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assign desout=desout1; endmodule

Verilog code for implementation of datapath of scrambler/descrambler : module completescramb(in,clk,rst,desout,sout,lfsr1,lfsr2); input in,clk,rst; output sout; output desout; output [6:0]lfsr1,lfsr2; wire sout,desout; scrambler s1(clk,rst,in,sout,lfsr1); descrambler ds1(clk,rst,sout,desout,lfsr2); endmodule

Verilog code for testbench: `timescale 1ns / 1ps module test1; reg in, clk, rst; wire desout, sout; wire [6:0] lfsr1,lfsr2; completescramb u1 (in,clk,rst,desout,sout,lfsr1,lfsr2 ); initial begin clk=1'b1; rst = 1'b0; in=1'b0; #10 rst = 1'b1; end initial begin forever #5 clk=~clk;
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end initial begin # 5 in = 1'b1; # 50 in = 1'b1; # 55 in = 1'b1; # 70 in =1'b 0; # 90 in = 1'b0; # 120 in = 1'b0; # 150 in = 1'b0; # 170 in = 1'b0; # 190 in = 1'b0; # 220 in = 1'b1; # 250 in = 1'b0; # 270 in = 1'b1; # 290 in = 1'b0; # 300 in = 1'b1; # 320 in = 1'b1; # 350 in = 1'b1; # 380 in = 1'b1; # 3000000 $finish; end endmodule

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Fig 4.3 Output waveform of scrambler/descrambler

The Parallel Scrambler: Parallel scramblers are used to achieve high throughput. In IEEE 1394b standard, the input to the transmitter is 8 (or 16) in parallel. So the input works at byte time (8Ts), where Ts is the bit time. But serial scramblers produce output sequences only one bit in a clock cycle. Therefore, it transforms serial scrambler output to parallel outputs by bitshift registers, as shown in Fig. 2-7. The output of serial scrambler is connected to bit-shift registers, and bit-shift registers shift one bit data from the serial scrambler output at one clock cycle. The eight parallel registers generate parallel scrambler data after bitshift registers shifting eight bits data. It totally needs one byte time to produce eight parallel scrambler outputs, which is the same as serial scrambler that takes eight clock cycles of bit time to generate scrambler output bit by bit.

Thus, due to the technology limitation, it cannot work at very high scrambling rate. Thus, a new architecture and algorithm i.e parallel scrambler, which can overcome the disadvantage mentioned above has been developed. In general, multiples of base rate signals are multiplexed and then scrambled before transmission
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and then is descrambled and demultiplexed after reception in the receiver end, as shown in Fig. 3-1(a). Scrambling used to be done serially or be done as paralleling bit-shift outputs, mentioned in section 2-3. Nevertheless, as the operating frequencies of transmission systems grow beyond Gbps, serial scrambling techniques were no longer applicable in these specifications. For example, in 10 Gbps Ethernet or 40 Gbps fibre transmission, with serial scrambling method, this would mean the scrambler shall work at frequency of 10/40 GHz which is not feasible with todays silicon-based CMOS integrated circuits. The requirement of high working frequency can be resolved by using parallel scrambling techniques [9-13] to enable the scrambling process at the lowfrequency base rate, as shown in Fig. 3-1(b). Under parallel scrambling, sets of scrambling processes are performed at the base rate simultaneously, which collectively achieves the effect of serial scrambling when the scrambled base-rate signals are multiplexed to form a

transmission-rate signal.

A common characteristic of all well-known parallel solutions

is that the number of inputs of the modulo-2 adders (XOR gates) used in the feedback loops of the pseudorandom code generator is more than two for some parallel ports. However, having to process the modulo-2 additions of more than two inputs will lead to an increase in the processing delay and lower the maximum working rate. Moreover, in todays deep sub-micron CMOS process, number of fan-outs and interconnection length also become a significant factor that affect the processing delay. Thus, the architecture shall be regular and have less fan-outs in the critical path.

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4.2 FEC Codes

FEC(Forward Error correction) codes add redundancy to the input bit streams to enable the receiver to detect errors that are incorporated during transmission. We can retrive the lost data without retransmission using these FEC codes. Here we use convolution codes as FEC codes 4.2.1 Convolutional Encoder: Convolutional coding is part of the Forward Error Correction done in communication systems. The purpose of forward error correction (FEC) is to improve the capacity of a channel by adding some carefully designed redundant information to the data being transmitted through the channel [4]. The process of adding this redundant information is known as channel coding [4]. Convolutional codes operate on serial data, one or a few bits at a time. There are a variety of useful Convolutional, and a variety of algorithms for decoding the received coded information sequences to recover the original data. Convolutional codes are usually described using two parameters: the code rate and the constraint length. The code rate, m/n, is expressed as a ratio of the number of bits into the Convolutional encoder (m) to the number of channel symbols output by the Convolutional encoder (n) in a given encoder cycle. The constraint length parameter, K, denotes the "length" of the Convolutional encoder, i.e. how many k-bit stages are available to feed the combinatorial logic that produces the output symbols. Convolutional codes are often used to improve the performance of digital radio, mobile phones, and satellite links. In the proposed design a Convolutional encoder with a code rate of has been chosen i.e. m=1 and n=2. A constraint length of 7 is kept because it is standard and its decoding can be efficiently done using the popular Viterbi Decoding Algorithm.

4.2.2 Encoder Design

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Figure 4.4 Convolutional Encoder Figure 5.1 shows the I/O parameters of the Convolutional Encoder. Input bus is 1 bit wide and arst_n is the asynchronous reset input. A negative edge on the arst_n input resets the encoder. A bit is latched in at the positive edge of the clock. For every input bit there is a two bit wide output designated by even and odd.. Convolutional Encoder can be implemented using either a shift register or by using . However, a shift register gives an easy to implement and area efficient solution. For the configuration of m=1, n=2 and k (constraint length) =7. Figure 5.1 shows how the Convolutional encoder is implemented in the proposed design using a shift register. Initially all zeroes are stored in the register. When the first input bit arrives it is shifted into the register from left and the 2 bit output appears on the lines designated as even and odd. The even output is generated by adding the contents of 1st, 0, 3rd, 4th and 6th stages of the shift register, whereas the odd output is generated by adding the 5th, 0, 3rd, 4th and 6th stages of the register. This addition is modulo-2 addition carried out through XOR gates (modulo-2 addition is basically a XOR operation). Just like the Scrambler the memory elements here are D-flip-flops as well.

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Verilog code for implementation of Convolutional Encoder: module convolencode(in,clk,rst,out); input in,clk,rst; output [1:0]out; reg [2:0]a; always @(posedge clk or negedge rst) begin if(!rst) a=3'b000; else begin a={in,a[2:1]}; end end assign out[0]=a[2]^a[1]^a[0]; assign out[1]=a[2]^a[0]; endmodule

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Fig 4.5 output waveform of Convolution Encoder

4.2.3 Convolutional decoder:

The Viterbi decoder block decodes the convolutional encoded user data symbols by using the Viterbi algorithm for decoding.A Viterbi decoder uses the Viterbi algorithm to decode bitstreams encoded using a convolutional forward error correction code. The algorithm determines the most likely input bitstream given the received noisy encoded stream. To understand the Viterbi algorithm, it helps to understand the convolutional encoder. A k-bit convolutional encoder is a state machine consisting of 2k states, with transitions between states conditional on input bits and emitting a fixed number of output bits. In these two protocols, 2 bits are emitted per input bit. The current state of the encoder is named by the last k input bits. Because transitions are conditional on a single bit, each state of the encoder can be reached only from two previous states. The Viterbi algorithm uses dynamic programming to find the most likely state transition sequence followed by the encoder given a received bit sequence. The algorithm retraces this sequence of states to reconstruct the original bit stream. Too much time and memory would be required for the decoder to wait until it has received the entire data sequence before producing a result. However, we can achieve almost the same level of accuracy by recording only the last n transitions, and emitting one bit per timestep. In practice, a value of n = 5(k + 1) yields satisfactory results. For 802.11a and 802.16, k = 6, so n = 35.

Viterbi decoder is a basic and important block in any Code Division Multiple Access (CDMA), and CDMA system uses forward error correction schemes like convolution encoder to prevent interference. The Viterbi algorithm may be viewed as a solution to the problem of maximum a posteriori probability estimation. One of the main blocks of a modem used during forward link demodulation is a Viterbi decoder. A normal Viterbi decoder trace back firstly and then decoding results. The aim of this paper was to design Viterbi decoder for high throughput. It means that this design can continuously trace back and simultaneously process decoding results. In this way, the Viterbi decoder is more

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efficient. This has been the focus in the present thesis on convolutional decoder suing viterbi algorithm.Several important design issues have also been discussed in the thesis report, such as organization of convolution encoder and Viterbi decoder, branch metric unit computation method, the design of add compare select, parallel unit of trace back and decoder. Fig.1. The structure of Viterbi decoder BMU (Branch Metric Unit) receives the input signals and compute the difference between the input signals and the expected values, and then outputs the results to the Add Compare Select. ACS (Add Compare Select) completes the survivor paths and generates the decision vector. This module has two comparers, and these two comparers are parallel. The one is used for comparing signal bit and the other is used for comparing data bits. The advantage of this design is considerably reducing the circuit timing delay [7].MEMORY is cycle used for saving the survivor paths [8].The core unit of this design is the TB (Trace Back) [9] and DECODER, which include two function modules. The one is TB that read the information of the survivor paths in the MEMORY. The other is DECODER that computes the output results. These two modules work simultaneously but in different MEMORY address. In this way, the Viterbi decoder is more efficient than a normal one because the DECODER do not need to wait TB. In our implementation, the Viterbi decoder consists of two modules: the path metric unit and the Traceback unit. The path metric unit contains a 2k word memory, where each entry is essentially the probability that a sequence of input bits ended in that state. In practice, cumulative error between the hypothesized bit stream and the received bit stream for that state is used as the path metric for that state. The traceback unit records the most likely n state sequence leading to each state, encoded as one bit per state transition, logically organized as an n entry shift register where each entry is 2k bits. The path metric unit updates all 2k entries for every 2 observations received from the demapper module. Once all the new path metrics are computed, the old path metrics can be discarded. As it computes each new path metric, it records the previous state pointer in the traceback unit. After the path metric unit updates the values for all the states, the traceback unit follows the recorded previous state pointers and emits the bit corresponding to the oldest transition in the sequence.
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Fig 4.6 Add-Compare-Select unit

Path Metric Unit: The path metric unit, which is shown in Figure 4, contains one or more Add-CompareSelect (ACS) units for calculating the path metrics for each state. The ACS computes two path metrics at a time, as shown in Figure 5. The number of ACS units, which is a parameter to the path metric unit, controls number of path metrics updated per cycle. The overall structure of the path metric unit is similar to that of a single FFT stage with the FFT butterflies replaced by the ACS units. With the generalized pipelining technique presented in ,we can easily parameterize the design of the path metric unit with the number of ACS units. This parameterization represents a tradeoff between area and power: the area increases as we increase the number of ACS units, while the power decreases.

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Fig 4.7 Path Metric Unit for K=3

Traceback Unit: The traceback unit contains a n2k bit shift register and a decoder which reconstructs one bit at a time by traversing the most likely state transition sequence. Traversing n = 35 transitions in one cycle leads to long cycle times. To reduce the critical path, we pipelined the traceback unit, with a parameterized pipeline depth. In the pipelined implementation of the traceback unit, a single pipeline stage in the decoder traverses s pointers. There are t such stages, such that s t = n and n = 35. Each pipeline register needs to store one traceback memory column of 2k bits and a current state index. We varied the number of pipeline stages (1, 5, 7 and 35) to analyze various design alternatives. Figure 6 shows the area and power measurements for different pipeline depths.

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The results reflect the minimum frequency required to support the 54 Mbps bitrate for 802.11a. The figure also shows the number of bits written to the traceback memory per cycle and the complexity of the address decode logic for reading out the bits from the traceback memory, which is the input size of the multiplexing logic to read the data from each element of the shift register. The results show that the 5-stage decodes consumes the least area and least power.

Implementation: In this report two architectures have been implemented.

1) Fixed constraint length architecture. 2) Parameterized constrained length architecture

1) Fixed constraint length architecture: 2) Parameterized constraint length architecture: In this architecture the the constraint length can be varied

5. CONCLUSIONS AND FUTURE DIRECTIONS

Various other modules present in the physical layer of 802.11a wireless protocol architecture are further studied and are to be implemented individually in verilog following a systematic manner and are checked till we obtain the desired results.
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First al individual blocks of the transmitter section is to be done and then later the receiver section is to to be implemented. All the individual blocks are to be integrated to complete the transmitter and the receiver pipelines and are integrated to get the complete design of the physical layer design of 802.11a wireless protocol. After the successful simulations of the design of the physical layer of 802.11a wireless protocol 8is carried out then we implement it on the FPGA, which will result in the fulfillment of the hardware implementation of the physical layer design of the 802.11a wireless protocol. Later Ill study and work on the implement the physical layer of the 802.11g wireless protocol which is similar to the 802.11a protocol. Ill the get the hardware implementation of the 802.11g protocol and ill compare the results of the two protocols. Ill undergo a keen study of the differences in the two protocols and then ill furnish the difference between those two protocols. And Ill find out the other techniques that can be incorporated in the two protocols, to make the wireless protocol more efficient and transmit data with higher data rates. The comparative study of the two protocols will be carried and final report will be submitted on the comparative study of the two wireless protocols.

6. REFERENCES
[1] Indian Journal of Science and Technology Vol.2 No. 10 (Oct 2009) ISSN: 09746846,Research article Secure data communication Bhat et al.Indian Society for Education and Environment (iSee) http://www.indjst.org Indian J.Sci.Technol.41.

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[2]

Design and Simulation of IEEE 802.11g (WLAN) Based PHY,A dissertation submitted by Raj Kumar Vaishya ,INDIAN INSTITUTE OF TECHNOLOGY, DELHI.

[3]

Design and Implementation of a Parallel Processing Viterbi Decoder Using FPGA Lei -ou Wang 1, Zhe-ying Li 1 iInstitute of Micro-electronic Application Tech,B eijng Union University Beijing, China.

[4]

Multi-Clock Pipelined Design of an IEEE 802.11a Physical Layer Transmitter Maryam Mizani and Daler Rakhmatov University of Victoria Department of Electrical and Computer Engineering 2006 IEEE.

[5]

On the design of an FPGA-Based OFDM modulator for IEEE 802.11a.2nd International Conference on Electrical and Electronics Engineering (ICEEE) and XI Conference on Electrical Engineering (CIE 2005) Mexico City, Mexico. September 7-9, 2005.

[6]

Design and Simulation of IEEE 802.11g (WLAN) Based PHY,A dissertation submitted by Raj Kumar Vaishya ,INDIAN INSTITUTE OF TECHNOLOGY, DELHI.

[7]

On the design of an FPGA-Based OFDM modulator for IEEE 802.11a.2nd International Conference on Electrical and Electronics Engineering (ICEEE) and XI Conference on Electrical Engineering (CIE 2005) Mexico City, Mexico. September 7-9, 2005.

[8]

Multi-Clock Pipelined Design of an IEEE 802.11a Physical Layer Transmitter Maryam Mizani and Daler Rakhmatov University of Victoria Department of Electrical and Computer Engineering 2006 IEEE.

[9]

VHDL modeling and simulation of data scrambler and descrambler for secure data communication G.M. Bhat*, M. Mustafa**, Shabir Ahmad** and Javaid Ahmad.

[10]

VHDL modeling and simulation of data scrambler and descrambler for secure data communication G.M. Bhat*, M. Mustafa**, Shabir Ahmad** and Javaid Ahmad

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[11]

A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog ByDr. S. Ramachandran Indian Institute of Technology Madras, India Digital Integrated Circuits A Design Perspective 2/e Jan M. Rabaey, Anantha handrakasan, Borivoje Nikoli Chapters 6 and 11.

[12]

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