Acquisition System Panel

ASP manual

Avalon Sciences Ltd

January 2000

Contents
Introduction 2
About the ASP..................................................................................................................... 2 Repair strategy .................................................................................................................... 3 Test adapter board............................................................................................................... 3

Specifications

Analog inputs ...................................................................................................................... 4 Telemetry input ................................................................................................................... 4 Telemetry control ................................................................................................................ 4 Physical ............................................................................................................................... 5 Environmental ..................................................................................................................... 5

System description

Overview............................................................................................................................. 6 STE bus............................................................................................................................... 6 CPU board........................................................................................................................... 6 GPIB board ......................................................................................................................... 7 IO board .............................................................................................................................. 7 MTX board.......................................................................................................................... 8 DRX board .......................................................................................................................... 8 Seismic input board........................................................................................................... 11

Calibration

13

ASP gain calibration.......................................................................................................... 13

Acquisition System Panel

Contents i

Introduction

About the ASP

The ASP (Acquisition System Panel) connects to any standard PC or notebook via an IEEE488 GPIB interface device (available from National Instruments) converting the PC into a powerful VSP data acquisition system. The ASP is fully supported by the ACQ module from the VSProwess software package.

Analogue geophones
The ASP may be used with single or dual analogue geophone systems. The analogue input and external control connectors are essentially compatible with those on the earlier analogue only DAQ unit. But note that the ASP does not have an internal airgun firing module.

SST500
The ASP is primarily designed to form part of the SST500 digital borehole seismic system. The ASP can send commands to the SST500 downhole digitisers (via the SCP and STU) and can receive the incoming serial datastream, merging this with the data from the digitised surface channels.

MSR
The ASP may also be used in conjunction with the Sercel MSR digital borehole seismic system without modification. There is one restriction. At the highest MSR sample rate of 4000 Hz (250 us) the ASP can operate with only two surface channels, which must be channels 7 and 8. These channels have been chosen because they are the ones most commonly assigned as reference channels.

Acquisition System Panel

Introduction 2

Repair strategy
Two ASPs are supplied with each SST500 system. We recommend that no attempt should be made to repair a faulty ASP. It should be returned to Avalon Sciences, via CGG Ravensbourne, suitably packaged and accompanied by a description of the problem. The use of high density programmable logic devices all but excludes the possibility of any successful board level repair. Board swapping between systems is not recommended because it may easily result in damage to cables or previously functional boards. The technical information contained within this manual is provided only as an aid to understanding the operation and use of the ASP.

Test adapter board

Please note that at the time of writing the AS2049 test adapter board does not exist. It is planned that this board will provide an interface to an external test system to enable instrument tests for both the ASP and SST500 systems.

Acquisition System Panel

Introduction 3

Specifications

Analog inputs
Analog channels Sample interval Record duration Converter Dynamic range Bandwidth 8 2, 1, 0.5, 0.25 ms 32 seconds 24 bit delta-sigma better than 102dB 3-187 Hz @2ms 3-375 Hz @1ms 3-750 Hz @0.5ms Phase Timing accuracy Maximum input voltage Inter-channel skew Distortion Gain accuracy DC offset Linear phase +/-25ppm over operating temperature 20 volts peak to peak None better than 0.05% better than 0.5% Auto-calibrated

Telemetry input
Data-rate Format 512 kbps sustained (2 Mbps burst rate) SST500 frame (max 120 byte frames)

Telemetry control
Data-rate Format Communications 8192 bits per second SST500 manchester Full-duplex RS422 or simplex RS485 to 19,200 bps

Acquisition System Panel

Specifications 4

Physical
Chassis Weight 3U, 19 inch 10 Kg

Environmental
Storage temperature Operating temperature EMI/EMC Power supply Power dissipation -20 to 55 degrees centigrade 0 to 50 degrees centigrade Shielded case 85-264 volts ac auto-ranging 30 watts

Acquisition System Panel

Specifications 5

System description

Overview
Drawing AS918 provides a block diagram of the ASP system and also shows the connector pin-outs likely to be of interest.

STE bus
The ASP is constructed around the industry standard STE bus. This decision allowed us to use some off the shelf parts (especially during the development phase) but also means that external signals have to connect to the boards via ribbon cables just behind the front panels. If it should become necessary to remove a board from the rack please use care not to damage any ribbon cables. Damaged ribbon cables can produce intermittent faults and are awkward to replace. Although the STE bus allows you to insert any board into any slot, the physical location of the interface cables mandate that each board must be inserted into the correct slot for normal operation. Drawing AS917 shows the correct location of each board. All active circuitry is contained on the pull out boards, except for the two bus terminator strips which are installed into the back of the backplane. A terminator fault is possible, but unlikely.

CPU board
The AS2040 CPU board is the system controller and employs a Motorola 68HC001 microprocessor running at 16.384 MHz. This device has an 8 bit interface mode which simplifies its application to the 8 bit STE bus. The CPU board also contains a 32Kbyte EPROM and 128Kbyte RAM. The EPROM contains only a small amount of bootstrap code. The main code is downloaded from the PC each time the ASP is reset. This procedure allows us to implement code updates simply by including a new version of the ASP program code file (ASP.bin) as part of each new VSProwess software release.

Acquisition System Panel

System description 6

Watchdog reset
The 1232 reset supervisor device includes a watchdog timer which must be periodically pulsed by a command from the CPU in order to hold off the reset signal. In the event that the CPU crashes or hangs up in some obscure loop then the watchdog timer expires and the system is automatically reset.

Code download
Immediately after a system reset, whether initiated by power up or by a watchdog timeout, the boot code in the EPROM asserts the SRQ (service request) signal on the GPIB bus and waits. The PC routinely checks the status of the SRQ signal and responds by conducting a serial poll of the ASP, which returns a value indicating that a code download is required. The PC therefore performs a code download and instructs the ASP to transfer control to the downloaded code. The entire process takes only a couple of seconds and is largely transparent to the user. We rely on the watchdog reset mechanism to recover from many common error conditions.

System clock
The CPU board provides an accurate and stable 16.384 MHz oscillator whose output is distributed to all boards via the backplane SYSCLK signal. The sampling clock is ultimately derived from this signal.

GPIB board
The AS2041 GPIB board uses the UPD7210C device and provides an IEEE488 (GPIB) interface for communication with the PC. The bus lines are filtered to reduce the EM emissions for which the GPIB bus is notorious.

IO board
The AS2047 IO board provides the interface to external source controllers via the EXT CTL connector.

Relay outputs
The IO board provides four isolated relay outputs (relays A-D) allowing the ASP to trigger any one of four source controllers. The relays are solid state optoMOS devices to ensure fast bounce-free operation. Each relay is protected against transient damage by a series resistor and transient absorber. The relay drive circuits are not prone to spurious operation upon system power up or down.

Acquisition System Panel

System description 7

Opto-isolated inputs
The IO board provides (as standard) four opto-isolated inputs, of which only two are presently used. One acts as a remote start input, eg to support walkaway operations and the other provides an external trip facility. +5 volts is available at pin 8 of the EXT CTL connector to drive the opto-isolators from relays.

Clock divider
The IO board divides the system clock to generate the 1.024 MHz signal required by the Seismic input boards.

MTX board
The AS2045 MTX (manchester transmitter) board allows the ASP to send manchester encoded commands to the SST500 system. The command signals are transformer isolated within the SCP (AS2045B board) both to avoid the risk of high voltages getting onto the interconnect cable and also because the command signals must share conductors with motor power.

Manchester encoding
Manchester encoding the command signal removes the dc component to permit transformer coupling. It also reduces the command signal bandwidth ratio, provides error detection capability and is self-clocking to simplify the data recovery process.

Efficient transmission
Rebooting the SST500 system involves transmitting unique program code to each of the digitiser modules. For a 12 sonde system this may require sending up to 50 kilobytes of data. The transmission rate is fixed at a lowly 8192 bits per second to avoid problems caused by signal distortion on long cables.But the data are transmitted with very low overhead in one kilobyte blocks.

Serial communications to SCP

The MTX board also provides a selectable two pair RS422 or single pair RS485 serial link to allow commands and status to be sent to and from the SCP. At the time of writing there is no software support for this link.

DRX board
The AS2046 DRX (data receiver) board allows the ASP to receive the serial datastream from the SST500 system.

Acquisition System Panel

System description 8

RS422 inputs
Four signals (RS422 differential pairs) are received from the SST500 SCP. The important ones are the DATA and CLOCK signals. The CLOCK signal is filtered and used to strobe the DATA signal into a shift register within the programmable logic device PLD-B. The LOCK signal (and its LED repeater LOK) indicates that the telemetry receiver in the SCP has locked onto a carrier signal. The ERROR signal indicates that the current databit is known to be in error.

Error display
PLD-C contains an error counter whose outputs drive a bank of 8 red LEDs on the DRX board front panel. This counter is reset at the beginning of each record. The top seven red LEDs (E1-E7) contain a binary representation of the number of errors which have occurred with E1 representing the least significant bit of the count. The bottom LED (E8) indicates that more than 128 errors have occurred. The purpose of the error display is to give some indication of the rate at which errors are occuring. Do not expect the error display to exactly mirror the display on the SCP, because the error counter on the SCP is not routinely reset as is the counter in PLD-C. Also you may observe that errors occur in groups of four, this is a consequence of the line coding algorithm used by the SST500 telemetry system. Note that if the SCP is not connected then the RS422 inputs may float to either state and you may observe that all of the red LEDs (and some of the green ones) appear to be continuously driven.

Frame
Databits are sent from the SST500 system packaged into frames. Each frame consists of preamble, sync code, scan count, checksum and all of the bytes for all of the downhole channels for one sample interval or scan. There is a short gap between consecutive frames which accomodates any slippage between the telemetry and sampling clocks.

Sync detection
PLD-B contains a shift register whose outputs are continuously compared against a standard sync pattern. If a match is detected it is assumed that a data frame is being received. A programmed number of bits (the size of the frame) are received, converted from serial to parallel and transferred into the 8Kbyte FIFO (first-in first-out) register. The ninth bit of the FIFO holds a flag indicating the location of the first byte of a frame.

Acquisition System Panel

System description 9

Reading the FIFO

Data transfer from the FIFO register to the PC via the GPIB bus does not commence until the FIFO is half full, as indicated by the HF flag, enabling efficient block transfers. Read accesses to the FIFO are restricted to a duration of about 50ns to avoid data corruption during the sensitive read phase. PLD-A buffers the FIFO data for the extended access period required by the STE bus.

Acquisition System Panel

System description 10

Seismic input board

There are normally eight AS2044 seismic input boards, fitted in slots 1 to 8 and digitising analogue channels 1 to 8 respectively. The seismic input board employs the same delta-sigma analogue to digital converters as used in the SST500 downhole digitisers and the channel characteristics are almost an exact match. Each seismic input board must have the correct channel identifier code set on its DIP switches. See the table below.

DIP switch settings

SW1 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 OFF ON OFF ON OFF ON OFF ON SW2 OFF OFF ON ON OFF OFF ON ON SW3 OFF OFF OFF OFF ON ON ON ON SW4 ON X X X X X X X

SW4 enables the DRDY interrupt. One or more of the boards must have SW4 turned on to allow proper system operation.

DC offset measurement
The input signal passes through a transient protected analog switch network which enables the amplifier inputs to be routed to ground to permit measurement of any system offsets. Input offset and very low frequency offset drift (<1Hz) is removed by the single pole low-pass filter formed by C31,C32 and R9.

Maximum input voltage

The maximum input voltage is 20 volts peak to peak (actually there is a certain amount of over-range capability). This level is too high for the delta-sigma converters which employ five volt supplies, so instrumentation amplifier U7 is actually configured as an attenuator. This does have a small impact on the effective dynamic range of the channel but makes it better suited to its typical applications of near field monitor or pre-amplified downhole signals.

Acquisition System Panel

System description 11

Gain calibration
Diode D10 and operational amplifier U9A form a 4.1 volt reference which may be adjusted over a small range to compensate for channel gain errors, allowing gain calibration.

Acquisition System Panel

System description 12

Calibration

ASP gain calibration

The ASP has no internal test input switching networks. You must connect an external test source to the analog connector. Install an optional AS2073 Test Signal Generator and CAB-ANATEST cable. The AS2073 TSG (Test Signal Generator) option is now available. The TSG automatically performs gain calibration during an instrument test. Alternatively use the following procedure. (1) Remove the ASP top cover. (2) Run the ACQ program and create a job with the ASP + ANALOG option. (3) From the file menu select Gain calibration. (4) Apply a low distortion 31.25 Hz, 5.303 volt rms sine wave signal source to channel 1 with all other inputs shorted to ground and adjust the gain calibration potentiometer until the display reads 5303 millivolts. Please use a plastic adjuster to avoid damage if dropped into the unit. (5) Repeat the procedure for the remaining channels. (6) If the reading appears to be displayed against the wrong channel then check that the DIP switches are correctly set. While the top cover is removed this can be done without removing the seismic input boards.

Acquisition System Panel

Calibration 13

Printed 15-Jan-2000

B1

EUROCARD J1 CPU logic s2040_2.sch

MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10

A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A27 A28

MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANA-

MD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+

C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30

MD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9

CM0 /ADRSTB /DATACK /ATNREQ0 /ATNREQ2

GND /DATSTB /SYSRST /ATNREQ1 /ATNREQ3

SYSCLK

A29 A30

VCC

DIN41612 C64 PLUG

C2 100n

C3 100n

C4 100n

C5 100n

C6 100n

C7 100n

C8 100n

C9 100n

C10 100n

C11 100n

C1

10u

GND

Avalon Sciences Ltd

Somerset, England

Title

CPU Board -master sheet

Dwg.

AS2040

Sheet

of

Rev.

Printed 15-Jan-2000

U10 TX RX 11 12 10 9 1 TX1IN RX1OUT TX2IN RX2OUT C1+ TX1OUT RX1IN TX2OUT RX2IN 14 13 7 8 GND RS232 VOUT+ VOUT5 C2LT1281 GND U10 NOT FITTED LINK U10-12 to U10-16 via 0.125W resistor 6 4 2 J2 HDR-6 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 /IPL0 /IPL1 /IPL2 GND FC0 FC1 FC2 VCC 22 R2 10K U9 /HALT /RST MCLK1 GND MCLK2 MCLK3 R3 10K /VPA VCC 21 23 24 19 20 15 18 30 29 28 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 27 26 25 5 3 1 /PBRST RX232 TX232 2 6 TX232 RX232 VCC A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 1 2 3 4 5 6 7 8 9 10 11 12 13

U8 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 27C256 A14 A13 A8 A9 A11 /OE A10 /CE IO7 IO6 IO5 IO4 IO3 27 26 25 24 23 22 21 20 19 18 17 16 15 A14 A13 A8 A9 A11 GND A10 /ROM D7 D6 D5 D4 D3 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

U7 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE IO7 IO6 IO5 IO4 IO3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A15 /MWR A13 A8 A9 A11 WNR A10 /RAM D7 D6 D5 D4 D3

VCC 1 2 3 J3 1Mbit - link 1&2 4Mbit - link 2&3

A17

+
C12 1u 3 4 C1C2+

+
C13 1u GND VCC D1 R1 270 LED 8 16384 KHz Somerset, England

C15

C14

1u

1u

SRAM WNR D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9

U1 1 2 3 4 5 6 7 8 9 RP2 100K GND D1 D3 D5 D7 D9 D11 D13 D15 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /STE MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7

1 2 3 4 5 6 U6 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 IPL0 IPL1 IPL2 FC0 FC1 FC2 E VMA VPA BERR HALT RESET CLK MODE MC68HC001FN16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AS R/W UDS LDS DTACK BR BG BGACK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 6 9 7 8 10 13 11 12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 /AS RNW /DS /DTACK VCC VCC /PBRST VCC VCC 1 2 3 7 8 9 RP1 100K U5 MCLK2 /ATNREQ0 /ATNREQ1 /STE /BAS /BDS WNR /RAM /ROM D0 /HALT /IPL0 /IPL1 /IPL2 /VPA /AS /DS RNW FC1 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20

GND D0 D2 D4 D6 D8 D10 D12 D14

IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQL U4 /PB TD TOL LTC1232 /ST /RST RST

IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN

40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21

/ATNREQ2 /ATNREQ3 /DATACK A21

U2 VCC A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /STE MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7

TR1 2N7000

/MWR

A22 A23 /DTACK LED /AUXWR TX FC0 MRST RX U3 A8 A9 A10 RNW /STE /BAS /BDS /RST MCLK3 GND 2 4 6 8 1 17 15 13 11 19 1A1 1A2 1A3 1A4 1G 2A4 2A3 2A2 2A1 2G 74ACT244

1Y1 1Y2 1Y3 1Y4

18 16 14 12

MA8 MA9 MA10 CM0

R4 51 R5 51 R6 51

7 6 5

/AUXWR /RST MRST

2Y4 2Y3 2Y2 2Y1

3 5 7 9

/ADRSTB /DATSTB /SYSRST SYSCLK

Avalon Sciences Ltd

Title

CPU Board

Dwg.

AS2040

Sheet

of

Rev.

Printed 15-Jan-2000

STE Interface s2041_2.sch

U11 U9 REN IFC NDAC NRFD DAV EOI ATN SRQ 25 23 21 19 17 15 13 11 9 7 5 3 1 HDR-26 GND ATN SRQ IFC NDAC NRFD DAV EOI DIO4 DIO3 DIO2 DIO1 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 3 4 5 6 7 8 9 10 REN IFC NDAC NRFD DAV EOI ATN SRQ REN IFC NDAC NRFD DAV EOI ATN SRQ 20 19 18 17 16 15 14 13 25 24 38 37 36 39 26 27 U8 REN IFC NDAC NRFD DAV EOI ATN SRQ RS2 RS1 RS0 23 22 21 GA2 GA1 GA0

J2 GND GND GND GND GND GND GND REN DIO8 DIO7 DIO6 DIO5 26 24 22 20 18 16 14 12 10 8 6 4 2

D0 D1 D2 D3 D4 D5 D6

12 13 14 15 16 17 18 19

FILTER-DIP

BDC

12 1 GND

DC SC 75162 U10

TE

2 1

GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7

D7 T/R1 CLK

3 4 8 9 10

U12 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 B1 B2 B3 B4 B5 B6 B7 B8 75160 FILTER-DIP

TE PE D1 D2 D3 D4 D5 D6 D7 D8

1 11 19 18 17 16 15 14 13 12

5 35 34 33 32 31 30 29 28

T/R3 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 UPD7210

RST CS RD WR

GCLK GRST /GCS /GRD /GWR

T/R2 IRQ DMAREQ DMAACK

2 11 6 7

DC GIRQ DMAREQ /DMAACK

VCC

EUROCARD

+
C2 10u C3 100n C4 100n C5 100n C6 100n C7 100n C8 100n C9 100n C10 100n C11 100n C12 100n C13 100n C14 100n C15 100n C16 100n C17 100n C18 100n

B1 GND

Avalon Sciences Ltd

Somerset, England

Title

GPIB Board

Dwg.

AS2041

Sheet

of

Rev.

Printed 15-Jan-2000

/FWR GND BD1 BD3 BD5 BD7 GND /FF GD7 GD5 GD3 GD1

LC1

U5 1 2 3 4 5 6 7 8 9 10 11 12 13 W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 AM7203 D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R 27 26 25 24 23 22 21 20 19 18 17 16 15 LC2 BD0 BD2 BD4 BD6 VCC /FRST /EF /HF GD6 GD4 GD2 GD0 /FRD 1 2 3 4 5 RP1

VCC DIR SW1 1 2 3 4 8 7 6 5 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 1 2 3 4 5 6 7 8 9

U1 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 MD0 MD2 MD4 MD6 MA0 MA2 23 22 21 20 19 18 17 16 15 14 13 /BEN DIR /FWR /RDSTAT GACCESS CM0 CM1 /DATACK /ATNREQ3 CM2 MA6 MA8 MA10 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 GA2 GA1 GA0 BSYSRST GND BSYSCLK GND 74HCT14 ENACK /SYSRST BSYSRST MA1 MA2 DIR GACCESS /GBEN IRQ GACK C1 100p GND D1 BAT85 R1 470 CONN_C64_STE SYSCLK /BEN A27 A28 A29 A30 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANAMD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+ C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30 MD1 MD3 MD5 MD7 MA1 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /BEN MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7

SW1 SW2 SW3 SW4

GND

J1

U2 MA6 MA7 MA8 MA9 MA10 MA11 IRQ GACK BDATSTB BADRSTB ENACK G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /RDSTAT BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 1 2 3 4 5 6 7 8 9 10 11 IN IN IN IN IN IN IN IN IN IN IN IO IO IO IO IO IO IO IO IO IO IN

MA7 MA9 MA11

U6 VCC SW1 SW2 SW3 SW4 /FF /HF /EF /EF 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245

CM0 CM2 /ADRSTB /DATACK

CM1 /DATSTB /SYSRST /ATNREQ3

GAL22V10

U4 MA0 DC DMAREQ /FRST GCLK GRST BDC /DMAACK 1 2 3 4 5 6 7 8 9 11 12 13 14 15 /FRD GND GND GND GIRQ 16 17 18 19 20 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQL

U7 DIR GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 /GCS G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /GBEN BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 /GRD /GWR

U3 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 6A 6Y 5A 5Y 4A 4Y 13 12 11 10 9 8 /DATSTB BDATSTB /ADRSTB BADRSTB SYSCLK BSYSCLK

Avalon Sciences Ltd

Somerset, England

Title

GPIB Board - STE Interface

Dwg.

AS2041

Sheet

of

Rev.

Printed 15-Jan-2000

TLOKLO TERRLO TDATLO

J2 10 8 6 4

9 7 5 3 1

TLOKHI TERRHI TDATHI

TCLKLO

TCLKHI

HEADER-10 J1 TERRHI J3 16 14 12 10 8 6 4 2 15 13 11 9 7 5 3 1 HEADER-16 TERRLO TDATHI TDATLO TCLKHI STXHI SRXHI TCLKLO TLOKHI TLOKLO MTXHI MTXHI MTXLO STXHI STXLO SRXHI SRXLO CCTVSIG CCTVRTN ICOMBODY ICOMTIP A B C D E F G H J K L M N P R S T U V CONN-20A48 ICOMBODY ICOMTIP J4 J5

STXLO SRXLO

MTXLO

CCTVSIG CCTVRTN

J6 J7

Avalon Sciences Ltd

Somerset, England

Title

ASP connector adaptor board

Dwg.

AS2042

Sheet

of

Rev.

Printed 15-Jan-2000

B1

EUROCARD Analog interface s2044_3.sch STE Interface s2044_2.sch

VCC

C2 100n

C3 100n

C4 100n

C5 100n

C6 100n

C7 100n

C8 100n

C9 100n

C10 100n

C11 100n

C12

10u

GND

Avalon Sciences Ltd

Somerset, England

Title

Seismic Input Board

Dwg.

AS2044

Sheet

of

Rev.

Printed 15-Jan-2000

U4 SOD MA3 MA5 ARST SYNC ARNW /ACS RSEL SID 1 2 3 4 5 6 7 8 9 11 12 13 CONNECT DRDY BSYSRST 14 15 16 17 18 19 20 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500L VCC 1 2 3 4 5 RP1 10K SIP5 SW1 SW1 SW2 SW3 SW4 1 2 3 4 8 7 6 5 ON=1 SW4 =ON = Enable DRDY interrupt IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 MA0 MA2 MA1 MA4 BD5 BD4 BD7 BD6 BD2 BD3 BD0 BD1 DIR BD1 BD0 BD3 BD2 BD5 BD4 BD7 BD6 1 2 3 4 5 6 7 8 9

U1 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANAMD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+ C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30 VANA+ MD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /BEN MD1 MD0 MD3 MD2 MD5 MD4 MD7 MD6 J1

IRQ ENBEN /RDA SCLK /WRB

U2 MA6 MA7 MA8 MA9 MA10 MA11 IRQ ENBEN BDATSTB BADRSTB ENACK 1 2 3 4 5 6 7 8 9 10 11 IN IN IN IN IN IN IN IN IN IN IN IO IO IO IO IO IO IO IO IO IO IN 23 22 21 20 19 18 17 16 15 14 13 /BEN DIR /RDA SCLK /WRB CM0 CM1 /DATACK /ATNREQ1 CM2

CM0 CM2 /ADRSTB /DATACK

CM1 /DATSTB /SYSRST /ATNREQ1

GND

GAL22V10

U5 11 12 MSYNC MFLAG MCLK MDATA 13 5 6 7 10 14 15 16 17 18 19 TDATA CSEL HNS MSYNC MFLAG MCLK MDATA PWDN USEOR DECC DECB DECA ORCAL CS5322 /CS SYNC CLKIN RESET RNW RSEL SCLK SID 1 2 3 4 28 27 26 25 /ACS SYNC ACLK ARST ARNW RSEL SCLK SID D1 BAT85 R1 470 1 SOD ERROR DRDY 24 23 22 SOD DRDY C1 100p GND ENACK /SYSRST BSYSRST /ANACLK ACLK 2 3 4 5 6 VANA/BEN A27 A28 A29 A30

/ANACLK

C64 PLUG U3 1A 1Y 2A 2Y 3A 3Y 13 12 11 10 9 8 /DATSTB BDATSTB /ADRSTB BADRSTB

6A 6Y 5A 5Y 4A 4Y

74HCT14

GND

Avalon Sciences Ltd

Somerset, England

Title

Seismic Input- STE Interface

Dwg.

AS2044

Sheet

of

Rev.

Printed 15-Jan-2000 R12 C21 J2 EPG0B303HLN 1 2 3 R15 100 12 14 13 3 R6 R16 J3 1 2 3 D11 SA12C C33 10n C34 10n D12 SA12C GND 100 226K 9 10 11 2 GND AD7592 GND GND GND GND GND /WR 4 6 R7 1M 2 3 R8 1M U7 AMP01 7 18 1 U8 14 R5 4K99 GND IN+ 15 C31 U9B 9 470n C32 R9 470n IN8 200K 5 6 + OP200 R10 GND GND 1K 7 100n 1K CONNECT

VA+ BSIG R13 10K R11 1K R14 100 3 2 OP200 U9A + 1 R17 12K4 0.1% REF

D10 TC04

C29 47u

C30 47u

C18 100n

GND GND

R18 4K7 V1 VR1 500R R2 220 U6 AREF C28 47u GND R3 220 R4 220 AINR AIN C27 BAT85 IP OP V1 D4 D5 D6 D7 D2 D3 0.22 GND C16 100n C15 100n C14 100n GND C13 100n C26 0.22 8 3 21 GND C17 0.22 5 REF+ VDD VDD MSYNC MFLAG MCLK MDATA /MDATA 2 22 25 24 20 18 17 V1 AINVSS VSS CS5321 HBR LPWR OFST 26 27 28 MSYNC MFLAG MCLK MDATA

6 10 9

REFAINR AIN+

L1 2.2mH VANA+

VA+

U10 78L05

VANA-

IP

OP

V2

5V6

5V6

C37 4.7u

C38 4.7u

C22 100n

C23 100n GND

C35 4.7u

C36 4.7u

Avalon Sciences Ltd

Somerset, England

Title

L2 2.2mH

VA-

U11 79L05

D8

D9

C25 10u

C24 10u

GND

Seismic Input Board -Analog interface

+
Dwg.

AS2044

Sheet

of

Rev.

Printed 15-Jan-2000

VARIANTS &A B1 &B Part fitted only to "B" variant (SCP) Part fitted only to "A" variant (ASP)

EUROCARD External Interface s2045_3.sch STE Interface s2045_2.sch

VCC

C18 100n

C19 100n

C20 100n

C21 100n

C22 100n

GND

VCC

C2 10u

C3 100n

C4 100n

C5 100n

C6 100n

C7 100n

C8 100n

C9 100n

C10 100n

C11 100n

C12 100n

GND

Avalon Sciences Ltd

Somerset, England

Title

MTX Board

Dwg.

AS2045

Sheet

of

Rev.

Printed 15-Jan-2000 &B Link pin 4 to pin 24 (MPO =1) U6 (&A) /RDB RXD TXD MPO GND BA2 BA1 BA0 FO 3.68 MHz 5 BSYSRST 1 2 3 4 5 6 7 8 9 10 11 /RD RXD TXD MPO MPI A2 A1 A0 CLK X2 RST SCC2691 GND VCC 74ACT245 R2 10K MD0 MD2 MD4 MD6 MA0 MA2 MA4 IO IO IO IO IO IO IO IO IO IO IN 23 22 21 20 19 18 17 16 15 14 13 /BEN DIR /RDA /RDB /WRA /WRB CM0 CM1 /DATACK /ATNREQ3 CM2 MA6 MA8 MA10 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 D1 BAT85 R1 Must be fitted to both variants U5 1 1024KHz R12 10K 2 3 FO DO EN EXO-3 GND C B A 7 6 5 ENACK /SYSRST BSYSRST /ATNREQ7 B1024KHz VCC GND U3 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 74HCT14 6A 6Y 5A 5Y 4A 4Y 13 12 11 10 9 8 /DATSTB BDATSTB /ADRSTB BADRSTB SYSCLK C1 100pF 1K C64 PLUG A27 A28 A29 /BEN A30 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANAMD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+ C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30 MD1 MD3 MD5 MD7 MA1 /WR D0 D1 D2 D3 D4 D5 D6 D7 /CE /IRQ 23 22 21 20 19 18 17 16 15 14 13 /WRB BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7

(&A) U7

U1 1 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /BEN MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7

J1

U4 1 MPO GND EN485TX BA2 BA1 BA0 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQ IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 MA0 MA2 MA1 MA4 BD4 BD5 BD6 BD7 BD3 BD2 BD1 BD0 MA6 MA7 MA8 MA9 MA10 VCC MA11 IRQ BDATSTB BADRSTB ENACK 1 2 3 4 5 6 7 8 9 10 11

U2 IN IN IN IN IN IN IN IN IN IN IN GAL22V10 IRQ OSCEN /RDA /WRA /WRB

MA7 MA9 MA11

CM0 CM2 /ADRSTB

CM1 /DATSTB /SYSRST /ATNREQ3 /ATNREQ7

SD /CTS /TXRST X32CLK ENCCLK BSYSRST

GND

Avalon Sciences Ltd

Somerset, England

Title

MTX board - STE Interface

Dwg.

AS2045

Sheet

of

Rev.

Printed 15-Jan-2000 EN485TX RS485 option SRXLO SRXHI R3 120 MAX483 VCC VCC U10 STXLO STXHI R4 D2 D3 D4 D5 120 MAX483 J3 SA5 8 6 4 2 7 5 3 1 JUMPER (&A) (&B) GND GND GND STXLO SRXLO MRXLO GND MTXLO 16 14 12 10 8 6 4 2 J2 15 13 11 9 7 5 3 1 RS232OUT RS232IN GND STXHI SRXHI MRXHI GND MTXHI Link 1&2, 7&8 Link 2&4, 6&8 Link 3&4, 5&6 RS422/485 comms RS422 to RS232 converter RS232 comms VCC 1 2 SD 3 4 5 6 7 8 9 U12 BZI BOI UDI SD SDO /SRST /NVM DCLK /RST HD6409 GND VCC VCC /BOO /BZO SS ECLK /CTS MS OX IX CO 19 18 17 16 15 14 13 12 11 VCC /BOO /BZO ENCCLK /CTS 7 6 B A RO RE DE DI 1 2 3 4 R11 10K RXD TXD R9 10K R10 10K VCC C13 1u C16 1u VCC 7 6 U9 RO B A RE DE DI 1 2 3 4 GND 11 12 10 9 1 U13 (&B) TX1OUT RX1IN TX2OUT RX2IN 14 13 7 8 GND RS232 2 6 RS232OUT RS232IN TX1IN RX1OUT TX2IN RX2OUT C1+

+
3 4 C1C2+ VOUT+ VOUT5 C2LT1281

C15 1u

C14

+
1u GND

16 pin header for ASP 16 pin HE14 R/A header for SCP

/TXRST

X32CLK

GND

R7 10K MRXHI R5 470 U14 (&B) 1 2 4 3 HCPL2731 Y2 6 Y1 7

R8 10K U11 /BOO /BZO 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 74HC132 D6 1Y 2Y 3Y 4Y 3 6 8 TC4427 11 2 4 U8 INA INB OUTA OUTB 7 5 R13 51 R14 R6 270 51 C17 22nF

MTXHI 9 7 4 10 6 3 MTXLO T1 (&B) J4 Wireline 1 Motor power D7 Wireline 4 (&B) Farnell 264-386 (&B) 3 2 1 Terminal block

MRXLO

T8K150

GND

Avalon Sciences Ltd

Somerset, England

Title

MTX Board - External Interface

Dwg.

AS2045

Sheet

of

Rev.

Printed 15-Jan-2000

B1 EUROCARD

External Interface s2046_3.sch

STE Interface s2046_2.sch

VCC

Avalon Sciences Ltd

Somerset, England

Title

+
C2 10uF C3 100n C4 100n C5 100n C6 100n C7 100n C8 100n C9 100n C10 100n C11 100n C12 100n C13 100n C14 100n C15 100n C16 100n GND

DRX Board

Dwg.

AS2046

Sheet

of

Rev.

Printed 15-Jan-2000

/FWR Y0 Y2 Y7 Y5 YFLAG /FF QFLAG BD5 BD7 BD2 BD0

LC2 1 2 3 4 5 6 7 8 9 10 11 12 13

U5 W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 AM7205RC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R 27 26 25 24 23 22 21 20 19 18 17 16 15 LC1 Y1 Y3 Y6 Y4 VCC /FRST /EF /HF BD4 BD6 BD3 BD1 /FRD U1 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 MD0 MD2 MD4 MD6 MA0 MA2 23 22 21 20 19 18 17 16 15 14 13 /BEN DIR /RDA /RDB /WRA /WRB CM0 CM1 /DATACK CM2 MA6 MA8 MA10 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 D1 BAT85 C1 100pF GND U3 T5 IRQ LEDEN /RDB /WRA /WRB ENACK /SYSRST BSYSRST NRZCLK /NRZCLK 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 74HCT14 6A 6Y 5A 5Y 4A 4Y 13 12 11 10 9 8 /DATSTB BDATSTB /ADRSTB BADRSTB SYSCLK R1 470 C64 SYSCLK /BEN A27 A28 A29 A30 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANAMD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+ C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30 MD1 MD3 MD5 MD7 MA1 G B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /BEN MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7

J1

GND

U2 MA6 MA7 MA8 MA9 MA10 VCC MA11 IRQ BDATSTB BADRSTB ENACK 1 2 3 4 5 6 7 8 9 10 11 IN IN IN IN IN IN IN IN IN IN IN IO IO IO IO IO IO IO IO IO IO IN

MA7 MA9 MA11

CM0 CM2 /ADRSTB /DATACK

CM1 /DATSTB /SYSRST

GAL22V10 U4 /FF QFLAG /EF T0 T1 T2 T3 /FRST 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQ PLD-A IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 MA0 MA2 MA1 /HF BD4 BD5 BD6 BD7 BD3 BD2 BD1 BD0 /ATNREQ2

/FRD T4 T6 RXEN /RDA FRAME LOCK BSYSRST

Avalon Sciences Ltd

Somerset, England

Title

DRX Board - STE Interface

Dwg.

AS2046

Sheet

of

Rev.

Printed 15-Jan-2000

VCC

VCC R7 1K 1A 1B 4A 4B 2A 2B 3A 3B 1 2 12 13 4 5 9 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 U9 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQL 1A 1B 4A 4B 2A 2B 3A 3B 1 2 12 13 4 5 9 10 U7 TLOKHI R2 120 TLOKLO TDATHI R3 120 U8 TLOKHI TERRHI TDATHI TCLKHI 2 3 4 5 6 7 15 14 13 12 11 10 TLOKLO TERRLO TDATLO TCLKLO TERRLO DA05P TCLKLO TERRHI R5 120 15 4B LTC488 TDATLO TCLKHI R4 120 9 14 3B 4A G G 4 12 GND GND 7 10 2B 3A 3Y 1 6 1B 2A 2Y 5 NRZDAT 1Y 3 LOCK 2 1A PLD-C IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 U6 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQ PLD-B IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 FRAME T4 LEDEN /NRZCLK T0 T1 T2 T3 /FWR Y0 Y2 Y7 Y5 YFLAG

D2 "LOK" D3 "1" D4 "0" D5 "FRM" D6 "E1" D7 2 3 D8 4 5 6 D9 7 8 470 D10 RP3 D11 1 2 3 D12 4 5 6 D13 "E8" 7 8 470 8 6 11 3 8 6 11 RP2 1 3 2 3 4 5 6 7 8 270 8 6 11 RP1 1 3

U10 1Y 4Y 2Y 3Y 74LS38 U11 1A 1B 4A 4B 2A 2B 3A 3B 1 2 12 13 4 5 9 10

Y1 Y3 Y6 Y4 4 J3 Test access T5 T6 RXEN NRZDAT 3 2 1

1Y 4Y 2Y 3Y 74LS38 U12

ERROR LOCK BSYSRST

FRAME NRZDAT /NRZCLK

1Y 4Y 2Y 3Y 74LS38

Test access J4 4 3 2 1

11

TLOKLO TERRLO TDATLO GND TCLKLO

10 8 6 4 2 J2

9 7 5 3 1

TLOKHI TERRHI TDATHI GND TCLKHI

4Y

13

ERROR

VCC

R6 100 C17 100p

NRZCLK

Avalon Sciences Ltd

Somerset, England

Title

DRX Board

Dwg.

AS2046

Sheet

of

Rev.

Printed 15-Jan-2000

EUROCARD

External Interface s2047_3.sch

DAC output s2047_4.sch

STE Interface s2047_2.sch

B1

+5

VCC

+
C11 10uF

C2 100n

C3 100n

C4 100n

C5 100n

C6 100n

C7 100n

C8 100n

C9 100n

C10 100n

GND

Avalon Sciences Ltd

Somerset, England

Title

IO Board- master sheet

Dwg.

AS2047

Sheet

of

Rev.

Printed 15-Jan-2000

U6 RLYB /RLYB RLYC /RLYC /IN7 IN7 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 74ACT14 6A 6Y 5A 5Y 4A 4Y 13 12 11 10 9 8 RLYA /RLYA RLYD /RLYD /IN6 IN6

RLYB RLYA U1 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 74ACT245 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 D1 BAT85 R1 C1 100p GND U3 470 C64 PLUG A27 A28 /BEN A29 A30 MD0 MD2 MD4 MD6 MA0 MA2 MA4 MA6 MA8 MA10 MA12 MA14 MA16 MA18 CM0 CM2 /ADRSTB /DATACK /TFRERR /ATNREQ0 /ATNREQ2 /ATNREQ4 /ATNREQ6 /BUSREQ0 /BUSACK0 SYSCLK VANAG B1 B2 B3 B4 B5 B6 B7 B8 19 18 17 16 15 14 13 12 11 /BEN MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 RLYD RLYC

5 4 3 2 1 GND RP4

10K

U7 /IN5 IN5 /IN3 IN3 /IN1 IN1 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 74ACT14 13 12 11 10 9 8 /IN4 IN4 /IN2 IN2 /IN0 IN0

J1

6A 6Y 5A 5Y 4A 4Y

MD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11 MA13 MA15 MA17 MA19 CM1 /DATSTB /SYSRST /ATNREQ1 /ATNREQ3 /ATNREQ5 /ATNREQ7 /BUSREQ1 /BUSACK1 VSTBY VANA+

C3 C4 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C20 C22 C23 C24 C25 C26 C27 C28 C29 C30

MD1 MD3 MD5 MD7 MA1 MA3 MA5 MA7 MA9 MA11

U2 MA6 MA7 MA8 1 2 3 4 5 6 7 8 9 10 11 IN IN IN IN IN IN IN IN IN IN IN IO IO IO IO IO IO IO IO IO IO IN 23 22 21 20 19 18 17 16 15 14 13 /BEN DIR /RDA /RDB /WRA /WRB CM0 CM1 /DATACK /ATNREQ2 CM2

U4 /RDA /WRB DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 RLYB RLYA RLYC IN7 IN6 IN5 IN3 IN1 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 IN IN IN IO0 IO1 IO2 IO3 IO4 IO5 IO17 IO16 IO15 IO14 IO13 IO12 IN IN IN IN ATV2500BQ CLK128K U5 BSYSCLK 1 2 3 4 5 6 CLK CLR QG QF QE QD 74HC4024 CLK1024K CLK512K CLK256K NC QA QB NC QC NC 13 12 11 10 9 8 CLK4096K CLK2048K 8 6 4 2 IN IN IN IN IO6 IO7 IO8 IO9 IO10 IO11 IO23 IO22 IO21 IO20 IO19 IO18 IN IN IN 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 /WRA MA2 MA1 BSYSRST BD4 BD5 BD6 BD7 BD3 BD2 BD1 BD0 RLYD IRQ AUXOP IN4 IN2 IN0

R15 10K

MA9 MA10 VCC MA11 IRQ BDATSTB BADRSTB ENACK

GND

CM0 CM2 /ADRSTB

CM1 /DATSTB /SYSRST

GAL22V10

BCLK1024K

R3 270 (was 51) TR1 2N7000 R23

1 /SYSRST BSYSRST 7 5 3 1 J3 2 3 4 5 6

GND

1A 1Y 2A 2Y 3A 3Y 74ACT14

6A 6Y 5A 5Y 4A 4Y

13 12 11 10 9 8

/DATSTB BDATSTB /ADRSTB BADRSTB SYSCLK BSYSCLK

AUXOP

R23 fitted for SSP only 0805 fitted to rear of TR1

10K

Avalon Sciences Ltd

Somerset, England

Title

IO Board - STE Interface

Dwg.

AS2047

Sheet

of

Rev.

Printed 15-Jan-2000 J2 (13) (25) 25 24 VAUX+ VAUX-

NC

26 +5 RP3 2 3 6 7 D3 26D580 8 3 2 1 4 5 6 7 8 270 19 17 18 16 R7 22 D5 26D580 R6 22 D4 26D580 U9 5 6 7 8 AQW214 +5 4 3 2 1 1 2 3 4 5 6 7 8 9 RP1 /IN7 VCC /RLYC /RLYD /RLYA

(12) Relay B (11) (24) Relay A (23)

23 21 22 20

R4

22 D2 26D580

U8 5 4

/RLYB

R5

22

(10) Relay D (9) (22) Relay C (21)

D25 connector pin numbers in brackets

(8)

15

R8

27R PR01

D14 SA5 2K2 U11 1 D6 3 2 3 D7 4 5 D8 6 7 D9 8 13 12 11 10 9 15 14 16

RP2 (20) (7) (19) (6) 14 13 12 11 2 4

GND 1

/IN6

5 6 7 8 270

/IN5

/IN4

(18) (17) (5) (4) (16) Remote start (15) (3) External trip (2) (14) (1)

10 8 9 7 6 4 5 3 2 1

R12

270

U10 R11 270 1 D10 2 3 R10 270 D11 4 5 D12 R9 270 D13 8 1N4448 TIL199 GND 9 6 7 11 10 /IN0 13 12 /IN1 15 14 /IN2 16 /IN3

GND

Avalon Sciences Ltd

Somerset, England

Title

IO Board -External Interface

Dwg.

AS2047

Sheet

of

Rev.

Printed 20-Jul-2001
3V3 DAC & routing s2073_2.sch DHA test and ADC s2073_3.sch Regulators s2073_4.sch 7 5 3 1 5x2 GND 2 +5 10 RLY8n RLY1n RLY7n RLY2n RLY6n RLY3n RLY5n RLY4n 11 12 13 14 15 16 17 18 U7 VCC GND Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 A8 A7 A6 A5 A4 A3 A2 A1 9 8 7 6 5 4 3 2 1 RLY8 RLY1 RLY7 RLY2 RLY6 D1 DTACK DIR RLY5 RLY4 GND BENn RLY4 RLY5 RLY3 RLY6 RLY2 RLY7 RLY8 RLY3 J1 GND U2 GND A0 50 49 48 47 46 45 44 42 40 37 36 35 33 32 30 29 28 27 41 31 A1 A2 G10 G12 D13 D12 D10 G13 D11 G11 G2 G3 G4 G5 D6 D5 D4 D3 D2 G6 D1 G1 A3 H14 C14 C13 C12 C11 C10 C6 C5 H3 C3 C2 TCK A14 A13 A12 F10 A10 A6 A5 A4 A3 A2 TDO CLK4/IN4 CLK3/IN3 CLK0/IN0 CLK1/IN1 E0 E1 E14 E13 E12 E6 E5 E4 E3 E2 B0 B10 B12 B11 B2 B3 B4 B5 B6 B1 F6 F5 F4 F3 F2 TDI U5 XCR3128XL H2 TMS F15 F14 F13 H13 H12 H11 H10 H6 H5 25 24 23 22 21 20 19 17 16 15 14 13 12 10 9 8 7 6 5 4 2 1 TDI RD2 RD3 TMS A10 RWn ASn DSn ENTBUS MUX5 MUX2 MUX0 MUX1 GND A8 A9 A10 RWn ASn DSn MTX RSTn 1 2 3 4 5 6 7 8 9 A0 A1 A2 A3 BSEL A6 A7 A8 A9 U3 DIR A1 A2 A3 A4 A5 A6 A7 A8 G B1 B2 B3 B4 B5 B6 B7 B8 74ALS245 BASn 19 18 17 16 15 14 13 12 11 GND MA8 MA9 MA10 BRWn BASn BDSn BMTX BRSTn BSYSCLK VATBUS+ GND GND BDTACKn BMTX BRWn A6 A7 4 ESI WCLK BCLK 74AHCT1G14 U26 1 MUX1 2 NC A ! Y 4 ECK SDAT CMODE MUX3 MUX4 CONVn ADCDAT ADCCLK TCK ! Y 4 ECSn ECS RA16 RA15 74AHCT1G14 U16 ECSn BUSYn +5 1 2 3 CS SO WP HD SCK SI FM25C160 U8 GND RA16 RA14 RA12 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RD0 RD1 RD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 A15 A17 WE A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 SRAM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RA15 +5 76 77 78 79 80 83 84 85 87 88 89 90 92 93 94 96 97 98 99 MWRn RA13 RAMn MRDn RSTn RA10 MTX RA11 RA9 RA11 MRDn RA10 RAMn RD7 RD6 RD5 RD4 RD3 1 2 3 4 5 6 SYSCLK BUSYn RA8 RA9 RA5 RA4 RA3 RA2 +5 RD7 RD6 RD0 RD5 RD4 RA0 RA1 RD1 BDTACKn U4 1A 1Y 2A 2Y 3A 3Y 74LS14 6A 6Y 5A 5Y 4A 4Y DTACK 13 12 11 10 9 8 BSYSCLK R25 39R SYSCLK GND TR1 FDV301N 100 81 RA6 7 6 5 +5 ECK ESI RA14 MWRn RA12 RA13 RA7 RA8 TDO 67 68 69 70 71 72 73 75 52 53 54 55 56 57 58 60 61 62 63 64 65 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 G B1 B2 B3 B4 B5 B6 B7 B8 74ALS245 19 18 17 16 15 14 13 12 11 GND MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 +5 BD0 BD2 BD4 BD6 MA0 MA2 MA4 MA6 MA8 MA10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 BSYSCLK -12 VCC GND C64 PLUG NC +12 VCC GND BRW BLRX BAS DTACK VFDBUS ATN2 BDSP ID0 GND ID2 BDS ID1 RST ATN1 ATN3 BLRXWR GND VCC BD0 BD2 BD4 BD6 MA0 MA2 MA4 MA6 MA8 MA10 GND VCC BD1 BD3 BD5 BD7 GND MA1 MA3 MA5 MA7 MA9 BCOMM C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 VA+ TBUSGND GND GND BDSn GND BRSTn GND +5 BD1 BD3 BD5 BD7 GND MA1 MA3 MA5 MA7 MA9 RLY1 D0 D2 D3 D4 D5 D6 D7 GND U6 ESDA6V1SC5 5 4 3 1 J4 10 8 6 4 2 TDO TDI TMS TCK 1 2 3 4 5 RAMn 10K BENn R10 22K R8 22K U1 DIR D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 DIR A1 A2 A3 A4 A5 A6 A7 A8 G B1 B2 B3 B4 B5 B6 B7 B8 74ALS245 19 18 17 16 15 14 13 12 11 BENn BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 RP1 3V3 3V3

ULN2803A U25 1 MUX0 2 NC A ! Y

74AHCT1G14 U27 1 ECS R15 22K GND 2 NC A

VFDRD VFDWR

Avalon Sciences Ltd

Somerset, England

Title

Test Signal Generator (TSG) board -Bus interface

Dwg.

AS2073

Sheet

of

Rev.

Printed 30-Jun-2001

DAC output voltage -5.3V to +5.3V

U12 SDAT RL1 OH1 AGN 5V TPH OH5 RL5 AGN 5V TPH BCLK 1 2 3 D BCLK NC REFDC NC SERVO 19 18 17 R1 4K42 C10 47p GND TPL RLY1n GND TPL RLY5n WCLK 7 8 9 10 WCLK NC 20B INV PCM1704U D1 1SS355 D5 GND GND GND GND TPH OH6 U17 2 RP2 RLY2n 3 2 8 U13B 6 D2 1SS355 D6 1SS355 GND RL3 OH3 AGN 5V TPH OH7 TPH GND TPL RLY3n GND TPL RLY7n D17 SMBJ15CA CHASSIS R18 1K R17 TPL D18 SMBJ15CA TPH OH8 CHASSIS TR2 FDV301N D12 1SS380 1K R31 1K GND +5 TPLA AGN2004 TPHA R26 1K RL9 R11 100R R13 1M R14 1M R12 100R TBUSTBUS+ RL7 AGN 5V TPH 5 5 + OPA2227 6 U15B + 7 DG419 R4 1K 5 1 6 3 VA5+ 2 VL U15A + GND VA5VA5R2 1K IO NC BPODC 14 13 12 3 2 U14A + OPA2227 R3 19K1 R5 19K1 C7 1n C6 1n 1 R7 19K1 C12 220p C8 470p

Fc = 8KHz

R9 1K

6 5

U14B + OPA2227 C11 47p

VDAC

OL1

OL5

+5

+5

R38 10K C57 100n

CMODE

1SS355

C3 100uF

C4 100uF

C5 100uF

RL2 OH2

AGN 5V TPH

RL6

AGN 5V

OL2

GND TPL

OL6

GND TPL

RP-MPM-1002-1002-A 1

1 OPA2227

+5

RLY6n

+5

7 OPA2227

OL3

OL7

+
D3 1SS355

+5

+
D7 1SS355

+5

RL4 OH4

AGN 5V TPH

RL8

AGN 5V

OL4

GND TPL

OL8

GND TPL

ENTBUS R28 100K

R32 10K

GND TR3 FDV301N C44 100n GND GND R37 470K

RLY4n

+
D4 1SS355

+5

RLY8n

+
D8 1SS355

+5 GND

GND

Avalon Sciences Ltd

Somerset, England

Title

Test Signal generator (TSG) board -DAC and routing relays

Dwg.

As2073

Sheet

of

Rev.

Printed 27-Jul-2001
R39 AGN2004 RL10 TR6 BSS129 51R C29 10n VA-

D24 SMBJ15CA J2 CHASSIS ENPWRn AUX12AUX12+ GND IN4 IN3 IN2 IN1 OL8 OH8 OL7 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 DB25PN J3 OH1 OL1 OH2 OL2 OH3 OL3 OH4 OL4 OH5 OL5 OH6 OL6 OH7 SMBJ15CA CHASSIS AUX12+ D25 AUX12-

C58

VA+ TR5 BSS129

+
+5 D11 1SS355

10n R40 51R

+5 OH1 OL1 OH2 OL2 OH3 OL3 OH4 OL4 OH5 OL5 OH6 OL6 OH7 REF5+ VDAC 4 5 6 7 12 11 10 9 14 GND VA+ ENPWRn R30 1K R20 1M C13 1u R29 1K D26 NOT FITTED D22 1SS380 13 2 8 1 16 15 3 D23 1SS380 VAVA+ MUX3 MUX4 GND R16 499R 3 1 8 2 LT1167 + U24 5 6 GND VA+ 1 2 3 C27 4u7 C14 1u 4 VIN NR GND VO TP U18 8 7 6 5 REF5+ U23 1 2 NC A ! Y 4 TR4 FDV301N

26 CHASSIS ENPWRn AUX12AUX12+ GND IN4 IN3 IN2 IN1 OL8 OH8 OL7 24 22 20 18 16 14 12 10 8 6 4 2

25 23 21 19 17 15 13 11 9 7 5 3 1

NC7S14M5

GND

MUXB
U20 S1 S2 S3 S4 S5 S6 S7 S8 GND DG508 A0 A1 A2 VAD VA+ EN

CHASSIS

HDR-26

MAX6250

GND

MUXA
U21 GND R33 1M R34 1M R35 1M R36 1M R21 1K R22 1K R23 D14 D13 SMBJ15CA 14V D15 14V D16 14V 1K R24 GND 1K CHASSIS VAIN4A 4 REF5+ TPLA TPHA 5 6 7 12 11 10 9 14 S1 S2 S3 S4 S5 S6 S7 S8 GND DG508 A0 A1 A2 VAD VA+ EN 13 2 8 1 16 15 3

D20 1SS380 2 8 MUX0 MUX1 MUX2

U19

VA5+ 3 VL 5 1 6 2

OPA2227 + U13A R6 U22 1 1 2 3 4 5 6 7 8 C15 1u C16 1u R1in GND R2in R3in BUF CAP REF GND VA5+ PWRD BSY CS CNV EXT DAT DCLK 16 15 14 13 12 11 10 9 GND ADCDAT ADCCLK BUSYn ECS CONVn VA5+

IN1 IN2 IN3 IN4

DG419 MUX5

1K

D21 1SS380

ADS7812/13

Range +/-10V

GND

Avalon Sciences Ltd

Somerset, England

Title

Test Signal Generator board -Downhole amplifier test and ADC

Dwg.

As2073

Sheet

of

Rev.

Printed 30-Jun-2001
3V3 +5

C42 100n

C41 100n

C40 100n

C39 100n

C38 100n

C56 100n

C55 100n

C54 100n

C53 100n

C52 100n

C51 100n

C50 100n

C49 100n

C48 100n

C47 100n

C46 100n

GND

GND

+5

VCC 1 3 2

U11 VIN EN GND BYP VO 5 4

3V3

C2 100u 6V3

C1 100u 6V3

C22 10u

C21 10u

C20 10u

R19 2R2 C19 10u 10V C9 470p

+
VA5+ VA5-

C43 100n

+
GND U9 1 2 C25 10u C24 10u C23 10u 3 4 VO NC GND U10 1 2 C18 10u C17 10u C26 10u 3 4 VOVIVINC GND

MIC5205-3.3BM5

R27 1K

GND

VA+ 8 7 6 5 C34 4u7 C33 4u7 C32 4u7 C31 4u7

VI

GND GND GND GND NC

LM78L05ACM GND

NC VIVIGND

8 7 6 5

LM79L05ACM

GND

C30 4u7

C37 4u7

C36 4u7

C35 4u7

VA-

GND1

D9

S2K GND GND D10

HOLE1 HOLE2 ESDPAD1 GND ESDPAD2 GND CHASSIS GND

S2K C45

100n C60 100n GND

Avalon Sciences Ltd

Somerset, England

Title

Test Signal Generator board -Regulators

Dwg.

As2073

Sheet

of

Rev.