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Ti li u tham kh o
Digital Systems, 5th Edition, R.J. Tocci, Prentice Hall, 2001 Digital Logic Desgn Principles, N. Balabanian & B. Carlson John Wiley & Sons Inc., 2004
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Introduction
What is a counter?
Count 1,2,3100 and back to 1,2.. Or represent in state diagram
12 10
2 8
4 6
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Introduction
Counter using FF JK FF used to count 3 bits numbers started from 000 to 111 Input J=K=1 Clock has negative going transition Q0Q1Q2 start with 000 and end up with 111
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Example
First step involved in building a digital clock is to take the 60 Hz signal feed into a Schmit-trigger, pulse-shaping circuit to produce a square wave. The 60 Hz square wave is then put into a MOD60 counter which is used to divide the 60 Hz frequency by exactly 60 to produce a 1 Hz waveforms. This 1 Hz waveform is fed to a series of counters, which then count seconds, minutes, hour, and so on, How many FFs are required for the MOD-60 counter?
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Frequency Division
Each FFs divides the frequency of it input by 2. Thus if we were added a second FF to the chain, the output of the second FF would have a frequency equal to of the clock frequency. Using the appropriate number of FFs, this circuit could divide a frequency by any power of two. Using N FFs would produce an output frequency from the last FF which is equal to 1/2N of the input frequency.
1 1
J
CLK FF
Q Q 1
J
CLK FF
Q Q 1 1
J
CLK FF
Q Q
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Frequency Division
Output of each FF basically provides an output frequency half the frequency of the waveform To illustrates this, see figure below.
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Frequency Division
The clock signal is 16kHz. The waveform at output A is an 8-kHz square wave At output B it is 4 kHz and at output C it is 2 kHz In any counter, the signal at the output of the last FF will have a frequency equal to the input clock frequency divided by the MOD number of the counter
output signal frequency = input CLK freq MOD number
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2.
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NAND o/p LOW clear the counter to 000 then NAND o/p goes back HIGH
MOD 6
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001
010
This counter counts from 000(zero) to 101(five) and then recycle to 000. It skips 110 and 111 so that it goes through only six different states MOD-6 counter. Glitch caused by the momentary occurrence of the 110 state before clearing.
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IC Asynchronous counter
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IC Asynchronous counter
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Example
Show how the 74LS293 should be connected to operate as a MOD-16 counter with a 10-kHz clock input. Determine the frequency at Q3.
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Example
Show how to wire the 74LS293 as a MOD-10 counter
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Example
Show how to wire a 74LS293 as a MOD-14 counter
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Example
A way to get a MOD-60 counter is shown below. Explain how this circuit works.
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This limitations can be overcome with the use of synchronous or parallel counters The function is the same to count number, but the operation is different
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Presettable Counters
Presettable can be preset to any desired starting count either asynchronous or synchronous. Many synchronous counters that are available in ICs are designed to be presettable. This presetting operation is also referred to as parallel loading the counter. The J,K & CLK inputs are wired for operation as a parallel up counter. The asynchronous PRESET & CLEAR inputs are wired to perform asynchronous presetting. To load the counter with any desired count at any time by:
1. 2. Apply the desired count to the parallel data inputs, P2, P1 & P0. Apply a LOW pulse to the PARALLEL LOAD input, PL
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Presettable Counters
Draw the output waveform and understand the operation of presettable counter
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74LS193/HC193
This is MOD 16 presettable up/down counter with synchronous counting, asynchronous preset and asynchronous master reset
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74LS193/HC193
Pin Description
Clock Inputs CPU and CPD Refer to Mode Select, if Mode in Count Up CPD must in HIGH state and for Count Down CPU in HIGH state Master Reset (MR): Active HIGH and reset the counter in 0000 state Preset Inputs: P3 P0 Count Outputs: Q3 Q0 Terminal Count Outputs: are used when two or more ICs are connected as a multistage to produce larger mode
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74LS193/HC193
(a) Logic on the 74ALS193 for generating TCU ; (b) logic for generating TCD
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Example
Draw the output waveform Q and Terminal Count of the 74HC193
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Waveform of 74HC193
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Explanation
At t0 the counter FFs are all low. This causes TCU to be high After t1, PL input is pulse LOW. Refer to MODE table, PL low gives output of counter loading up the input P3 P0, then the output Q becomes 1011 At t1, the CPU input makes a PGT, but the counter cannot response to this because PL is still active at that time
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Cont.
At time t2, t3, t4 and t5 the counter counts up on each PGT at CPU After t5, the counter is in 1111 state but TCU does not go low until CPU goes low at t6 The counter reset to 0000
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Exercise
Draw the output waveform of the following counter
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1. 2.
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5.
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1. Determined the desired number of bits (FFs) and the desired counting sequence.
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