Chapter 8: Sequential Circuit ATPG

8.1 Race condition

The signals are sketched in the timing diagram below. We assume ideal logic signals that change at times 0, 1, 2, etc.: time = 0, D falls and CK rises. time = 1, outputs of NOT gate and the bottom OR gate rise.

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ap Neither the state of the master latch nor that of the slave latch is aected by the h change in D. To be stored correctly in the ip-op, the data input (D) should c n/ change earlier than the rising edge of CK by an interval known as the setup time. Also, the data should remain unchanged beyond the rising edge of CK for a duration io known as the hold time. ut ol /s si vl e/ st we s/ or th au g/ for the master latch to acquire a steady state after the D Setup time is the time en input changes while the clock is in the active state (0 for the ip-op of Figure 8.2 in the book.) cs Hold time is the delay of the clock control gates (OR gates in the ip-op of m/ It is the interval that the clock takes to isolate the storing gates (two Figure 8.2.) co NAND gates) of the master latch from the data input. l. In the above case, data and clock changed simultaneously and the ip-op aw recorded the wrong (old) data. We illustrate a peculiar behavior of the latch when .
time 1, all signals retain their values without any further change.
D CK NOT gate top OR gate data must not change bottom OR gate top NAND gate D CK master latch open master latch closed bottom NAND gate Q Q setup time hold time time 0 1

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data and clock changes occur close to each other. As shown in the next gure, suppose the N OT gate has a delay of two units and all other gates have one unit of delay. Suppose CK rises one unit after the fall of D. This produces simultaneous 0 1 transitions at the outputs of the two OR gates. The two equal delay NAND gates now oscillate between 00 and 11 states.

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CK D NOT OR1 OR2 NAND1 NAND2 CK D NOT delay 2 OR2 1 1 NAND2 OR1 1

NAND1 1

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ap The oscillations we observe in this example do not actually occur. Any unbalance h in the delays of the NAND gates will stabilize the state of the latch to either 01 or 10 c state. Such delay-dependent behavior is commonly known as the race condition or n/ metastability. In our example, a race is possible if the separation between the o i clock and data transitions is less than the delay of NOT gate. In general, a race t condition or metastability is avoided if the setup and hold time restrictions arelu satised. o /s 8.2 i It requires just one vector to initialize the circuit. If the s initial state is unknown, vl i.e., C = X, the vector A = B = 1 initializes the state to 1, irrespective of the presence of any fault at the output S . Given this / state, detection of any output te fault at the output reduces to a combinational ATPG problem of setting the output s to the opposite value. This can be done bye single vector: (A = 0, B = 0) will a 1) will set it to 0. Thus, just two vectors, set the output to 1 or (A = 0, B = /w s an initialization vector 11 followed by an appropriate vector to set the output, will detect the output fault in the circuit of Figure 8.3 (see page 215 of the book.) or th 8.3 au / Considering the combinational logic of the circuit we nd that for sensitizing a path gwe must specify the other PI as well as the present state, C . from a PI to PO, S , en be rst initialized. Any input fault in the circuit of Figure 8.3 Thus, the circuit must cs (see page 215 of the book) can be tested as follows: / Vectorm (Initialization.) If the fault is s-a-1 type, then vector 11 is used to 1 co . initialize the00circuits (both good andtofaulty) to 1. If the fault is s-a-0 type, wl then vector initializes the circuits 0. .a Vcetor 2 (Fault activation and path sensitization.) For a s-a-1 fault, the cirn n n n n n n n n n

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cuit has been initialized to a 1 state. A 0 is applied to the faulty line, activating the fault as 0/1. Application of 1 to the other input propagates a value 0/1 to the output Sn . For a s-a-0 fault, the circuit is initialized to a 0 state. An input vector 11 now activates the fault and also propagates its eect to Sn .

Thus, only two vectors are needed to test any input fault.
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8.4
The required test has two steps: 1. Fault activation. Assuming the present state to be unknown, we set the next state to 1. For Cn = X, backward justication of Cn+1 = 1 in Figure 8.3 (see page 215 of the book) gives us An = 1 and Bn = 1. 2. Path sensitization. For the next vector, the above next state becomes the present state and the fault Cn s-a-0 is sensitized. We sensitize a path from Cn to Sn by setting An = 1 and Bn = 1. Thus, the test sequence is (An , Bn ) = (1,1), (1,1).

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on For test generation with the ve-valued algebra, we use the following steps (also see ti the illustration): lu Step 1: Place a D at the output B in time-frame 0. so Step 2: This can only be justied by either DD or D1 input to the AND gate in i/ time-frame 0. DD is not possible due to the state input being X in the timels that a state 1 can be frame -1. We place D1 by applying A = 1 and assuming /v justied. te Step 3: Any input, 0 or 1, as shown in thees gure, produces a state output X from time-frame 1. Thus, the faulty circuit cannot be initialized to any known w state, including the 1 needed for the test. Hence, it is impossible to nd s/ a test by the 5-valued algebra. or th au g/ en cs m/ co l. aw p. Following similar steps with the nine-valued algebra (see illustration below), we
8.5
A A 0 or 1 s-a-0 1 s-a-0 0 or D D X X 1 0 or X D B B Time-frame -1 Time-frame 0 Test generation attempted with 5-valued algebra.

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nd that two 1s at A detect the fault at B as 1/0 in time-frame 0. Notice that the fault is detected although the faulty circuit is never initialized.

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A 1 1/0 X s-a-0 1/X 1 1/0 1/X

A s-a-0 1/X

X/0 B Time-frame -1

1/0 B Time-frame 0

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ap 8.6 Initialization fault ch The following gure illustrates the time-frame expansion procedure of generating n/ a vector, A = 0, B = 1, which starting from the unknown state detects theo fault A s-a-1 as 1/X. After the application of the input vector, the ip-op ti is clocked before the output can be observed. Even if we add more vectors to the test sequence, luthe faulty the faulty circuit output will not become deterministic. This is because so circuit is not initializable. The fault is only potentially detectable. i/ ls /v te es /w rs ho ut /a ng se /c om .c wl .a Note: Some test generators will nd the potential detection test of the above
Test generation with 9-valued algebra.

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A=B=X

sa1

0/1

1/0

0/X

1/0

Timeframe 1 C

Timeframe 0 C

1/X

0,0/1,0

1,0,0/1

0,0,X

0,0/1,0

0,0,X

0/1,0,0/1

sa1 0/1,0/1,X/1 1/0,1/0,X/0

1/0,1,X/0

FF 1,1/0,1

sa1 0/1,0/1,X/1 1/0,1/0,X/0

1,1/0,X/1

FF 0,1,1/0

1,1,X

1/0,1/0,X/0

1,1,X

1/0,1/0,X/0

Test simulation with initial state 1.

Test simulation with initial state 0.

type. Others will consider the fault untestable (conservative approach.) Most fault simulators will nd the fault potentially detectable. Interestingly, the two test simulation scenarios in the gure show that the fault is denitely detectable, though the detection requires multiple observations. If we assume the initial state to be 1 then the fault is detected as 1/0 after the application of the rst clock. However, this
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output will be 1 (same as the correct output) if the initial state was 0. In this case, repeating the same vector and clocking once again will produce a 1/0 output. A conventional fault simulator will not report such detection because it does not enumerate the possible initial state scenarios. For such multiple observation tests see reference [525] of the book.

8.7
The note in the solution of Problem 8.6 explains the operation of a multiple observation test. Besides simulation, a multiple observation test can also be derived by the following procedure. An observable state variable, which cannot be initialized in the faulty circuit but must be observed for fault detection, is represented symbolically by a Boolean variable s. Inversion of s is s. A test sequence is derived such that any one of the following pairs of outputs is produced: 0/s and 0/s 1/s and 1/s 0/s and 1/s 0/s and 1/s

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vl e/ state variable assumes, We notice that irrespective of the value the uninitialized st one element in each test output pair will provide denite fault detection. For exame ple, the outputs produced by the test (A,w = (0,1), (0,1) of Problem 8.6 are 1/s B) and 1/s, respectively, which agree with / second pair given above. the When the feedback in the circuit of Figure 8.25 (see page 250 of the book) has rs no inversion, a test sequence (A, B) = (0,0), (0,1) will produce outputs 0/s and 1/s. ho Details on multiple observation tests may be This is a multiple observation test. ut found in reference [525] cited in the book. /a ng 8.8 se The following gure shows the combinational 0 and 1 controllabilities as (CC0, CC1). /c Notice that the output measures for a ip-ops are obtained by just adding 1 to the input measures. This is due to assumptions that the clock has controllabilities om c (1,1) and the combinational depth of a ip-op is 0. The fault site can be driven .1/0 by controlling B = 1 and it cannot be driven to 0/1. Thus, its drivabilities to wl d(0/1) = and d(1/0) = 1, respectively. Drivabilities of all other signals are are .a successively computed by simple path sensitization.
The path shown in bold lines is the least drivability (minimum eort) path. A test obtained by a drivability-based ATPG procedure is shown in the lower gure. This three-vector test, (A, B) = (1, 1), (1, 1), (1, X), sensitizes the minimum drivability path and we nd that another path, shown by dotted lines, must also be sensitized.
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(CC0,CC1) d(0/1)= d(1/0)= 8 8

(2,2)

d(0/1)= d(1/0)=

(1,1) A sa0 B (1,1) d(0/1)= d(1/0)=1

C (2,2) F1 d(0/1)= d(1/0)=101 8

(4,2) 8

(5,3) F2 d(0/1)= d(1/0)=203 8 E d(0/1)=105 d(1/0)= 8 F3 (6,3)

8 8

Z (16,3) d(0/1)=115 d(1/0)= 8

d(0/1)= d(1/0)=103

(7,4) d(0/1)=205 d1/0)= 8

Drivabilities for fault B sa0 in circuit of Figure 8.9. Bold lines show easiest drivability path. D 1,1,1 A sa0 B 1,1,X F1 X,1/0,1/0 C 0,0,0

1,1,1 F2

X,1,1

X,X/1,0/1 E X,0/1,0/1 F3

X,X,0/1

A threevector test for fault B sa0. Dotted lines show an additional path sensitized.

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vl e/ st X CLR we 0/1 Z sa0. s/ 0/1 0/1 1 A 0/X or 0 NS PS 1 h 0 0/1 1/0 ut /a Combinational test for A sa0. ng To justify P S = 1 in this test, we generate an input vector for the combinational circuit that will produce N S = 1 output. We nd a vector, CLR = 0, A = se 1, P S = 0. In order to apply the required approximation, we assume no fault /c The justication must continue until we can nd a vector with during justication. m P S co = X. P S = 0 is easily justied by an input, CLR = 1, A = X, P S = X. Thus, the test P S) = (0, 1, 0), l. 1, 1), whichsequence contains three vectors, (CLR, A,that the (1, X, X),to detect (X, is simulated in the next gure. We nd test fails aw the fault. In the last time-frame, where the combinational vector is applied, the .
8.9 Approximate test
A combinational test for the fault A s-a-0, as shown in the following gure, is CLR = X, A = 1, P S = 1. The fault is detected at Z as 0/1. P S input is 1/0 instead of 1. This is due to the fault being present in the previous time-frame. Thus the faulty previous state interferes with the newly generated fault eect and the output Z becomes 0 instead of 0/1. A valid test is generated by time-frame expansion when the fault is assumed to be present in all time-frames (as we did for simulation in the above gure.) The new

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X A X PS sa0

1 CLR PS

1 A sa0

0 CLR PS

1 A sa0

X CLR

1/0 0/1

1/0 0/1

1/0

1/0

1 1/0

0 NS Z X NS

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so time-frame test, as shown in the following gure, has only one change. In/ last i the A is changed to 0. So, no new fault eect is produced there and the fault eect 1/0 ls produced in time-frame -1 is propagated to Z. /v te es /w rs ho ut /a ng se /c om .c wl .a The test sequence is (CLR, A, P S) = (1, X, X), (0, 1, 0), (X, 0, 1/0). p
Timeframe 2 X PS X A 1 CLR Timeframe 1 PS 1 0 A CLR Timeframe 0 PS 0 A X CLR sa0 sa0 sa0 1/0 0 0/1 1 1 1/0 0 0 1/0 1/0 1 1/0 X NS Z X 1/0 NS Z 0 Correct test generation by timeframe expansion method. NS 0 X/0 Z 1/0

NS Z 0 Z 0 Simulation of approximate test sequence shows it to be be invalid.

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8.10
A necessary condition for detection of a fault in a sequential circuit is that there must exist at least one time-frame in which, 1. the fault is activated, and 2. the fault eect is propagated to the boundary of the combinational logic, i.e., to one or more PO and/or one or more state variables. Since the fault is combinationally untestable it is impossible to satisfy these conditions even though the state inputs are assumed to be fully controllable. Thus, no vector sequence can be generated to test the fault in the sequential circuit.

8.11

Consider the time-frame expansion method of sequential circuit ATPG. A timeframe consists of combinational logic with some fault activity (fault activation and path sensitization.) In general, this activity must be justied at the PIs of the timeframe by three-valued (0, 1 and X) logic and at the state inputs by nine-valued (0, 1, 0/1, 0/X, . . etc.) logic. There are two types of time-frames, ones in which the fault is activated, and others where the fault is not activated. Let us consider the time-frame in which the fault is activated for the rst time. To be a part of the test sequence, this time-frame must propagate the fault eect either to a PO or to a state variable. We call this the rst detection time-frame. Clearly, such a time-frame is necessary for fault detection. In the rst detection time-frame a combinational test detects the fault at its boundary (PO or state output) when a suitable test vector at PI and state inputs is applied. All preceding time-frames then only generate fault-free states leading to a state input that is necessary for the rst detection time-frame. If the combinational test cannot be justied then the rst detection time-frame will be impossible and no sequential test can be obtained for the targeted fault. A more detailed discussion of this result may be found in the reference [30] cited in the book.

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.c Pseudo-combinational test The circuit and a combinational test, = wl pseudo-combinational the following gure. Simulation ofAthe 0, B = 1, for the sequential circuit .a fault D s-a-0 are shown in
8.12
with input A = 0, B = 1, repeated four times shows that the fault will be detected as 1/0 appearing as the fourth output. We assume that the initial states of all three ip-ops are X.

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D 0 1

sa0

1/0

A B

1/0

E 1

Pseudocombinational circuit for the sequential circuit of Figure 8.9..

D 0,0,0,0 1,1,1,1 F1 X,1,1,1 C

sa0 1/0,1/0,1/0,1/0 Z 1/X,1/X,1/X,1/0 E X,X,0,0 F3 X,X,X,0

A B

X,1,1,1 F2

X,X,1,1

Test simulation in sequential circuit.

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so / A pseudo-combinational circuit is obtained by shorting all i ip-ops in an acyclic synchronous sequential circuit. We will prove that a test vector for the former, ls latter, where d is when repeated d + 1 times, will be a test sequencev the / for called the sequential depth and is the maximum number of ip-ops in any input te to output path. Our proof is based on a series of observations: es Observation 1: A clocked ip-op is equivalent to a delay that equals the clock /w period, T . rs Observation 2: The output of o combinational circuit with arbitrary delays is a uniquely determined by h input vector provided (a) output is allowed to the stabilize through a time interval, which equals the longest input to output ut combinational path delay after the input is applied, and (b) the input is held /a that time interval. constant throughout ng e Observation s A combinational circuit with a single stuck-at fault (and many 3: other non-feedback types of faults) is also a combinational circuit. /c Observations 1 and 2 specify that the basic dierence between an acyclic seom quential circuit and its pseudo-combinational circuit is the delay. The delay of the .c has an upper bound, (d + 1)T , where T is the clock period. The delay of former wl latter equals that of the longest combinational path in that circuit. Note that the .a T is greater than the longest combinational path delay. p
8.13
seq seq seq

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The given test vector produces two dierent outputs from the good and faulty pseudo-combinational circuits. If the conditions of Observation 1 are satised, then the good and faulty acyclic sequential circuits will produce outputs that will dier in a similar way. This is done by holding the vector at the input for an interval (dseq + 1)T and clocking the circuit dseq times.
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8.14
A circuit is initializable means, given that all ip-ops are in unknown (X) states, there exists a nite-length input sequence that will bring all ip-ops to known states. Initializability is often considered in a narrower (and practical) sense to mean that the nite-length sequence, when simulated by a three-valued logic simulator, will set all ip-ops in deterministic (0 or 1) states. The required proof follows from contradiction. We begin with an assertion that an uninitializable circuit is cycle-free. Then its s-graph is a directed acyclic graph (DAG), which can be levelized according to the maximum distance from PIs. Levels of ip-op vertices must be contiguous integers from 1 to dseq , the sequential depth. All ip-ops in level 1 are controlled by PIs and can be set to some (may not be every) known states by one input vector followed by a clock. Similarly, all ip-ops in level 2 are controlled by PIs and the ip-ops of level 1 (which are now in known states) and these can be set to known states by a second input vector followed by another clock. Following this procedure, by the time dseq input vectors have been applied, each followed by a clock, all ip-ops will be in known states. Since, dseq for a DAG is a nite integer, the circuit is initialized by a nite length input sequence. This contradicts our assertion. Hence, the circuit cannot be cycle-free and must be cyclic.

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vl e/ below. The levels shown Modied s-graphs with PI and PO vertices are shown t give the minimum distance from PIs. The es depths of the two circuits are 1 and 2, respectively. This depth gives a lower bound on the length of a test sequence for a /w is almost always longer than this lower fault. In practice, however, a test sequence rs bound. The maximum distance levelization and the corresponding depth is a more realistic measure of the test length for a cycle-free circuit. For cyclic circuits no ho t tight measure of test length exists. For an upper bound of 9 on length, uip-ops in the circuit, see Section 8.2.5the test book. a of the where N is the number of g/ Level=0 Level=0 Level=1 en Level=1 s F2 Z A Level=1 Level=2 /c om F1 B F3 Level=1 .c Level=2 Level=0 wl Level=0 Level=1 of Figure 8.9. Cyclefree circuit Cyclic circuit of Figure 8.13. .a Minimum distance levelization of sgraphs.
8.15 Cyclic circuits
Nf f ff
CNT FF1 FF2 Z CLR

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8.16

Race fault in asynchronous circuit

A procedure to test the s-a-1 fault at the output of the NOT gate in the circuit of Figure 8.27 is outlined below: 1. We inject the values of A and A into the feedback loop consisting of the two NOR gates by applying B = 1. A = 1 is applied to activate the fault. We assume that the two NOR gates have equal delays and simulate their outputs independently, with the feedback inputs in the unknown (X) state. This is illustrated in time-frame 1 in the following gure.

2. The outputs of NOR gates are applied after the feedback delays in time-frame 2. We nd that the outputs, 1/0 and 1, are stable since another time-frame will not change them.
B 1 0/1 sa1 A 1 B 1 0/1 sa1 A 1 B 0 0/1 sa1 1 A B 0 0/1 sa1 1 A

0/1 X X X

0/1 1 0

X/0

0 1 0

X/0 0 Q Timeframe 1

1/0 0 Q Timeframe 2

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.c wl Note: Some ATPG programs will consider this fault to be untestable. Strictly .a speaking, the logic model does not have the information to nd tests for such faults,

3. Next we apply B = 0 to activate the loop. Time-frames 3 through 5 show that in the good circuit the Q output stabilizes to state 0 and the output of the other NOR gate stabilizes to 1. In the faulty circuit, the outputs of the two NOR gates oscillate as 11, 00, 11, . . . This oscillation in the idealized logic model is a manifestation of a metastable behavior. The output Q may settle to a 1 or to a 0 state depending upon the relative delays of the two NOR gates. In the absence of more detailed knowledge of circuit parameters (delays, etc.) we consider the fault to be potentially detectable.

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1 0/1 Q Timeframe 3

1/0 0

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0/1

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1/0

1 0/1 Q Timeframe 5

Timeframe 4

which are often classied as race faults. The race refers to an unstable equilibrium in which two possible states compete, each trying to win by getting through the feedback path rst. When dealing with the analog behavior of the circuit, this condition is referred to as metastability. For some set of gate delays the circuit will settle in the correct state and the fault would be considered redundant. For other delays the
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output will settle in the wrong state and the circuit, which is then indeed faulty, will be found to be so by the test.

8.17

Oscillation fault

Let us denote the output of NAND gate as Y . The following gure shows test generation using nine-value logic. First, we initialize Z = 0 and Y = 1 by setting A = 0. C is then set to 0 to activate the fault as 0/1. To propagate the faulty state to Y , Z is set to 1 by applying A = B = 1. This makes Y = 1/0, and this value propagates to the output Z. However, now the two inputs of the NAND gate become 0/1 and 1/0, respectively, causing Y = 1. Thus, the output Z continues to change as 1/0 1 1/0 1 . . . . This means that the fault-free circuit will produce a constant 1 output, while the faulty circuit output will uctuate between 1 and 0. The period of uctuation will equal the combined delay of the path including the four gates. The test has two steps: (1) Initialization, A = 0; (2) Combinational test, A = B = 1, C = 0.
A B 0>1 1 1>1/0>1>1/0 ....

0>1>1/0>1>1/0 ....

1>1/0>1>1/0 ....

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om .c wl .a
8.18

We evaluate the fault-free function of the circuit as Z = ABY + AC. Further, Y = CZ = AC. Substituting this, we nd Z = ABC + AC = A(B + C). The function and its two gate combinational (feedback-free) implementation are shown in the gure.

cs /

B (b) Boolean minimization.

ng e

vl Y e/ st (a) Test generation with ninevalue logic. we s/ A or A 1 th B 1u 1 C /a

sa1 0/1 Solution of Problem 8.17

1>1/0>1>1/0 ....

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(c) Feedbackfree combinational circuit.

Simulation-based initialization

The initialization sequence for the circuit of Figure 8.9 (see page 226 of the book) is, (A, B) = (0,0), (1,0). The procedure is illustrated in the following table where the selected vectors are shown in boldface.

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Phase I

Simulation-based initialization of circuit of Figure 8.9 Types of vectors Trial vectors States Cost Remarks A B F 1 F 2 F 3 func. Initial condition X X X X X 3 Cost=#FFs Starting vector 0 0 0 X X 2 Cost red. Unit Hamm. dist. 1 0 0 1 1 0 Cost red. Circuit initialized (cost=0), Phase I completed.

The initialization sequence for the circuit of Figure 8.13 (see page 230 of the book) is, (CN T, CLR)= (0,1). The procedure is illustrated in the following table where the selected vector is shown in boldface. Phase I Simulation-based initialization of circuit of Figure 8.13 Types of vectors Trial vectors States Cost Remarks CN T CLR F F 1 F F 2 func. Initial condition X X X X 2 Cost=#FFs Starting vector 0 0 X X 2 No cost red. Unit Hamm. dist. 1 0 X X 2 No cost red. 0 1 0 0 0 Cost red. Circuit initialized (cost=0), Phase I completed.

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vl because neither CN T = This procedure cannot initialize the circuit in Figure 8.12, e/ These are the only pos0 nor CN T = 1 can force any ip-op into a dened state. st sible trial vectors. Thus, the initial cost of 2 will never be reduced. we 8.19 CONTEST s/ or The CONTEST procedure for the s-a-0 fault in Figure 8.3 is as follows: th au g/ en cs m/ co l. aw p.
Trial vectors An X 0 Output s Phase Type of vectors Cn X Bn X 0 C n+1 S n+1 X 0 X Cost function Remarks I Initial condition An arbitrary vector 1 Cost = number of uninitialized flip-flops. Phase I completed. Vector 00 accepted. X X 0 II Initialization vector X 0 0 0 0 0 0 X 1 1 Fault simulation of initialization vector; fault not activated. No cost reduction by any trial vector; vector 10 arbitrarily selected. 8 Unit Hamming distance vectors 0 1 0 0 8 1 0 0 8 Unit Hamming distance vectors 0 0 1 0 8 0 1 1 1/0 0 Fault detected; vector 11 selected.

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The test sequence is (An , Bn ) = (00), (10), (11). The selected vectors are shown in boxes in the table.
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8.20

CONTEST

Four steps that lead to the detection of the given s-a-0 faults are illustrated below. For simulation, as a vector is applied to PIs A and B, the next state Cn+1 value is transferred to the present state input Cn . Step 1: Initialization vector 00 is simulated with Cn = X. The signal values, dynamic controllabilities, DC0 and DC1, and propagation cost P C are shown in the following circuit diagram. P C is always 0 for the PO Sn .
DC0=0 DC1=1 PC=101 0 PC=101 PC=100 PC=100 PC=101 DC0=0 DC1=2 PC=100 0 DC0=0 DC1=1 PC=100 0 DC0=0 DC1=1 PC=100 0 PC=2 PC=100 PC=0 PC=100 DC0=0 DC1=103 PC=1 0 DC1=1 DC0=100 PC=0 X

A n

PC=101 sa0

PC=103

PC=1

DC0=100 DC1=1 PC=0 X

Bn

DC0=0 DC1=1 PC=100

PC=100

C n

X DC0=100 DC1=102 PC=0

p: t

/f /

tp

vl Activation cost (AC) equals DC1 at the fault site since the fault is of s-a-0 e/ type. We use a weighting factor of 1,000 that multiplies AC. Thus, the fault st detection cost for vector 00 is, we AC + P C Cost(00) = / s 1000 r= 1000 2 + 101 = 2101 ho 10 is simulated using the initial state C = 0 Step 2: Unit Hamming distance vector ut obtained in Step 1.a measures and costs are computed, as shown below, All g/ en cs m/ co l. aw .
FF

so i/ s

ut l
C

n+1

on i

Sn

ap ch /

er t

.p 8

DC0=0 DC1=2 PC=100

A n

DC0=1 DC1=0 PC=0

PC=1

PC=0

PC=0

Bn

DC0=0 DC1=1 PC=0 0 DC0=1 DC1=0 PC=0 1

PC=0

DC0=2 DC1=0 PC=0 1

PC=101 PC=0 PC=0

sa0

DC0=0 DC1=101 PC=0 0

PC=0

DC0=2 DC1=0 PC=0

PC=1

DC0=0 DC1=1 PC=0

PC=2

DC1=1 DC0=0 PC=0 1

Sn

PC=100

C n

PC=100

n+1

DC0=0 DC1=101 PC=0

DC0=0 DC1=1 PC=100

FF

Cost(10) = 1000 1 + 0 = 1000

Solution Manual V1.4 c M. L. Bushnell and V. D. Agrawal For Teachers only Page 77

Step 3: Another unit Hamming distance vector 01 is simulated using the initial state of Step 1 and measures and costs are computed, as shown below,
DC0=1 DC1=0 PC=0 0 PC=1 1 DC0=0 DC1=1 PC=0 PC=1 PC=0 PC=0 DC0=0 DC1=1 PC=0 0 DC0=1 DC1=0 PC=0 1 DC0=2 DC1=0 PC=0 1 PC=0 PC=0 PC=2 PC=100

A n

PC=0 sa0

PC=101

DC0=0 DC1=101 PC=0 0 DC1=1 DC0=0 PC=0 1

PC=0

DC0=2 DC1=0 PC=0 1

Sn

Bn

PC=100 0

C n

0 DC0=0 DC1=101 PC=0

n+1

DC0=0 DC1=1 PC=100

FF

Cost(01) = 1000 1 + 0 = 1000

Since the cost of both trial vectors is the same, we arbitrarily select the rst vector, 10. Step 4: Now, 10 becomes the current vector. It produces a next state Cn+1 = 0. We try a unit Hamming distance vector 11 as shown below,
DC0=1 DC1=0 PC=0 1 PC=0 1 DC0=1 DC1=0 PC=2 PC=2 PC=2 PC=0 DC0=1 DC1=0 PC=0 1 DC0=2 DC1=0 PC=1 DC0=0 DC1=1 PC=0 0

A n

PC=0 sa0

Bn

C n

p: t

tp /f /

co Cost(11) = 1000 0 + 0 = 0 l. w A zero cost indicates that the fault is detected. Thus the complete test se.a
quence is (An , Bn ) = (0,0), (1,0), (1,1).

/c m

en s
0

DC0=0 DC1=100 PC=0

/a g

ut

vl e/ st we s/ or h
PC=100 PC=1 DC0=0 DC1=1 PC=0 0 PC=0 PC=0 DC1=0 DC0=1 PC=0 0

so i/ s

ut l

on i

ap ch /

er t

.p 8

PC=1

DC0=0 DC1=1 PC=0 1

Sn

PC=101 1

PC=100

n+1

DC0=2 DC1=0 PC=100

FF

Solution Manual V1.4 c M. L. Bushnell and V. D. Agrawal For Teachers only

Page 78