Seminar Books

CRMC prequesites
My seminar
PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Fri, 17 Feb 2012 15:06:31 UTC
Contents
Articles
Pulse-density modulation Delta-sigma modulation Current mirror Pulse-width modulation Smart transducer Translinear circuit 1 4 16 24 31 31
References
Article Sources and Contributors Image Sources, Licenses and Contributors 35 36
Article Licenses
License 37
Pulse-density modulation
Pulse-density modulation, or PDM, is a form of modulation used to represent an analog signal with digital data. In a PDM signal, specific amplitude values are not encoded into pulses of different size as they would be in PCM. Instead, it is the relative density of the pulses that corresponds to the analog signal's amplitude. Pulse-width modulation (PWM) is the special case of PDM where all the pulses corresponding to one sample are contiguous in the digital signal.
Description
In a pulse-density modulation bitstream a 1 corresponds to a pulse of positive polarity (+A) and a 0 corresponds to a pulse of negative polarity (-A). Mathematically, this can be represented as:
where x[n] is the bipolar bitstream (either -A or +A) and a[n] is the corresponding binary bitstream (either 0 or 1). A run consisting of all 1s would correspond to the maximum (positive) amplitude value, all 0s would correspond to the minimum (negative) amplitude value, and alternating 1s and 0s would correspond to a zero amplitude value. The continuous amplitude waveform is recovered by low-pass filtering the bipolar PDM bitstream.
Examples
A single period of the trigonometric sine function, sampled 100 times and represented as a PDM bitstream, is: 0101011011110111111111111111111111011111101101101010100100100000010000000000000000000001000010010101
An example of PDM of 100 samples of one period a sine wave. 1s represented by blue, 0s represented by white, overlaid with the sine wave.
Two periods of a higher frequency sine wave would appear as: 0101101111111111111101101010010000000000000100010011011101111111111111011010100100000000000000100101
or In pulse-density modulation, a high density of 1s occurs at the peaks of the sine wave, while a low density of 1s occurs at the troughs of the sine wave.
Analog-to-digital conversion
A PDM bitstream is encoded from an analog signal through the process of delta-sigma modulation. This process uses a one bit quantizer that produces either a 1 or 0 depending on the amplitude of the analog signal. A 1 or 0 corresponds to a signal that is all the way up or all the way down, respectively. Because in the real world analog signals are rarely all the way in one direction there is a quantization error, the difference between the 1 or 0 and the actual amplitude it represents. This error is fed back negatively in the process loop. In this way every error successively influences every other quantization measurement and its error. This has the effect of averaging out the quantization error.
Digital-to-analog conversion
The process of decoding a PDM signal into an analog one is simple: one only has to pass the PDM signal through a low-pass filter. This works because the function of a low-pass filter is essentially to average the signal. The average amplitude of pulses is measured by the density of those pulses over time, thus a low pass filter is the only step required in the decoding process.
Relationship to biology
Notably, one of the ways animal nervous systems represent sensory and other information is through rate coding whereby the magnitude of the signal is related to the rate of firing of the sensory neuron. In direct analogy, each neural event - called an action potential - represents one bit (pulse), with the rate of firing of the neuron representing the pulse density.
Algorithm
A digital model of pulse-density modulation can be obtained from a digital model of the delta-sigma modulator. Consider a signal in the discrete time domain as the input to a first-order delta-sigma modulator, with the output. In the discrete frequency domain, the delta-sigma modulator's operation is represented by
Rearranging terms, we obtain
Here, quantization
is
the of
frequency-domain the delta-sigma represents at low frequencies, and more at high frequencies. This demonstrates the noise
Pulse-density modulation of a sine wave using this algorithm.
error
modulator. The factor contributes less to the output
a high-pass filter, so it is clear that shaping effect of the delta-sigma modulator: the quantization noise is "pushed" out of the low frequencies up into the high-frequency range. Using the inverse Z-transform, we may convert this into a difference equation relating the input of the delta-sigma modulator to its output in the discrete time domain,
There are two additional constraints to consider: first, at each step the output sample minimize the "running" quantization error only two values. We choose . Second, for convenience, allowing us to write
is chosen so as to
is represented as a single bit, meaning it can take on
This, finally, gives a formula for the output sample
in terms of the input sample
. The quantization error
of each sample is fed back into the input for the following sample.
Pulse-density modulation The following pseudo-code implements this algorithm to convert a pulse-code modulation signal into a PDM signal: // Encode samples into pulse-density modulation // using a first-order sigma-delta modulator function pdm(real[0..s] x) var int[0..s] y var real[-1..s] qe qe[-1] := 0 // initial running error is zero
for n from 0 to s if x[n] >= qe[n-1] y[n] := 1 else y[n] := -1 qe[n] := y[n] - x[n] + qe[n-1] return y, qe // return output and running error
Applications
PDM is the encoding used in Sony's Super Audio CD (SACD) format, under the name Direct Stream Digital.
External links
1-bit A/D and D/A Converters [1] Discusses delta modulation, PDM (also known as Sigma-delta modulation or SDM), and relationships to Pulse-code modulation (PCM)
References
[1] http:/ / www. cs. tut. fi/ sgn/ arg/ rosti/ 1-bit/
Delta-sigma modulation
Delta-sigma (; or sigma-delta, ) modulation is a method for encoding high-resolution or analog signals into lower-resolution digital signals. The conversion is done using error feedback, where the difference between the two signals is measured and used to improve the conversion. The low-resolution signal typically changes more quickly than the high-resolution signal and it can be filtered to recover the high-resolution signal with little or no loss of fidelity. This technique has found increasing use in modern electronic components such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), frequency synthesizers, switched-mode power supplies and motor controllers. A very popular application of delta-sigma conversion is in audio applications where a digital audio signal, as from an MP3 player, is converted into the analog audio signal which will be amplified and output by speakers or headphones. Because most of the modulator is a digital circuit, it is cheap to construct. Since the output of this modulator typically has only two levels, the generation of the analog output signal is power efficient. Further, because the modulator's output signal changes much faster than the desired audio signal, it can be heavily filtered and the resulting analog signal has high enough fidelity for use in professional applications. Low cost, low power, and high fidelity make delta-sigma modulators very popular.
Motivation
Why convert an analog signal into a stream of pulses?
In brief, because it is very easy to regenerate pulses at the receiver into the ideal form transmitted. The only part of the transmitted waveform required at the receiver is the time at which the pulse occurred. Given the timing information the transmitted waveform can be reconstructed electronically with great precision. In contrast, without conversion to a pulse stream but simply transmitting the analog signal directly, all noise in the system is added to the analog signal, reducing its quality. Each pulse is made up of a step up followed after a short interval by a step down. It is possible, even in the presence of electronic noise, to recover the timing of these steps and from that regenerate the transmitted pulse stream almost noiselessly. Then the accuracy of the transmission process reduces to the accuracy with which the transmitted pulse stream represents the input waveform.
Why delta-sigma modulation?

Delta-sigma modulation converts the analog voltage into a pulse frequency and is alternatively known as Pulse Density modulation or Pulse Frequency modulation. In general, frequency may vary smoothly in infinitesimal steps, as may voltage, and both may serve as an analog of an infinitesimally varying physical variable such as acoustic pressure, light intensity, etc. The substitution of frequency for voltage is thus entirely natural and carries in its train the transmission advantages of a pulse stream. The different names for the modulation method are the result of pulse frequency modulation by different electronic implementations, which all produce similar transmitted waveforms.
Why use delta-sigma modulation on a CD?

Delta-sigma modulation is unrelated to the physical encoding of a CD, DVD, or SACD. Digital data is physically represented as a transition (or not) between a light and dark reflection of the laser by the disc. The brightness of the reflected signal is converted using an analog to digital converter; the required rates of conversion make a delta-sigma ADC unsuitable. Once the physical data is recovered from the disc, the logical data is recovered using a number of steps, including error corrective coding. Audio data on a CD is logically encoded using PCM and so can easily be converted into an audible analog signal using a variety of conversion methods, delta-sigma included.
Why the delta-sigma analog to digital conversion?

The ADC converts the mean of an analog voltage into the mean of an analog pulse frequency and counts the pulses in an known interval so that the pulse count divided by the interval gives an accurate digital representation of the mean analog voltage during the interval. This interval can be chosen to give any desired resolution or accuracy and the method is cheaply produced by modern methods. Thus it is popular and widely used. is the mathematical symbol for the summation of delta pulses and is read sigma-delta.
Analog to digital conversion

Description
The analog to digital converter, ADC, generates a pulse stream in which the frequency of pulses in the stream is proportional to the analog voltage input, , so that the frequency, where k is a constant for the particular implementation. A counter sums the number of pulses that occur in a predetermined period, P so that the sum, . is chosen so that a digital display of the count, Because , is a display of with a predetermined scaling factor. , and thus has a known integral may take any designed value it may be made large enough to give any desired resolution or accuracy. and duration , is
Each pulse of the pulse stream has a known, constant amplitude but variable separating interval. In a formal analysis an impulse such as integral
is treated as the Dirac (delta) function and is specified by the .
step produced on integration. Here we indicate that step as
The interval between pulses, p, is determined by a feedback loop arranged so that
. , which
The action of the feedback loop is to monitor the integral of v and when that integral has incremented by is indicated by the integral waveform crossing a threshold, then subtracting combined waveform sawtooths between the threshold and ( threshold pulse stream. Between impulses the slope of the integral is proportional to
from the integral of v so that the
). At each step a pulse is added to the
. Whence
. It is the pulse stream which is transmitted for delta-sigma modulation but the pulses are counted to form sigma in the case of analogue to digital conversion.
Analysis
Shown below the block diagram illustrated in Fig. 1 are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts on the left and 0.4 volts on the right. In most practical applications the summing interval is large compared with the impulse duration and for signals which are a significant fraction of full scale the variable separating interval is also small compared with the summing interval. The NyquistShannon sampling theorem requires two samples to render a varying input signal. The samples appropriate to this criterion are two successive counts taken in two successive summing intervals. The summing interval, which must accommodate a large count in order to achieve adequate precision, is inevitably long so that the converter can only render relatively low frequencies. Hence it is convenient and fair to represent the input voltage (1) as constant over a few impulses. Consider first the waveforms on the left. 1 is the input and for this short interval is constant at 0.2V. The stream of delta impulses is shown at 2 and the difference between 1 and 2 is shown at 3. This difference is integrated to produce the waveform 4. The threshold detector generates a pulse 5 which starts as the waveform 4 crosses the threshold and is sustained until the waveform 4 falls below the threshold. Within the loop 5 triggers the impulse Fig.1a: Effect of clocking impulses generator and external to the loop increments the counter. The summing interval is a prefixed time and at its expiry the count is strobed into the buffer and the counter reset. It is necessary that the ratio between the impulse interval and the summing interval is equal to the maximum (full scale) count. It is then possible for the impulse duration and the summing interval to be defined by the same clock
Fig.1: Block diagram and waveforms for a sigma delta ADC.
Delta-sigma modulation with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined with absolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that the amplitude of the impulse be accurately defined. On the right the input is now 0.4V and the sum during the impulse is 0.6V as opposed to 0.8V on the left. Thus the negative slope during the impulse is lower on the right than on the left. Also the sum is 0.4V on the right during the interval as opposed to 0.2V on the left. Thus the positive slope outside the impulse is higher on the right than on the left. The resultant effect is that the integral (4) crosses the threshold more quickly on the right than on the left. A full analysis would show that in fact the interval between threshold crossings on the right is half that on the left. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left which is consistent with the input voltage being doubled. Construction of the waveforms illustrated at (4) is aided by concepts associated with the Dirac delta function in that all impulses of the same strength produce the same step when integrated, by definition. Then (4) is constructed using an intermediate step (6) in which each integrated impulse is represented by a step of the assigned strength which decays to zero at the rate determined by the input voltage. The effect of the finite duration of the impulse is constructed in (4) by drawing a line from the base of the impulse step at zero volts to intersect the decay line from (6) at the full duration of the impulse. As stated, Fig.1 is a simplified block diagram of the delta-sigma ADC in which the various functional elements have been separated out for individual treatment and which tries to be independent of any particular implementation. Many particular implementations seek to define the impulse duration and the summing interval from the same clock as discussed above but in such a way that the start of the impulse is delayed until the next occurrence of the appropriate clock pulse boundary. The effect of this delay is illustrated in Fig.1a for a sequence of impulses which occur at a nominal 2.5 clock intervals, firstly for impulses generated immediately the threshold is crossed as previously discussed and secondly for impulses delayed by the clock. The effect of the delay is firstly that the ramp continues until the onset of the impulse, secondly that the impulse produces a fixed amplitude step so that the integral retains the excess it acquired during the impulse delay and so the ramp restarts from a higher point and is now on the same locus as the unclocked integral. The effect is that, for this example, the undelayed impulses will occur at clock points 0, 2.5, 5, 7.5, 10, etc. and the clocked impulses will occur at 0, 3, 5, 8, 10, etc. The maximum error that can occur due to clocking is marginally less than one count. Although the Sigma-Delta converter is generally implemented using a common clock to define the impulse duration and the summing interval it is not absolutely necessary and an implementation in which the durations are independently defined avoids one source of noise, the noise generated by waiting for the next common clock boundary. Where noise is a primary consideration that overrides the need for absolute amplitude accuracy; e.g., in bandwidth limited signal transmission, separately defined intervals may be implemented.
Practical Implementation
A circuit diagram for a practical implementation is illustrated, Fig 1b and the associated waveforms Fig. 1c. A scrap view of an alternative front end is shown in Fig. 1b which has the advantage that the voltage at the switch terminals are relatively constant and close to 0.0V. Also the current generated through R by Vref is constant at Vref/R so that much less noise is radiated to adjacent parts of the circuit. Then this would be the preferred front end in practice but, in order to show the impulse as a voltage pulse so as to be consistent with previous discussion, the front end given here, which is an electrical equivalent, is used. From the top of Fig 1c the waveforms, labelled as they are on the circuit diagram, are:The clock. (a) Vin. This is shown as varying from 0.4V initially to 1.0V and then to zero volts to show the effect on the feedback loop. (b) The impulse waveform. It will be discovered how this acquires its form as we traverse the feedback loop. (c) The current into the capacitor, Ic, is the linear sum of the impulse voltage upon R and Vin upon R. To show this sum as a voltage the product R Ic is plotted. The input impedance of the amplifier is regarded as so high that the current drawn by the input is neglected. (d) The negated integral of Ic. This Fig.1c: ADC waveforms negation is standard for the op. amp. implementation of an integrator and comes about because the current into the capacitor at the amplifier input is the current out of the capacitor at the amplifier output and the voltage is the integral of the current divided by the capacitance of C.
Fig.1b: circuit diagram
Delta-sigma modulation (e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected for reference to 0.0V. Whenever the negative input terminal is taken negative with respect the positive terminal of the amplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturates positive whenever the integral (d) goes below the 0V reference level and remains there until (d) goes positive with respect to the reference level. (f) The impulse timer is a D type positive edge triggered flip flop. Input information applied at D is transferred to Q on the occurrence of the positive edge of the clock pulse. thus when the comparator output (e) is positive Q goes positive or remains positive at the next positive clock edge. Similarly, when (e) is negative Q goes negative at the next positive clock edge. Q controls the electronic switch to generate the current impulse into the integrator. Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4V, shows (e) crossing the threshold well before the trigger edge (positive edge of the clock pulse) so that there is an appreciable delay before the impulse starts. After the start of the impulse there is further delay while (e) climbs back past the threshold. During this time the comparator output remains high but goes low before the next trigger edge. At that next trigger edge the impulse timer goes low to follow the comparator. Thus the clock determines the duration of the impulse. For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is only briefly positive. Vin (a) goes to full scale, +Vref, shortly before the end of the next impulse. For the remainder of that impulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following this impulse the full scale positive current is flowing (c) and the integrator sinks at its maximum rate and so crosses the threshold well before the next trigger edge. At that edge the impulse starts and the Vin current is now matched by the reference current so that the net capacitor current (c) is zero. Then the integration now has zero slope and remains at the negative value it had at the start of the impulse. This has the effect that the impulse current remains switched on because Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent with contiguous, butting impulses which is required at full scale input. Eventually Vin (a) goes to zero which means that the current sum (c) goes fully negative and the integral ramps up. It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off. The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquired at the end of the impulse. (g) The countstream is generated by gating the negated clock with Q to produce this waveform. Thereafter the summing interval, sigma count and buffered count are produced using appropriate counters and registers. The Vin waveform is approximated by passing the countstream (g) into a low pass filter, however it suffers from the defect discussed in the context of Fig.1a. One possibility for reducing this error is to halve the feedback pulse length to half a clock period and double its amplitude by halving the impulse defining resistor thus producing an impulse of the same strength but one which never butts onto its adjacent impulses. Then there will be a threshold crossing for every impulse. In this arrangement a monostable flip flop triggered by the comparator at the threshold crossing will closely follow the threshold crossings and thus eliminate one source of error, both in the ADC and the sigma delta modulator.
Remarks
In this section we have mainly dealt with the analogue to digital converter as a stand alone function which achieves astonishing accuracy with what is now a very simple and cheap architecture. Initially the Delta-Sigma configuration was devised by INOSE et al. to solve problems in the accurate transmission of analog signals. In that application it was the pulse stream that was transmitted and the original analog signal recovered with a low pass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with . The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with to be replaced with the errors associated with the mean of means when discussing the ADC. For those uncomfortable with this assertion consider
Delta-sigma modulation this. It is well known that by Fourier analysis techniques the incoming waveform can be represented over the summing interval by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number of cycles over the sampling period. It is also well known that the integral of a sine wave or cosine wave over one or more full cycles is zero. Then the integral of the incoming waveform over the summing interval reduces to the integral of the constant and when that integral is divided by the summing interval it becomes the mean over that interval. The interval between pulses is proportional to the inverse of the mean of the input voltage during that interval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. Thus the average of the input voltage over the summing period is V/N and is the mean of means and so subject to little variance. Unfortunately the analysis for the transmitted pulse stream has, in many cases, been carried over, uncritically, to the ADC. It was indicated in section 2.2 Analysis that the effect of constraining a pulse to only occur on clock boundaries is to introduce noise, that generated by waiting for the next clock boundary. This will have its most deleterious effect on the high frequency components of a complex signal. Whilst the case has been made for clocking in the ADC environment, where it removes one source of error, namely the ratio between the impulse duration and the summing interval, it is deeply unclear what useful purpose clocking serves in a transmission environment since it is a source of both noise and complexity. A very accurate transmission system with constant sampling rate may be formed using the full arrangement shown here by transmitting the samples from the buffer protected with redundancy error correction. In this case there will be a trade off between bandwidth and N, the size of the buffer. The signal recovery system will require redundancy error checking, digital to analog conversion,and sample and hold circuitry. A possible further enhancement is to include some form of slope regeneration.This amounts to PCM (pulse code modulation) with digitization performed by a sigma-delta ADC. The above description shows why the impulse is called delta. The integral of an impulse is a step. A one bit DAC may be expected to produce a step and so must be a conflation of an impulse and an integration. The analysis which treats the impulse as the output of a 1-bit DAC hides the structure behind the name (sigma delta) and cause confusion and difficulty interpreting the name as an indication of function. This analysis is very widespread but is deprecated. A modern alternative method for generating voltage to frequency conversion is discussed in synchronous voltage to frequency converter (SVFC) which may be followed by a counter to produce a digital representation in a similar manner to that described above.[1]
10
Digital to analog conversion

Discussion
Delta-sigma modulators are often used in digital to analog converters (DACs). In general, a DAC converts a digital number representing some analog value into that analog value. For example, the analog voltage level into a speaker may be represented as a 20 bit digital number, and the DAC converts that number into the desired voltage. To actually drive a load (like a speaker) a DAC is usually connected to or integrated with an electronic amplifier. This can be done using a delta-sigma modulator in a Class D Amplifier. In this case, a multi-bit digital number is input to the delta-sigma modulator, which converts it into a faster sequence of 0's and 1's. These 0's and 1's are then converted into analog voltages. The conversion, usually with MOSFET drivers, is very efficient in terms of power because the drivers are usually either fully on or fully off, and in these states have low power loss.
Delta-sigma modulation The resulting two-level signal is now like the desired signal, but with higher frequency components to change the signal so that it only has two levels. These added frequency components arise from the quantization error of the delta-sigma modulator, but can be filtered away by a simple low-pass filter. The result is a reproduction of the original, desired analog signal from the digital values. The circuit itself is relatively inexpensive. The digital circuit is small, and the MOSFETs used for the power amplification are simple. This is in contrast to a multi-bit DAC which can have very stringent design conditions to precisely represent digital values with a large number of bits. The use of a delta-sigma modulator in the digital to analog conversion has enabled a cost-effective, low power, and high performance solution.
11
Relationship to -modulation
modulation (SDM) is inspired by modulation (DM), as shown in Fig.2. If quantization was homogeneous (e.g., if it was linear), the following would be a sufficient derivation of the equivalence of DM and SDM: 1. Start with a block diagram of a -modulator/demodulator. 2. The linearity property of integration ( ) makes it possible to move the integrator, which reconstructs the analog signal in the demodulator section, in front of the -modulator. 3. Again, the linearity property of the integration allows the two integrators to be combined and a -modulator/demodulator block diagram is obtained.
Fig.2: Derivation of - from -modulation
However, the quantizer is not homogeneous, and so this explanation is flawed. It's true that is inspired by -modulation, but the two are distinct in operation. From the first block diagram in Fig.2, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signal , the low-pass filter sees the signal
However, sigma-delta modulation of the same input signal places at the low-pass filter
In other words, SDM and DM swap the position of the integrator and quantizer. The net effect is a simpler implementation that has the added benefit of shaping the quantization noise away from signals of interest (i.e., signals of interest are low-pass filtered while quantization noise is high-pass filtered). This effect becomes more dramatic with increased oversampling, which allows for quantization noise to be somewhat programmable. On the other hand, -modulation shapes both noise and signal equally.
Delta-sigma modulation Additionally, the quantizer (e.g., comparator) used in DM has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in SDM must take values outside of the range of the input signal, as shown in Fig.3.
12
Fig.3: An example of SDM of 100 samples of one period a sine wave. 1-bit samples (e.g., comparator output) overlaid with sine wave where logic high (e.g., ) represented by blue and logic low (e.g., ) represented by white.
In general, has some advantages versus modulation: The whole structure is simpler: Only one integrator is needed The demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal The quantizer (e.g., comparator) can have full-scale outputs The quantized value is the integral of the difference signal, which makes it less sensitive to the rate of change of the signal.
Principle
The principle of the architecture is explained at length in section 2. Initially, when a sequence starts, the circuit will have an arbitrary state which is dependant on the integral of all previous history. In mathematical terms this corresponds to the arbitrary integration constant of the indefinite integral. This follows from the fact that at the heart of the method there is an integrator which can have any arbitrary state dependant on previous input, see Fig. 1c (d). From the occurrence of the first pulse onward the frequency of the pulse stream is proportional to the input voltage to be transformed. A demonstration applet is available online to simulate the whole architecture.[2]
Variations
There are many kinds of ADC that use this delta-sigma structure. The above analysis focuses on the simplest 1st-order, 2-level, uniform-decimation sigma-delta ADC. Many ADCs use a second-order 5-level sinc3 sigma-delta structure.
2nd order and higher order modulator

The number of integrators, and consequently, the numbers of feedback loops, indicates the order of a -modulator; a 2nd order modulator is shown in Fig.4. First order modulators are unconditionally stable, but stability analysis must be performed for higher order modulators.
Fig.4: Block diagram of a 2nd order modulator
13
3-level and higher quantizer

The modulator can also be classified by the number of bits it has in output, which strictly depends on the output of the quantizer. The quantizer can be realized with a N-level comparator, thus the modulator has log2N-bit output. A simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a "1.5" bit quantizer; a 4-level quantizer is a 2 bit quantizer; a 5-level quantizer is called a "2.5 bit" quantizer.[3]
Decimation structures
The conceptually simplest decimation structure is a counter that is reset to zero at the beginning of each integration period, then read out at the end of the integration period. The multi-stage noise shaping (MASH) structure has a noise shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties: simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are required unconditionally stable (there are no feedback loops outside the accumulators) A very popular decimation structure is the sinc filter. For 2nd order modulators, the sinc3 filter is close to optimum.[4][5]
Quantization theory formulas

When a signal is quantized, the resulting signal approximately has the second-order statistics of a signal with independent additive white noise. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is
In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idle tones and pattern noise in Sigma-Delta converters. Oversampling ratio, where is the sampling frequency and is Nyquist rate
The rms noise voltage within the band of interest can be expressed in terms of OSR
14
Oversampling
Let's consider a signal at frequency and a sampling frequency of much higher than Nyquist rate (see fig.5). modulation is based on the technique of oversampling to reduce the noise in the band of interest (green), which also avoids the use of high-precision analog circuits for the anti-aliasing filter. The quantization noise is the same both in a Nyquist converter (in yellow) and in an oversampling converter (in blue), but it is distributed over a larger spectrum. In -converters, noise is further reduced at low frequencies, which is the band where the signal of interest is, and it is Fig.5: Noise shaping curves and noise spectrum in modulator increased at the higher frequencies, where it can be filtered. This technique is known as noise shaping. For a first order delta sigma modulator, the noise is shaped by a filter with transfer function Assuming that the sampling frequency approximated as: . Similarly for a second order delta sigma modulator, the noise is shaped by a filter with transfer function . The in-band quantization noise can be approximated as: . In general, for a -order -modulator, the variance of the in-band quantization noise: . When the sampling frequency is doubled, the signal to quantization noise is improved by for a .
, the quantization noise in the desired signal bandwidth can be
-order -modulator. The higher the oversampling ratio, the higher the signal-to-noise ratio and the higher the resolution in bits. Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of averaging of the higher data rate bitstream.
15
Example of decimation
Let's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110, counting the number of ones, the decimation result is 4/8 = 0.5 = 100b (binary); in other words, the sample frequency is reduced by a factor of eight the serial (1-bit) input bus becomes a parallel (3-bits) output bus.
Naming
The technique was first presented in the early 1960s by prof. Haruhiko Yasuda while he was student at Waseda University, Tokyo, Japan, The name Delta-Sigma comes directly from the presence of a Delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.[6] That is, the name comes from integrating or "summing" differences, which are operations usually associated with Greek letters Sigma and Delta respectively. Both names Sigma-Delta and Delta-Sigma are frequently used.
References
[1] Voltage-to-Frequency Converters (http:/ / www. analog. com/ static/ imported-files/ tutorials/ MT-028. pdf) by Walt Kester and James Bryant 2009. Analog Devices. [2] Analog Devices : Virtual Design Center : Interactive Design Tools : Sigma-Delta ADC Tutorial (http:/ / designtools. analog. com/ dt/ sdtutorial/ sdtutorial. html) [3] Sigma-delta class-D amplifier and control method for a sigma-delta class-D amplifier (http:/ / www. faqs. org/ patents/ app/ 20090072897) by Jwin-Yen Guo and Teng-Hung Chang [4] A Novel Architecture for DAQ in Multi-channel, Large Volume, Long Drift Liquid Argon TPC (http:/ / www. slac. stanford. edu/ econf/ C0604032/ papers/ 0232. PDF) by S. Centro, G. Meng, F. Pietropaola, S. Ventura 2006 [5] A Low Power Sinc3 Filter for Modulators (http:/ / ieeexplore. ieee. org/ xpl/ freeabs_all. jsp?arnumber=4253561) by A. Lombardi, E. Bonizzoni, P. Malcovati, F. Maloberti 2007 [6] H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- Modulation", IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209.
Walt Kester (2008-10). "ADC Architectures III: Sigma-Delta ADC Basics" (http://www.analog.com/static/ imported-files/tutorials/MT-022.pdf) (PDF). Analog Devices. Retrieved 2010-11-02. R. Jacob Baker (2009). CMOS Mixed-Signal Circuit Design (http://CMOSedu.com/) (2nd ed.). Wiley-IEEE. ISBN978-0-470-29026-2. R. Schreier, G. Temes (2005). Understanding Delta-Sigma Data Converters. ISBN0-471-46585-2. S. Norsworthy, R. Schreier, G. Temes (1997). Delta-Sigma Data Converters. ISBN0-7803-1045-4. J. Candy, G. Temes (1992). Oversampling Delta-sigma Data Converters. ISBN0-87942-285-8.
External links
1-bit A/D and D/A Converters (http://www.cs.tut.fi/sgn/arg/rosti/1-bit/) Sigma-delta techniques extend DAC resolution (http://www.embedded.com//showArticle. jhtml?articleID=22101730) article by Tim Wescott 2004-06-23 Tutorial on Designing Delta-Sigma Modulators: Part I (http://www.commsdesign.com/design_corner/ showArticle.jhtml?articleID=18402743) and Part II (http://www.commsdesign.com/design_corner/ showArticle.jhtml?articleID=18402763) by Mingliang (Michael) Liu Gabor Temes' Publications (http://eecs.oregonstate.edu/research/members/temes/pubs.html) Simple Sigma Delta Modulator example (http://electronjunkie.wordpress.com/tag/sigma-delta-modulation/) Contains Block-diagrams, code, and simple explanations Example Simulink model & scripts for continuous-time sigma-delta ADC (http://www.circuitdesign.info/blog/ 2008/09/example-simulink-model-scripts/) Contains example matlab code and Simulink model Bruce Wooley's Delta-Sigma Converter Projects (http://www-cis.stanford.edu/icl/wooley-grp/projects.html)
Delta-sigma modulation An Introduction to Delta Sigma Converters (http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html) (which covers both ADC's and DAC's sigma-delta) Demystifying Sigma-Delta ADCs (http://www.maxim-ic.com/appnotes.cfm/an_pk/1870/CMP/WP-10). This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter. Motorola digital signal processors: Principles of sigma-delta modulation for analog-to-digital converters (http:// digitalsignallabs.com/SigmaDelta.pdf) One-Bit Delta Sigma D/A Conversion Part I: Theory (http://www.digitalsignallabs.com/presentation.pdf) article by Randy Yates presented at the 2004 comp.dsp conference MASH (Multi-stAge noise SHaping) structure (http://www.holmea.demon.co.uk/Frac2/Mash.htm) with both theory and a block-level implementation of a MASH How a Sigma-Delta ADC Works at TechOnline (http://www.techonline.com/learning/course/100152) free registration required to read the article Continuous time sigma-delta ADC noise shaping filter circuit architectures (http://www.circuitdesign.info/ blog/2008/11/continuous-time-sigma-delta-adc-noise-shaping-filter-circuit-architectures-2/) discusses architectural trade-offs for continuous-time sigma-delta noise-shaping filters Some intuitive motivation for why a Delta Sigma modulator works (http://www.cardinalpeak.com/blog/ ?p=392/)
16
Current mirror
A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. The current being 'copied' can be, and sometimes is, a varying signal current. Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that reverses the current direction as well or it is a current-controlled current source (CCCS). The current mirror is used to provide bias currents and active loads to circuits
Mirror characteristics
There are three main specifications that characterize a current mirror. The first is the transfer ratio (in the case of a current amplifier) or the output current magnitude (in the case of a constant current source CCS). The second is its AC output resistance, which determines how much the output current varies with the voltage applied to the mirror. The third specification is the minimum voltage drop across the output part of the mirror necessary to make it work properly. This minimum voltage is dictated by the need to keep the output transistor of the mirror in active mode. The range of voltages where the mirror works is called the compliance range and the voltage marking the boundary between good and bad behavior is called the compliance voltage. There are also a number of secondary performance issues with mirrors, for example, temperature stability.
Current mirror
17
Practical approximations
For small-signal analysis the current mirror can be approximated by its equivalent Norton impedance . In large-signal hand analysis, a current mirror is usually and simply approximated by an ideal current source. However, an ideal current source is unrealistic in several respects: it has infinite AC impedance, while a practical mirror has finite impedance it provides the same current regardless of voltage, that is, there are no compliance range requirements it has no frequency limitations, while a real mirror has limitations due to the parasitic capacitances of the transistors the ideal source has no sensitivity to real-world effects like noise, power-supply voltage variations and component tolerances.
Circuit realizations of current mirrors

Basic idea
A bipolar transistor can be used as the simplest current-to-current converter but its transfer ratio would highly depend on temperature variations, tolerances, etc. To eliminate these undesired disturbances, a current mirror is composed of two cascaded A current mirror consists of two cascaded inverse converters with mirrored transfer current-to-voltage and characteristic. voltage-to-current converters placed at the same conditions and having reverse characteristics. They have not to be obligatory linear; the only requirement is their characteristics to be mirrorlike (for example, in the BJT current mirror below, they are logarithmic and exponential). Usually, two identical converters are used but the characteristic of the first one is reversed by applying a negative feedback. Thus a current mirror consists of two cascaded equal converters (the first - reversed and the second - direct).
Basic BJT current mirror

If a voltage is applied to the BJT base-emitter junction as an input quantity and the collector current is taken as an output quantity, the transistor will act as an exponential voltage-to-current converter. By applying a negative feedback (simply joining the base and collector) the transistor can be "reversed" and it will begin acting as the opposite logarithmic current-to-voltage converter; now it will adjust the "output" base-emitter voltage so as to pass the applied "input" collector current. The simplest bipolar current mirror (shown in Figure 1) implements this idea. It consists of two cascaded transistor stages acting accordingly as a reversed and direct voltage-to-current converters. Transistor Q1 is connected to ground. Its collector-base voltage is zero as shown. Consequently, the voltage drop across Q1
Figure 1: A current mirror implemented with npn bipolar transistors using a resistor to set the reference current IREF; VCC = supply voltage
Current mirror is VBE, that is, this voltage is set by the diode law and Q1 is said to be diode connected. (See also Ebers-Moll model.) It is important to have Q1 in the circuit instead of a simple diode, because Q1 sets VBE for transistor Q2. If Q1 and Q2 are matched, that is, have substantially the same device properties, and if the mirror output voltage is chosen so the collector-base voltage of Q2 is also zero, then the VBE-value set by Q1 results in an emitter current in the matched Q2 that is the same as the emitter current in Q1. Because Q1 and Q2 are matched, their 0-values also agree, making the mirror output current the same as the collector current of Q1. The current delivered by the mirror for arbitrary collector-base reverse bias VCB of the output transistor is given by (see bipolar transistor): , where IS = reverse saturation current or scale current, VT = thermal voltage and VA = Early voltage. This current is related to the reference current IREF when the output transistor VCB = 0 V by:
18
as found using Kirchhoff's current law at the collector node of Q1: The reference current supplies the collector current to Q1 and the base currents to both transistors when both transistors have zero base-collector bias, the two base currents are equal, IB1=IB2=IB.
Parameter 0 is the transistor -value for VCB = 0 V. Output resistance If VCB is greater than zero in output transistor Q2, the collector current in Q2 will be somewhat larger than for Q1 due to the Early effect. In other words, the mirror has a finite output (or Norton) resistance given by the rO of the output transistor, namely (see Early effect): , where VA = Early voltage and VCB = collector-to-base bias. Compliance voltage To keep the output transistor active, VCB 0 V. That means the lowest output voltage that results in correct mirror behavior, the compliance voltage, is VOUT = VCV = VBE under bias conditions with the output transistor at the output current level IC and with VCB = 0 V or, inverting the I-V relation above:
where VT = thermal voltage and IS = reverse saturation current or scale current.
Current mirror Extensions and complications When Q2 has VCB > 0 V, the transistors no longer are matched. In particular, their -values differ due to the Early effect, with
19
where VA is the Early voltage and 0 = transistor for VCB = 0 V. Besides the difference due to the Early effect, the transistor -values will differ because the 0-values depend on current, and the two transistors now carry different currents (see Gummel-Poon model). Further, Q2 may get substantially hotter than Q1 due to the associated higher power dissipation. To maintain matching, the temperature of the transistors must be nearly the same. In integrated circuits and transistor arrays where both transistors are on the same die, this is easy to achieve. But if the two transistors are widely separated, the precision of the current mirror is compromised. Additional matched transistors can be connected to the same base and will supply the same collector current. In other words, the right half of the circuit can be duplicated several times with various resistor values replacing R2 on each. Note, however, that each additional right-half transistor "steals" a bit of collector current from Q1 due to the non-zero base currents of the right-half transistors. This will result in a small reduction in the programmed current. An example of a mirror with emitter degeneration to increase mirror resistance is found in two-port networks. For the simple mirror shown in the diagram, typical values of will yield a current match of 1% or better.
Basic MOSFET current mirror

The basic current mirror can also be implemented using MOSFET transistors, as shown in Figure 2. Transistor M1 is operating in the saturation or active mode, and so is M2. In this setup, the output current IOUT is directly related to IREF, as discussed next. The drain current of a MOSFET ID is a function of both the gate-source voltage and the drain-to-gate voltage of the MOSFET given by ID = f (VGS, VDG), a relationship derived from the functionality of the MOSFET device. In the case of transistor M1 of the mirror, ID = IREF. Reference current IREF is a known current, and can be provided by a resistor as shown, or by a "threshold-referenced" or "self-biased" current source to ensure that it is constant, independent of voltage supply variations.[1]
Using VDG=0 for transistor M1, the drain current in M1 is ID = f (VGS,VDG=0), so we find: f (VGS, 0) = IREF, implicitly determining the value of VGS. Thus IREF sets the value of VGS. The circuit in the diagram forces the same VGS to apply to transistor M2. If M2 is also biased with zero VDG and provided transistors M1 and M2 have good matching of their properties, such as channel length, width, threshold voltage etc., the relationship IOUT = f (VGS,VDG=0 ) applies, thus setting IOUT = IREF; that is, the output current is the same as the reference current when VDG=0 for the output transistor, and both transistors are matched. The drain-to-source voltage can be expressed as VDS=VDG +VGS. With this substitution, the Shichman-Hodges model provides an approximate form for function f (VGS,VDG):[1]
Figure 2: An n-channel MOSFET current mirror with a resistor to set the reference current IREF; VDD is the supply voltage
Current mirror where, is a technology related constant associated with the transistor, W/L is the width to length ratio of the
20
transistor, VGS is the gate-source voltage, Vth is the threshold voltage, is the channel length modulation constant, and VDS is the drain source voltage. Output resistance Because of channel-length modulation, the mirror has a finite output (or Norton) resistance given by the ro of the output transistor, namely (see channel length modulation): , where = channel-length modulation parameter and VDS = drain-to-source bias. Compliance voltage To keep the output transistor resistance high, VDG 0 V.[2] (see Baker).[3] That means the lowest output voltage that results in correct mirror behavior, the compliance voltage, is VOUT = VCV = VGS for the output transistor at the output current level with VDG = 0 V, or using the inverse of the f-function, f 1: . For Shichman-Hodges model, f Extensions and reservations A useful feature of this mirror is the linear dependence of f upon device width W, a proportionality approximately satisfied even for models more accurate than the Shichman-Hodges model. Thus, by adjusting the ratio of widths of the two transistors, multiples of the reference current can be generated. It must be recognized that the Shichman-Hodges model[4] is accurate only for rather dated technology, although it often is used simply for convenience even today. Any quantitative design based upon new technology uses computer models for the devices that account for the changed current-voltage characteristics. Among the differences that must be accounted for in an accurate design is the failure of the square law in Vgs for voltage dependence and the very poor modeling of Vds drain voltage dependence provided by Vds. Another failure of the equations that proves very significant is the inaccurate dependence upon the channel length L. A significant source of L-dependence stems from , as noted by Gray and Meyer, who also note that usually must be taken from experimental data.[1]
-1
is approximately a square-root function.
Current mirror
21
Feedback assisted current mirror

Figure 3 shows a mirror using negative feedback to increase output resistance. Because of the op amp, these circuits are sometimes called gain-boosted current mirrors. Because they have relatively low compliance voltages, they also are called wide-swing current mirrors. A variety of circuits based upon this idea are in use,[5][6][7] particularly for MOSFET mirrors because MOSFETs have rather low intrinsic output resistance values. A MOSFET version of Figure 3 is shown in Figure 4 where MOSFETs M3 and M4 operate in Ohmic mode to play the same role as emitter resistors RE in Figure 3, and MOSFETs M1 and M2 operate in active mode in the same roles as mirror transistors Q1 and Q2 in Figure 3. An explanation follows of how the circuit in Figure 3 works. The operational amplifier is fed the difference in voltages V1 - V2 at the top of the two emitter-leg resistors of value RE. This difference is amplified by the op amp and fed to the base of output transistor Q2. If the collector base reverse bias on Q2 is increased by increasing the applied voltage VA, the current in Q2 increases, increasing V2 and decreasing the difference V1 - V2 entering the op amp. Consequently, the base voltage of Q2 is decreased, and VBE of Q2 decreases, counteracting the increase in output current. If the op amp gain Av is large, only a very small difference V1 - V2 is sufficient to generate the needed base voltage VB for Q2, namely
Figure 3: Gain-boosted current mirror with op amp feedback to increase output resistance
Consequently, the currents in the two leg resistors are held nearly the same, and the output current of the mirror is very nearly the same as the collector current IC1 in Q1, which in turn is set by the reference current as
Figure 4: MOSFET version of wide-swing current mirror; M1 and M2 are in active mode, while M3 and M4 are in Ohmic mode and act like resistors
Current mirror where 1 for transistor Q1 and 2 for Q2 differ due to the Early effect if the reverse bias across the collector-base of Q2 is non-zero.
22
Figure 5: Small-signal circuit to determine output resistance of mirror; transistor Q2 is replaced with its hybrid-pi model; a test current IX at the output generates a voltage VX, and the output resistance is Rout = VX / IX.
Output resistance An idealized treatment of output resistance is given in the footnote.[8] A small-signal analysis for an op amp with finite gain Av but otherwise ideal is based upon Figure 5 (, rO and r refer to Q2). To arrive at Figure 5, notice that the positive input of the op amp in Figure 3 is at AC ground, so the voltage input to the op amp is simply the AC emitter voltage Ve applied to its negative input, resulting in a voltage output of Av Ve. Using Ohm's law across the input resistance r determines the small-signal base current Ib as:
Combining this result with Ohm's law for RE, Ve can be eliminated, to find:[9]
Kirchhoff's voltage law from the test source IX to the ground of RE provides: Substituting for Ib and collecting terms the output resistance Rout is found to be:
For a large gain Av >> r / RE the maximum output resistance obtained with this circuit is a substantial improvement over the basic mirror where Rout = rO. The small-signal analysis of the MOSFET circuit of Figure 4 is obtained from the bipolar analysis by setting = gm r in the formula for Rout and then letting r . The result is This time, RE is the resistance of the source-leg MOSFETs M3, M4. Unlike Figure 3, however, as Av is increased (holding RE fixed in value), Rout continues to increase, and does not approach a limiting value at large Av.
Current mirror Compliance voltage For Figure 3, a large op amp gain achieves the maximum Rout with only a small RE. A low value for RE means V2 also is small, allowing a low compliance voltage for this mirror, only a voltage V2 larger than the compliance voltage of the simple bipolar mirror. For this reason this type of mirror also is called a wide-swing current mirror, because it allows the output voltage to swing low compared to other types of mirror that achieve a large Rout only at the expense of large compliance voltages. With the MOSFET circuit of Figure 4, like the circuit in Figure 3, the larger the op amp gain Av, the smaller RE can be made at a given Rout, and the lower the compliance voltage of the mirror.
23
Other current mirrors

There are many sophisticated current mirrors that have higher output resistances than the basic mirror (more closely approach an ideal mirror with current output independent of output voltage) and produce currents less sensitive to temperature and device parameter variations and to circuit voltage fluctuations. These multi-transistor mirror circuits are used both with bipolar and MOS transistors. These circuits include: the Widlar current source the Wilson current source the Cascoded current sources
Notes
[1] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer (2001). Analysis and Design of Analog Integrated Circuits (Fourth Edition ed.). New York: Wiley. p.308309. ISBN0471321680. [2] Keeping the output resistance high means more than keeping the MOSFET in active mode, because the output resistance of real MOSFETs only begins to increase on entry into the active region, then rising to become close to maximum value only when VDG 0 V. [3] R. Jacob Baker (2010). CMOS Circuit Design, Layout and Simulation (Third ed.). New York: Wiley-IEEE. pp.297, 9.2.1 and Figure 20.28, p. 636. ISBN978-0-470-88132-3. [4] NanoDotTek Report NDT14-08-2007, 12 August 2007 (http:/ / www. nanodottek. com/ NDT14_08_2007. pdf) [5] R. Jacob Baker. 20.2.4 pp. 645646. ISBN978-0-470-88132-3. [6] Ivanov VI and Filanovksy IM (2004). Operational amplifier speed and accuracy improvement: analog circuit design with structural methodology (http:/ / books. google. com/ books?id=IuLsny9wKIIC& pg=PA110& dq=gain+ boost+ wide+ + "current+ mirror"#PPA107,M1) (The Kluwer international series in engineering and computer science, v. 763 ed.). Boston, Mass.: Kluwer Academic. p.6.1, p. 105108. ISBN1-4020-7772-6. . [7] W. M. C. Sansen (2006). Analog design essentials. New York ; Berlin: Springer. p.0310, p. 93. ISBN0-387-25746-2. [8] An idealized version of the argument in the text, valid for infinite op amp gain, is as follows. If the op amp is replaced by a nullor, voltage V2 = V1, so the currents in the leg resistors are held at the same value. That means the emitter currents of the transistors are the same. If the VCB of Q2 increases, so does the output transistor because of the Early effect: = 0 ( 1 + VCB / VA ). Consequently the base current to Q2 given by IB = IE / ( + 1) decreases and the output current Iout = IE / (1 + 1 / ) increases slightly because increases slightly. Doing the math,
where the transistor output resistance is given by rO = ( VA + VCB ) / Iout. That is, the ideal mirror resistance for the circuit using an ideal op amp nullor is Rout = ( + 1 ) rO, in agreement with the value given later in the text when the gain .
[9] Notice that as Av , Ve 0 and Ib IX.
Current mirror
24
References External links

Patent (1968) by RJ Widlar: Biasing scheme especially suited for integrated circuits (http://www.google.com/ patents?hl=en&id=IhlMAAAAEBAJ&dq=+"Biasing+scheme+especially+suited+for+integrated+circuits"& printsec=frontcover&source=web&ots=Oq1T4owqMu&sig=oYenqTCaZip9QTcLwVjIcOgIc-U&sa=X& oi=book_result&resnum=4&ct=result#PPP3,M1) Current mirrors (http://www.google.bg/search?hl=en&source=hp&biw=1266&bih=641&q=current+ mirror&oq=current+mirror&aq=f&aqi=g10&aql=&gs_sm=e& gs_upl=1781l6281l0l14l14l0l3l3l0l328l2455l0.4.6.1) 4QD tec - Current sources and mirrors (http://www.4qdtec.com/csm.html) Compendium of circuits and descriptions
Pulse-width modulation
Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches. The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off periods, the higher the power supplied to the load is. The PWM switching frequency has to An example of PWM in an AC motor drive: the phase-to-phase voltage (blue) is modulated as a series of pulses that results in a sine-like flux density waveform (red) in be much faster than what would affect the magnetic circuit of the motor. The smoothness of the resultant waveform can be the load, which is to say the device that controlled by the width and number of modulated impulses (per given cycle) uses the power. Typically switchings have to be done several times a minute in an electric stove, 120Hz in a lamp dimmer, from few kilohertz (kHz) to tens of kHz for a motor drive and well into the tens or hundreds of kHz in audio amplifiers and computer power supplies. The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time; a low duty cycle corresponds to low power, because the power is off for most of the time. Duty cycle is expressed in percent, 100% being fully on. The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there is practically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being the product of voltage and current, is thus in both cases close to zero. PWM also works well with digital controls, which, because of their on/off nature, can easily set the needed duty cycle. PWM has also been used in certain communication systems where its duty cycle has been used to convey information over a communications channel.
25
History
In the past, when only partial power was needed (such as for a sewing machine motor), a rheostat (located in the sewing machine's foot pedal) connected in series with the motor adjusted the amount of current flowing through the motor, but also wasted power as heat in the resistor element. It was an inefficient scheme, but tolerable because the total power was low. This was one of several methods of controlling power. There were otherssome still in usesuch as variable autotransformers, including the trademarked 'Autrastat' for theatrical lighting; and the Variac, for general AC power adjustment. These were quite efficient, but also relatively costly. For about a century, some variable-speed electric motors have had decent efficiency, but they were somewhat more complex than constant-speed motors, and sometimes required bulky external electrical apparatus, such as a bank of variable power resistors or rotating converter such as Ward Leonard drive . However, in addition to motor drives for fans, pumps and robotic servos, there was a great need for compact and low cost means for applying adjustable power for many devices, such as electric stoves and lamp dimmers. One early application of PWM was in the Sinclair X10, a 10W audio amplifier available in kit form in the 1960s. At around the same time PWM started to be used in AC motor control [1]
Principle
Pulse-width modulation uses a rectangular pulse wave whose pulse width is modulated resulting in the variation of the average value of the waveform. If we consider a pulse waveform with a low value , a high value and a duty cycle D (see figure 1), the average value of the waveform is given by:
Fig. 1: a pulse wave, showing the definitions of , and D.
As for
is a pulse wave, its value is and for . The above expression then becomes:
This latter expression can be fairly simplified in many cases where obvious that the average value of the signal (
as
. From this, it is
) is directly dependent on the duty cycle D.
26
The simplest way to generate a PWM signal is the intersective method, which requires only a sawtooth or a triangle waveform (easily generated using a simple oscillator) and a comparator. When the value of the reference signal (the red sine wave in figure 2) is more than the modulation waveform (blue), the PWM signal (magenta) is in the high state, otherwise it is in the low state.
Delta
In the use of delta modulation for PWM control, the output signal is integrated, and the result is compared with limits, which correspond to a Reference signal offset by a constant. Every time the integral of the output signal reaches one of the limits, the PWM signal changes state.
Fig. 2: A simple method to generate the PWM pulse train corresponding to a given signal is the intersective PWM: the signal (here the red sinewave) is compared with a sawtooth waveform (blue). When the latter is less than the former, the PWM signal (magenta) is in high state (1). Otherwise it is in the low state (0).
Delta-sigma
In delta-sigma modulation as a PWM control method, the output signal is subtracted from a reference signal to form an error signal. This error is integrated, and when the integral of the error exceeds the limits, the output changes state.
Fig. 3 : Principle of the delta PWM. The output signal (blue) is compared with the limits (green). These limits correspond to the reference signal (red), offset by a given value. Every time the output signal reaches one of the limits, the PWM signal changes state.
27
Space vector modulation

Space vector modulation is a PWM control algorithm for multi-phase AC generation, in which the reference signal is sampled regularly; after each sample, non-zero active switching vectors adjacent to the reference vector and one or more of the zero switching vectors are selected for the appropriate fraction of the sampling period in order to synthesize the reference signal as the average of the used vectors.
Direct torque control (DTC)

Direct torque control is a method used to control AC motors. It is closely Fig. 4 : Principle of the sigma-delta PWM. The top green waveform is the reference related with the delta modulation (see signal, on which the output signal (PWM, in the bottom plot) is subtracted to form the above). Motor torque and magnetic error signal (blue, in top plot). This error is integrated (middle plot), and when the integral flux are estimated and these are of the error exceeds the limits (red lines), the output changes state. controlled to stay within their hysteresis bands by turning on new combination of the device's semiconductor switches each time either of the signal tries to deviate out of the band.
Time proportioning
Many digital circuits can generate PWM signals (e.g. many microcontrollers have PWM outputs). They normally use a counter that increments periodically (it is connected directly or indirectly to the clock of the circuit) and is reset at the end of every period of the PWM. When the counter value is more than the reference value, the PWM output changes state from high to low (or low to high).[2] This technique is referred to as time proportioning, particularly as time-proportioning control[3] which proportion of a fixed cycle time is spent in the high state. The incremented and periodically reset counter is the discrete version of the intersecting method's sawtooth. The analog comparator of the intersecting method becomes a simple integer comparison between the current counter value and the digital (possibly digitized) reference value. The duty cycle can only be varied in discrete steps, as a function of the counter resolution. However, a high-resolution counter can provide quite satisfactory performance.
28
Types
Three types of pulse-width modulation (PWM) are possible: 1. The pulse center may be fixed in the center of the time window and both edges of the pulse moved to compress or expand the width. 2. The lead edge can be held at the lead edge of the window and the tail edge modulated. 3. The tail edge can be fixed and the lead edge modulated.
Spectrum
The resulting spectra (of the three cases) are similar, and each contains a dc component, a base sideband Fig. 5 : Three types of PWM signals (blue): leading edge modulation (top), trailing edge containing the modulating signal and modulation (middle) and centered pulses (both edges are modulated, bottom). The green phase modulated carriers at each lines are the sawtooth waveform (first and second cases) and a triangle waveform (third harmonic of the frequency of the pulse. case) used to generate the PWM waveforms using the intersective method. The amplitudes of the harmonic groups are restricted by a envelope (sinc function) and extend to infinity. On the contrary, the delta modulation is a random process that produces continuous spectrum without distinct harmonics.
Applications
Telecommunications
In telecommunications, the widths of the pulses correspond to specific data values encoded at one end and decoded at the other. Pulses of various lengths (the information itself) will be sent at regular intervals (the carrier frequency of the modulation). _ Clock _ _ _ _ _ _ _
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __| |____| |____| |____| |____| |____| |____| |____| |____ _ __ ____ ____ _ | | | | | | | | | | | | | | | | | | | | _________| |____| |___| |________| |_| |___________ 0 1 2 4 0 4 1 0
PWM Signal
Data
The inclusion of a clock signal is not necessary, as the leading edge of the data signal can be used as the clock if a small offset is added to the data value in order to avoid a data value with a zero length pulse.
Pulse-width modulation _ PWM Signal | | | | | | __| |____| 0 1 __ | | | | |___| 2 ___ | | | | |__| 4 _____ _ | | | | | | | | |_| |____| 0 4 _____ | | | | |_| 1 __ _ | | | | | | |___| |_____ 0
29
Data
Power delivery
PWM can be used to control the amount of power delivered to a load without incurring the losses that would result from linear power delivery by resistive means. Potential drawbacks to this technique are the pulsations defined by the duty cycle, switching frequency and properties of the load. With a sufficiently high switching frequency and, when necessary, using additional passive electronic filters, the pulse train can be smoothed and average analog waveform recovered. High frequency PWM power control systems are easily realisable with semiconductor switches. As explained above, almost no power is dissipated by the switch in either on or off state. However, during the transitions between on and off states, both voltage and current are non-zero and thus power is dissipated in the switches. By quickly changing the state between fully on and fully off (typically less than 100 nanoseconds), the power dissipation in the switches can be quite low compared to the power being delivered to the load. Modern semiconductor switches such as MOSFETs or Insulated-gate bipolar transistors (IGBTs) are well suited components for high efficiency controllers. Frequency converters used to control AC motors may have efficiencies exceeding 98 %. Switching power supplies have lower efficiency due to low output voltage levels (often even less than 2 V for microprocessors are needed) but still more than 70-80 % efficiency can be achieved. Variable-speed fan controllers for computers usually use PWM, as it is far more efficient when compared to a potentiometer or rheostat. (Neither of the latter is practical to operate electronically; they would require a small drive motor.) Light dimmers for home use employ a specific type of PWM control. Home-use light dimmers typically include electronic circuitry which suppresses current flow during defined portions of each cycle of the AC line voltage. Adjusting the brightness of light emitted by a light source is then merely a matter of setting at what voltage (or phase) in the AC halfcycle the dimmer begins to provide electrical current to the light source (e.g. by using an electronic switch such as a triac). In this case the PWM duty cycle is the ratio of the conduction time to the duration of the half AC cycle defined by the frequency of the AC line voltage (50 Hz or 60 Hz depending on the country). These rather simple types of dimmers can be effectively used with inert (or relatively slow reacting) light sources such as incandescent lamps, for example, for which the additional modulation in supplied electrical energy which is caused by the dimmer causes only negligible additional fluctuations in the emitted light. Some other types of light sources such as light-emitting diodes (LEDs), however, turn on and off extremely rapidly and would perceivably flicker if supplied with low frequency drive voltages. Perceivable flicker effects from such rapid response light sources can be reduced by increasing the PWM frequency. If the light fluctuations are sufficiently rapid, the human visual system can no longer resolve them and the eye perceives the time average intensity without flicker (see flicker fusion threshold). In electric cookers, continuously-variable power is applied to the heating elements such as the hob or the grill using a device known as a Simmerstat. This consists of a thermal oscillator running at approximately two cycles per minute and the mechanism varies the duty cycle according to the knob setting. The thermal time constant of the heating elements is several minutes, so that the temperature fluctuations are too small to matter in practice.
30
Voltage regulation
PWM is also used in efficient voltage regulators. By switching voltage to the load with the appropriate duty cycle, the output will approximate a voltage at the desired level. The switching noise is usually filtered with an inductor and a capacitor. One method measures the output voltage. When it is lower than the desired voltage, it turns on the switch. When the output voltage is above the desired voltage, it turns off the switch.
Audio effects and amplification

PWM is sometimes used in sound (music) synthesis, in particular subtractive synthesis, as it gives a sound effect similar to chorus or slightly detuned oscillators played together. (In fact, PWM is equivalent to the difference of two sawtooth waves. [4]) The ratio between the high and low level is typically modulated with a low frequency oscillator, or LFO. In addition, varying the duty cycle of a pulse waveform in a subtractive-synthesis instrument creates useful timbral variations. Some synthesizers have a duty-cycle trimmer for their square-wave outputs, and that trimmer can be set by ear; the 50% point was distinctive, because even-numbered harmonics essentially disappear at 50%. A new class of audio amplifiers based on the PWM principle is becoming popular. Called "Class-D amplifiers", these amplifiers produce a PWM equivalent of the analog input signal which is fed to the loudspeaker via a suitable filter network to block the carrier and recover the original audio. These amplifiers are characterized by very good efficiency figures ( 90%) and compact size/light weight for large power outputs. For a few decades, industrial and military PWM amplifiers have been in common use, often for driving servo motors. They offer very good efficiency, commonly well above 90%. Field-gradient coils in MRI machines are driven by relatively-high-power PWM amplifiers. Historically, a crude form of PWM has been used to play back PCM digital sound on the PC speaker, which is driven by only two voltage levels, typically 0 V and 5 V. By carefully timing the duration of the pulses, and by relying on the speaker's physical filtering properties (limited frequency response, self-inductance, etc.) it was possible to obtain an approximate playback of mono PCM samples, although at a very low quality, and with greatly varying results between implementations. In more recent times, the Direct Stream Digital sound encoding method was introduced, which uses a generalized form of pulse-width modulation called pulse density modulation, at a high enough sampling rate (typically in the order of MHz) to cover the whole acoustic frequencies range with sufficient fidelity. This method is used in the SACD format, and reproduction of the encoded audio signal is essentially similar to the method used in class-D amplifiers.
References
[1] Schnung, A.; Stemmler, H. (August 1964). "Geregelter Drehstrom-Umkehrantrieb mit gesteuertem Umrichter nach dem Unterschwingungsverfahren". BBC Mitteilungen (Brown Boveri et Cie) 51 (8/9): 555577. [2] www.netrino.com Introduction to Pulse Width Modulation (PWM) (http:/ / www. netrino. com/ Embedded-Systems/ How-To/ PWM-Pulse-Width-Modulation) [3] Fundamentals of HVAC Control Systems, by Robert McDowall, p. 21 (http:/ / books. google. com/ books?id=UMk1EUp-W-UC& pg=PA21& dq="time+ proportioning") [4] http:/ / www. soundonsound. com/ sos/ Mar03/ articles/ synthsecrets47. asp
31
External links
An Introduction to Delta Sigma Converters (http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html) Introductory Tutorial (http://www.embedded.com.au/pages/Motor_Interface.html) on PWM and Quadrature Encoding
Smart transducer
A smart transducer is an analog or digital transducer or actuator combined with a processing unit and a communication interface. As sensors and actuators become more complex they provide support for various modes of operation and interfacing. Some applications require A smart transducer containing a transducer, processing unit and communication interface. additionally fault-tolerance and distributed computing. Such high-level functionality can be achieved by adding an embedded microcontroller to the classical sensor/actuator, which increases the ability to cope with complexity at a fair price. In the machine vision field, a single compact unit which combines the imaging functions and the complete image processing functions is often called a smart sensor.
Translinear circuit
A translinear circuit is a circuit that carries out its function using the translinear principle. These are current-mode circuits that can be made using transistors that obey an exponential current-voltage characteristicthis includes BJTs and CMOS transistors in weak inversion. The word translinear (TL) was invented by Barrie Gilbert in 1975[1] to describe circuits that used the exponential current-voltage relation of BJTs[2][3]. By using this exponential relationship, this class of circuits can implement multiplication, amplification and power-law relationships. When Barrie Gilbert described this class of circuits he also described the translinear principle (TLP) which made the analysis of these circuits possible in a way that the previous view of BJTs as linear current amplifiers did not allow. TLP was later extended to include other elements that obey an exponential current-voltage relationship (such as CMOS transistors in weak inversion). The TLP has been used in a variety of circuits including vector arithmetic circuits[4], current conveyors, current-mode operational amplifiers, and RMS-DC converters[5]. It has been in use since the 1960s (by Gilbert), but was not formalized until 1975[1]. In the 1980s, Evert Seevinck's work helped to create a systematic process for translinear circuit design. In 1990 Seevinck invented a circuit he called a companding current-mode integrator[6] that was effectively a first-order log-domain filter. A version of this was generalized in 1993 by Douglas Frey and the connection between this class of filters and TL circuits was made most explicit in the late 90s work of Jan Mulder et al. where they describe the dynamic translinear principle. More work by Seevinck led to synthesis techniques for extremely low-power TL circuits[7]. More recent work in the field has led to the voltage-translinear principle, multiple-input translinear element networks, and field-programmable analog arrays (FPAAs).
Translinear circuit
32
The Translinear Principle

The translinear principle is that in a closed loop containing an even number of translinear elements (TEs) with an equal number of them arranged clockwise and counter-clockwise, the product of the currents through the clockwise TEs equals the product of the currents through the counter-clockwise TEs or The TLP is dependent on the exponential current-voltage relationship of a circuit element. Thus, an ideal TE follows the relationship
where
is a pre-exponential scaling current,
is a dimensionless multiplier to .
is a dimensionless
multiplier to the gate-emitter voltage and
is the thermal voltage
In a circuit, TEs are described as either clockwise (CW) or counterclockwise (CCW). If the arrow on the emitter point clockwise, it's considered a CW TE, if it points counterclockwise, it's considered a CCW TE. Consider an example:
A circuit with a translinear loop
By Kirchoff's Voltage Law, the voltage around the loop that goes from
to
must be 0. In other words, the
voltage drops must equal the voltage increases. When a loop that only goes through the emitter-gate connections of TEs exists, we call it a translinear loop. Mathematically, this becomes
Because of the exponential current-voltage relationship, this implies TLP:
this is effectively because current is used as the signal. Because of this, voltage is the log of the signal and addition in the log domain is like multiplication of the original signal (ie ). This rule, that the product of the current through CW TEs is equal to the current through CCW TEs in a translinear loop is known as the translinear principle. For a detailed derivation of the TLP, and physical interpretations of the parameters in the ideal TE law, please refer to [2] or [3]. A derivation of the TLP based on graph theory concepts has been given by Rafael Vargas-Bernal et al. in 2000[8][9]. In this work, it is illustrated as a graphical representation can be used for the future development of a verification tool that plays an important and fundamental role in the structured design of translinear circuits.
Translinear circuit
33
Example Translinear Circuits

Squaring Circuit
A TL squaring circuit using an alternating TL loop
According to TLP,
. This means that
where
is the unit scaling current (ie . This particular circuit is
the definition of unity for the circuit). This is effectively a squaring circuit where
designed in what is known as an alternating topology, which means that CW TEs alternate with CCW TEs. Here's the same circuit in a stacked topology.
A TL squaring circuit using a stacked TL loop
The same equation applies to this circuit as to the alternating topology according to TLP. Neither of these circuits can be implemented in real life without biasing the transistors such that the currents expected to flow through them can actually do so. Here are some example biasing schemes:
A biasing scheme for the alternating squaring circuit using diode connections.
A biasing scheme for the alternating squaring circuit using diode connections and a feedback connection between the collector and emitter of the TE (EP connection).
A biasing scheme for the stacked squaring circuit using diode connections and an EP connection.
Translinear circuit
34
2-Quadrant Multiplier
The design of a 2-quadrant multiplier can be easily done using TLP. The first issue with this circuit is that negative values of currents need to be represented. Since all currents must be positive for the exponential relationship to hold (the log operation is not defined for negative numbers), positive currents must represent negative currents. The way this is done is by defining two positive currents whose difference is the current of interest. A two quadrant multiplier has the relationship We'll let and hold while allowing and to be either positive or negative. etc. Plugging these . This can be rephrased as . Also note that
values into the original equation yields
. By equating the positive and negative portions of the equation, two equations that can be directly built as translinear loops arise:
The following are the alternating loops that implement the desired equations and some biasing schemes for the circuit.
References
The translinear loops that implement our desired equations. [1] Gilbert, Barrie (1975-01-09). "Translinear circuits: a proposed classification". Electronics Letters 11 (1): 1416. doi:10.1049/el:19750011. [2] Liu, Shih-Chii; Jrg Kramer, Giacomo Indiveri, Tobias Delbrck, and Rodney Douglas (2002). Analog VLSI: Circuits and Principles (http:/ / books. google. com/ ?id=ewqb4aurZtMC& printsec=frontcover& dq=analog+ vlsi). MIT Press. ISBN0262122553. . [3] Minch, Bradley A. (2000) (PDF). Analysis and Synthesis of Translinear Circuits (http:/ / www. csl. cornell. edu/ TR/ CSL-TR-2000-1002. pdf). . Retrieved 2008-02-21. [4] Gilbert, Barrie (1976-05-27). "High-accuracy vector-difference and vector-sum circuits". Electronics Letters 12 (11): 293294. doi:10.1049/el:19760226. A biasing scheme for the alternating TL two-quadrant multiplier circuit using diode connections and an EP connection. [5] Ashok, S. (1976-04-15). "Translinear root-difference-of-squares circuit". Electronics Letters 12 (8): 194195. doi:10.1049/el:19760150. [6] Seevinck, Evert (1990-11-22). "Companding current-mode integrator: a new circuit principle for continuous-time monolithic filters". Electronics Letters 26 (24): 20462047. doi:10.1049/el:19901319. [7] Seevinck, Evert; Vittoz, E.A.; Du Plessi, M.; Joubert, T.H.; Beetge, W. (December, 2000). "CMOS Translinear Circuits for Minimum Supply Voltage". IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing 47 (12): 15601564. doi:10.1109/82.899656. [8] Vargas-Bernal, Rafael; Reyes, Arturo Sarmiento; Serdijn, Wouter A. (2831 May 2000). "Identifying Translinear Loops in the Circuit Topology". Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland. 2. pp. 585588. doi:10.1109/ISCAS.2000.856396. ISBN0-7803-5482-6 A biasing scheme that consolidates some current sources. [9] Vargas-Bernal, Rafael (November 2002). "Prediction of Multiple DC Operating Points in a CMOS Log-Domain Filter". Proceedings of the IEEE Latin-American CAS Tour, Puebla Mexico. pp. 7073.
Article Sources and Contributors
35
Article Sources and Contributors

Pulse-density modulation Source: http://en.wikipedia.org/w/index.php?oldid=474453198 Contributors: ABCD, Andux, Chzz, Damian Yerrick, Dcoetzee, Dpbsmith, EBB, Graham87, Hephaestos, Jaxl, Jbinder, Kaldosh, Kghose, Maximus Rex, Michael Hardy, Mjb, Moxfyre, NicholasKinar, Nunh-huh, Oleg Alexandrov, Oxymoron83, Pcap, Rbj, Reywas92, Rjf ie, Ross Fraser, SchreiberBike, Serrano24, Smack, Starx, Sylvain Leroux, TedPavlic, Wdwd, Xavier Gir, 25 anonymous edits Delta-sigma modulation Source: http://en.wikipedia.org/w/index.php?oldid=476791488 Contributors: 121a0012, Alain r, Ali@gwc.org.uk, Altzinn, Atlant, Bappi48, Beetelbug, Bob Bermani, Bpromo7, Bratsche, CapitalR, Charles Matthews, Cojoco, CyrilB, Damian Yerrick, DavidCary, Denisarona, DmitTrix, Edokter, Epugachev, Gaius Cornelius, Gerweck, GregorB, Hankwang, Hanspi, HenningThielemann, Icarus4586, Jd8837, Jim.henderson, Jkl, Jwinius, Katanzag, Krishnavedala, Kvng, Lanugo, Lm317t, Lulo.it, Lv131, Mahira75249, Margin1522, Markhurd, Mild Bill Hiccup, Mortense, MrOllie, Mwarren us, NOW, Ohconfucius, Omegatron, Onionmon, Optimale, Ozfest, Puffingbilly, Qdr, Requestion, Rich Farmbrough, Rjf ie, Rjwilmsi, S Roper, Sam8, Sanjosanjo, SchuminWeb, Serrano24, Snood1, Southcaltree, StradivariusTV, TedPavlic, Tetvesdugo, The Anome, Voidxor, Wsmarz, Yates, 152 anonymous edits Current mirror Source: http://en.wikipedia.org/w/index.php?oldid=472931941 Contributors: Albert Castillo, Albugwiki, Alfred Centauri, Azaghal of Belegost, Bjf, BorgQueen, Brews ohare, Chowbok, Circuit dreamer, DabMachine, Dr.K., Editor at Large, Everyking, Hooperbloob, ICE77, Iandiver, Inductiveload, Iridescent, Kungfuadam, Leonard G., Light current, Lindenh248, Lovibond, Mako098765, Matt B., Mboverload, Msiddalingaiah, Omegatron, Pdn, Petrb, Pgadfor, Rich Farmbrough, Rogerbrent, Rohitbd, Ronz, Royboycrashfan, Rpyle731, Rsashwinkumar, Searchme, Slasher-fun, Soap, Zangar, 91 anonymous edits Pulse-width modulation Source: http://en.wikipedia.org/w/index.php?oldid=467460285 Contributors: Adambro, Ademkader, Alll, Allmightyduck, Andy Dingley, Arjayay, Asher196, Bobo192, CapitalR, Chrike, Circuit dreamer, Ckatz, CyrilB, DARTH SIDIOUS 2, DMChatterton, DV8 2XL, Damian Yerrick, DavidCary, Deconstructhis, Dermeister, Deville, Dicklyon, DoostdarWKP, EnOreg, EpiVictor, Everyking, Fish and karate, Funky Monkey, F, GB fan, GRAHAMUK, GandalfDaGraay, Gerry Ashton, Giftlite, Glenn, Glrx, Gurch, Heron, Hooperbloob, Ian Pitchford, Ixfd64, JKN abb, Jaberwocky6669, Jaeger5432, Jeepday, Joel Saks, Johncatsoulis, Kenyon, KnightRider, Krishnavedala, Kubing, Lambtron, Leopold Stotch, Lumpbucket, ML1986, Matt B., Mayflowerone, Meestaplu, Michael Hardy, Mikey likes mountains, Mschlindwein, Nahum Reduta, Nbarth, Nick Wilson, Nikevich, Nit vs atwiki, OlEnglish, Phoenix7777, PierreAbbat, Politepunk, R'n'B, RJFJR, RandomAct, Rivertorch, Rohitbd, Rsutherland, RuM, S Roper, SCEhardt, Sam8, Selket, Shfork, Shulini, Simon Brady, SimonP, Sonett72, Spinningspark, Spook`, Squall line, Starx, Sven Manguard, TedPavlic, Teslaton, Tim Starling, Toffile, Twas Now, Wikipelli, Wizard191, Xzapro4, Yngvarr, Zangar, Zureks, 216 anonymous edits Smart transducer Source: http://en.wikipedia.org/w/index.php?oldid=442321089 Contributors: Huon, KJG2007, Kauai68, Malcolma, Michael Devore, North8000, Voin.legourski, 3 anonymous edits Translinear circuit Source: http://en.wikipedia.org/w/index.php?oldid=453455957 Contributors: Bdieseldorff, Bminch, Casmemsnano, Giftlite, Que, R'n'B, RTC, Rich Farmbrough, Roopunk, 1 anonymous edits
Image Sources, Licenses and Contributors
36
Image Sources, Licenses and Contributors

Image:Pulse-density modulation 1 period.gif Source: http://en.wikipedia.org/w/index.php?title=File:Pulse-density_modulation_1_period.gif License: Public Domain Contributors: Kaldosh, Wdwd Image:Pulse-density modulation 2 periods.gif Source: http://en.wikipedia.org/w/index.php?title=File:Pulse-density_modulation_2_periods.gif License: Public Domain Contributors: Kaldosh, Wdwd Image:Pulse density modulation.svg Source: http://en.wikipedia.org/w/index.php?title=File:Pulse_density_modulation.svg License: Creative Commons Attribution-Sharealike 3.0,2.5,2.0,1.0 Contributors: Original uploader was Moxfyre at en.wikipedia Image:Block Diagram Delta-Sigma.svg Source: http://en.wikipedia.org/w/index.php?title=File:Block_Diagram_Delta-Sigma.svg License: GNU Free Documentation License Contributors: Fuhghettaboutit, Puffingbilly, 1 anonymous edits Image:Fig 1a.svg Source: http://en.wikipedia.org/w/index.php?title=File:Fig_1a.svg License: GNU Free Documentation License Contributors: Puffingbilly Image:Fig. 1b.svg Source: http://en.wikipedia.org/w/index.php?title=File:Fig._1b.svg License: Creative Commons Attribution-Share Alike Contributors: Puffingbilly Image:Fig 1c.svg Source: http://en.wikipedia.org/w/index.php?title=File:Fig_1c.svg License: Creative Commons Attribution-Sharealike 3.0 Contributors: Puffingbilly Image:FromDtoDS.svg Source: http://en.wikipedia.org/w/index.php?title=File:FromDtoDS.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Katanzag Image:DeltaSigma2.svg Source: http://en.wikipedia.org/w/index.php?title=File:DeltaSigma2.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Katanzag Image:DeltaSigmaNoise.svg Source: http://en.wikipedia.org/w/index.php?title=File:DeltaSigmaNoise.svg License: Creative Commons Attribution-Sharealike 2.5 Contributors: Katanzag Image:Reverse function 450.jpg Source: http://en.wikipedia.org/w/index.php?title=File:Reverse_function_450.jpg License: GNU Free Documentation License Contributors: Cyril Mechkov -Circuit-fantasist Image:Simple bipolar mirror.svg Source: http://en.wikipedia.org/w/index.php?title=File:Simple_bipolar_mirror.svg License: Creative Commons Attribution-Sharealike 3.0,2.5,2.0,1.0 Contributors: Simple_bipolar_mirror.PNG: Brews ohare derivative work: Azaghal of Belegost (talk) Image:Simple MOSFET mirror.PNG Source: http://en.wikipedia.org/w/index.php?title=File:Simple_MOSFET_mirror.PNG License: Creative Commons Attribution-Share Alike Contributors: Brews ohare Image:Gain-assisted current mirror.svg Source: http://en.wikipedia.org/w/index.php?title=File:Gain-assisted_current_mirror.svg License: Creative Commons Attribution 2.5 Contributors: Albedo-ukr, Ea91b3dd Image:Wide-swing MOSFET mirror.svg Source: http://en.wikipedia.org/w/index.php?title=File:Wide-swing_MOSFET_mirror.svg License: Creative Commons Attribution 2.5 Contributors: Ea91b3dd Image:Mirror output resistance.PNG Source: http://en.wikipedia.org/w/index.php?title=File:Mirror_output_resistance.PNG License: Creative Commons Attribution-Share Alike Contributors: Brews ohare Image:PWM, 3-level.svg Source: http://en.wikipedia.org/w/index.php?title=File:PWM,_3-level.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Zureks Image:Duty cycle general.svg Source: http://en.wikipedia.org/w/index.php?title=File:Duty_cycle_general.svg License: Creative Commons Attribution-Sharealike 2.5 Contributors: Duty_cycle_general.png: Cyril BUTTAY derivative work: Krishnavedala (talk) Image:Pwm.svg Source: http://en.wikipedia.org/w/index.php?title=File:Pwm.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Pwm.png: CyrilB derivative work: Krishnavedala (talk) Image:Delta PWM.svg Source: http://en.wikipedia.org/w/index.php?title=File:Delta_PWM.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Delta_PWM.png: Cyril BUTTAY derivative work: Krishnavedala (talk) Image:Sigma-delta PWM.svg Source: http://en.wikipedia.org/w/index.php?title=File:Sigma-delta_PWM.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Sigma_delta.png: Cyril BUTTAY derivative work: Krishnavedala (talk) Image:Three PWM types.svg Source: http://en.wikipedia.org/w/index.php?title=File:Three_PWM_types.svg License: Creative Commons Attribution-Sharealike 2.5 Contributors: Three_types.png: Cyril BUTTAY derivative work: Krishnavedala (talk) Image:Smart transducer.gif Source: http://en.wikipedia.org/w/index.php?title=File:Smart_transducer.gif License: Public Domain Contributors: Voin.legourski Image:unbiased alt TL squaring.png Source: http://en.wikipedia.org/w/index.php?title=File:Unbiased_alt_TL_squaring.png License: Public Domain Contributors: BradleyMinch Image:unbiased stacked TL squaring.png Source: http://en.wikipedia.org/w/index.php?title=File:Unbiased_stacked_TL_squaring.png License: Public Domain Contributors: BradleyMinch Image:biased alt TL squaring.png Source: http://en.wikipedia.org/w/index.php?title=File:Biased_alt_TL_squaring.png License: Public Domain Contributors: BradleyMinch Image:biased alt TL squaring2.png Source: http://en.wikipedia.org/w/index.php?title=File:Biased_alt_TL_squaring2.png License: Public Domain Contributors: BradleyMinch Image:biased stacked TL squaring.png Source: http://en.wikipedia.org/w/index.php?title=File:Biased_stacked_TL_squaring.png License: Public Domain Contributors: BradleyMinch Image:unbiased alt TL twoquadmult.png Source: http://en.wikipedia.org/w/index.php?title=File:Unbiased_alt_TL_twoquadmult.png License: Public Domain Contributors: BradleyMinch Image:biased alt TL twoquadmult.png Source: http://en.wikipedia.org/w/index.php?title=File:Biased_alt_TL_twoquadmult.png License: Public Domain Contributors: BradleyMinch Image:biased alt TL twoquadmult2.png Source: http://en.wikipedia.org/w/index.php?title=File:Biased_alt_TL_twoquadmult2.png License: Public Domain Contributors: BradleyMinch
License
37
License
Creative Commons Attribution-Share Alike 3.0 Unported //creativecommons.org/licenses/by-sa/3.0/

Seminar Books

Enviado por

Dados do documento

Descrição original:

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Seminar Books

Enviado por

Direitos autorais:

Formatos disponíveis

CRMC prequesites

Rearranging terms, we obtain

modulator. The factor contributes less to the output

is represented as a single bit, meaning it can take on

This, finally, gives a formula for the output sample

in terms of the input sample

. The quantization error

Why delta-sigma modulation?

Why use delta-sigma modulation on a CD?

Why the delta-sigma analog to digital conversion?

Analog to digital conversion

is treated as the Dirac (delta) function and is specified by the .

step produced on integration. Here we indicate that step as

The interval between pulses, p, is determined by a feedback loop arranged so that

from the integral of v so that the

). At each step a pulse is added to the

Fig.1: Block diagram and waveforms for a sigma delta ADC.

Fig.1b: circuit diagram

Digital to analog conversion

Fig.2: Derivation of - from -modulation

2nd order and higher order modulator

Fig.4: Block diagram of a 2nd order modulator

3-level and higher quantizer

Quantization theory formulas

, the quantization noise in the desired signal bandwidth can be

Circuit realizations of current mirrors

Basic BJT current mirror

where VT = thermal voltage and IS = reverse saturation current or scale current.

Basic MOSFET current mirror

is approximately a square-root function.

Feedback assisted current mirror

Other current mirrors

References External links

) is directly dependent on the duty cycle D.

Space vector modulation

Direct torque control (DTC)

Audio effects and amplification

The Translinear Principle

is a pre-exponential scaling current,

multiplier to the gate-emitter voltage and

is the thermal voltage

A circuit with a translinear loop

must be 0. In other words, the

Because of the exponential current-voltage relationship, this implies TLP:

Example Translinear Circuits

A TL squaring circuit using an alternating TL loop

. This means that

is the unit scaling current (ie . This particular circuit is

A TL squaring circuit using a stacked TL loop

values into the original equation yields

Article Sources and Contributors

Article Sources and Contributors

Image Sources, Licenses and Contributors

Image Sources, Licenses and Contributors

Você também pode gostar