Analysis, Comparison and Application of Vedic Multipliers

ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS
Figure 4.15 8-Bit Vedic Multiplier (8V) Design using Urdhva Tiryakbhyam Sutra 4.3.4 16- bit Vedic Multiplier Design The design of 16-bit Vedic Multiplier is structurally symmetrical to that of the 8-bit Vedic Multiplier. The black box view for the 16x16 Vedic Multiplier is shown in the fig 4.15.
A[15:0] 16 x 16 VEDIC B[15:0] MULTIPLIER R [31:0]
Figure 4.15
Black Box view of 16-bit Vedic Multiplier
Department of ECE, SITAMS
Page 1
The sixteen bit inputs A and B are divided into two equal groups of size 8-bit .Let A be divided into groups GA1 and GA2 and B is divided into GB1 and GB2. A=A[15:0] : GA1=A[7:0] ; GA2=A[15:8] B=B[15:0] : GB1=B[7:0] ; GB2=B[15:8] The output is a 32-bit result which is represented by R=R[31:0]. The basic building block of 16V Multiplier is 8V Multiplier. In order to get four partial products of 16-bit length four 8V Multiplier are used .since the group size is eight the first eight least significant bits in the first and second stage multiplication stages are considered to be the resultant bits remaining bits are obtained at the final stage. Let P1 ,P2, P3 and P4 be the four ,16-bit partial products. Their summation to obtained to produce the final result R is illustrated in the below Fig.4.16. 1.P1= P1 [15:0] & P2=P2[15:0] 2. P3=P3 [15:0] & P4=P4[15:0]
P4[15:8] P4[7:0] + + + R[31:16] P3[15:8] P3[7:0] P2[15:8] P2[7:0] P1[15:8] P1[7:0] R[15:8] R[7:0]
Figure 4.16 Partial product summation for 16-bit Vedic Multiplier In the design of 16V to sum all these eight bit partial products three 16-bit RCA s are required. BelowFig.4.17 illustrates the 16V Vedic Multiplier design.
Page 2
Figure4.17
Design of 16- bit Vedic Multiplier (16 V) based on Urdhva Tiryakbhyam
4.4 ATTRIBUTES OF VEDIC MULTIPLIER BASED ON URDHVA TIRYAKBHYAM SUTRA 1. The design is based on Vedic method of multiplication which reduces N-bit (N=2n where n= 0,1,2,3...) binary multiplication to four N/2-bit Multiplications. 2. Every N/2 bit multiplication can be further reduced to 2x2-bit multiplication thus making a design thus making the design of the multiplier regular which means hierarchical decomposition of a large system results in not only simple, but also similar blocks, as much as possible. 3. Any N x N (N=2n where n= 0,1,2,3...) bit Multiplier design can be done using a 2-bit RCA (Ripple Carry Adder) and 2x2 bit array multiplier as building blocks thus making a hierarchal multiplier design.
Page 3
4. As the design is hierarchal in structure it reduces the design complexity and exploits modularity which means that the various functional blocks which make up the larger system must have well-defined functions and interfaces.. The concept of modularity enables the parallelisation of the design process. It also allows the use of generic modules in various designs - the well-defined functionality and signal interface allow plug-and-play design. 5. For any N x N-bit multiplication the result is obtained in three stages of multiplication by using only four partial products of N-bit length. 4.5 MODIFIED BASE ALGORITHM USING NIKHILAM SUTRA
To analyze Vedic Multiplier based on Nikhilam Sutra it is important to know how Nikhilam Sutra can be applied to the binary information. The logic behind the sutra can be understood by the following algebraic expression. A x B = = (X-a)(X-b)= X( (X-a )+(X-b) X) +a x b Where A and B are multiplicand and Multiplier. a and b are compliments of A and B which are expressed as a= X-A & b= X-B where X is the base for the numbers A and B In decimal number system the base X is considered to be 10
n
eq. 4.11
.The value of n
depends on number of digits in the decimal number system, following the same idea of Nikhilam Sutra for a binary number the base X is considered to be 2 .Where n value depends on size of the input date. When X=2 then a= 2 - A and b= 2 - B Now a and b are the 2s compliment forms of A and B now remaining process of multiplication is same to that of in decimal number system.
n n n n
Page 4
A modified base algorithm for 16x16 bit binary multiplication by Nikhilam Sutra is shown below 1. Consider A=A[15:0] & B=B[15:0] then base is 216(here n=16 size of the inputs). 2. Perform 2s compliment of A i.e. a = 216- A. 3. Perform 2s compliment of B i.e. =2n-B here n=16 (number of bits). 4. LHS part of the result = a x b. 5. RHS part of the result = (A-b) or (B-a). 6. Result for all numbers = 2n x LHS+RHS. 7. Results for large number multiplication= {LHS, RHS}. Nikhilam Sutra is well suitable for large number multiplication (both multiplicand and Multiplier should be large numbers) because as the number becomes larger their compliment values get reduced to small numbers than the original numbers. Below example gives clear cut idea how Nikhilam Sutra reduces large number multiplication to small number multiplication. Eg.1 Let A= 1111_1111_1000_0000 and B= 1111_1111_1000_0000 2s compliment of A (a) = 0000_0000_1000_0000 2s compliment of B (b) = 0000_0000_1000_0000 From the two compliment result we can understand that for all the numbers above than A and B values the compliment size is 8-bit only. Now RHS= a x b = 0000_0000_1000_0000 X0000_0000_1000_0000 = 0100_0000_0000_0000 LHS= A-b = 1111_1111_1000_0000 - 0000_0000_1000_0000 = 1111_1111_0000_0000
Page 5
LHS can be obtained by just adding A+ B because when 2s compliment subtraction is performed the 2s compliment of b again becomes B only so instead of subtraction, addition can be used. Now the total answer is {LHS, RHS}= 1111_1111_0000_0000_0100_0000_0000_0000 If both the Multiplier and multiplicand are not nearer to the base then step 6 must be followed to get the final result. In this case for the numbers ranging from 65,408 to 65535 (max. Value of 16 bit data) only one eight bit multiplication and one addition is enough to get the total result. It can be understood that designing a Multiplier based on Nikhilam Sutra is a special case Multiplier only suitable for large numbers. 4.6 16-BIT VEDIC MULTIPLIER DESIGN USING NIKHILAM SUTRA The 16-bit Nikhilam based Multiplier is designed for the multiplication of numbers ranging from 65,408 to 65535 to show the advantage of using Nikhilam sutra for large number multiplication. The black box view of the Multiplier is shown in below Fig.4.18.
A[15:0] 16 x 16 B[15:0] VEDICMULTIPLIER R[31:0]
Figure 4.18
Black box view of 16-bit Vedic Multiplier
There are three ports namely, data input A, data input B and data output R. The representation has four ports: 1) A[15:0] : It is the first input of Vedic Multiplier.
Page 6
2) B[15:0] : It is the second input of Vedic Multiplier. 3) R[31:0] : It is the output of Vedic Multiplier. Following the modified base algorithm of Nikhilam Sutra a 16-bit Vedic Multiplier is designed as shown in the Fig.4.19 .For the numbers ranging from 65,408 to 65,535 which requires only one 8-bit Multiplication and 2s complement of first 8-bits starting from LSB for both the inputs. Below Fig.4.19 illustrates the implementation of Vedic Multiplier based on Nikhilam Sutra (for 8-bit multiplication 8V is used).
Figure 4.19 Implementation of 16-bit Vedic Multiplier based on Nikhilam Sutra
Page 7
4.7
ATTRIBUTES OF THE VEDIC MULTIPLIER BASED ON NIKHILAM
SUTRA 1. Multiplier designed based on the Nikhilam Sutra is efficient when large number multiplication is involved. 2. Using very less components in the design the Multiplier outperforms Vedic Multiplier based on Urdhva Tiryakbhyam Sutra for large numbers using just an 8x8 multiplication. 3 The sequence of 1s in MSB of both Multiplier and multiplicand will decided the size of the Multiplier block. 4. The most significant part and least significant part of the results are obtained independently because of this, the Multiplier delay will be reduced to a very large extent.
Page 8
CHAPTER -5 ARRAY & MODIFIED BOOTH MULTIPLIERS
This chapter gives attention toward the Array and Modified Booth Multipliers. Algorithm and design of the Array and Modified Booth Multipliers are presented in detail. 5.1 ALGORITHM OF ARRAY MULTIPLIER
The Algorithm used by Array Multiplier is shift and add methodology i.e. the basic procedure for multiplying two numbers. The algorithm is illustrated in the Fig. 5.1 by considering a 4 x 4 bits binary multiplication [2]. Let A= A[3:0] and B=B[3:0] and their product R =R[7:0]=A x B A[3] A[2] A[1] A[0] X B[3] B[2] B[1] B[0] A[3]B[0] A[2]B[0] A[1]B[0] A[0]B[0] A[3]B[1] A[2]B[1] A[1]B[1] A[0]B[1] A[3]B[2] A[2]B[2] A[1]B[2] A[0]B[2] A[3]B[3] A[2]B[3] A[1]B[3] A[0]B[3] R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0]
Figure 5.1 4x4-bit multiplication using add and shift methodology Every bit of the Multiplier is multiplied with the multiplicand .every row of partial product is formed by the multiplication of each bit of the Multiplier with the multiplicand one by one and the addition of these partial products is performed by shifting the next partial product one position left than the previous partial product and summing them gives the final result.
Page 9
5.2
DESIGN OF THE ARRAY MULTIPLIER
1. The Array Multiplier can be designed by using only two types of components they are I.AND gates: Used for the generation of the partial product elements in the partial products II .ADDERS (Half adder & Full adder): Array of adders is used for the addition of the partial product elements to get the final result. 2. The structure of the array Multiplier looks similar to that of the arrangement of the partial products in the basic multiplication process for example design for an 4 x4 array Multiplier is shown below in fig 5.2.(based on Fig. 5.1). P0[3] P1[2] P1[1] P0[2] P1[0] P0[1]
F A
P1[3] P2[1]
F A
P2[0]
H A
A0 B0
F A
P2[3] P2[2]
F A
P3[0]
H A
F A
F A
H A
P3[3]
F A
R7 R6
P3[2]
F A
R5
P3[1]
H A
R4 R3 R2 R1 R0
Figure 5.2 Design of the 4 x4-bit Array Multiplier

In the circuit diagram P0, P1, P2 and P3 represents the partial product terms formed by the AND gates (there are not shown in Fig.5.2) .The elements of partial
Page 10

Analysis, Comparison and Application of Vedic Multipliers

Enviado por

Dados do documento

Descrição original:

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Analysis, Comparison and Application of Vedic Multipliers

Enviado por

Direitos autorais:

Formatos disponíveis

ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS

A[15:0] 16 x 16 VEDIC B[15:0] MULTIPLIER R [31:0]

Black Box view of 16-bit Vedic Multiplier

Department of ECE, SITAMS