Window Discriminator

TCA 965 B

Preliminary Features
q

Bipolar IC

q q q

Two window settings direct setting of lower and upper edge voltage (window edges) indirect setting by window center voltage and half window width Adjustable hysteresis Digital outputs with open collectors for currents up to 50 mA Adjustable reference voltage VStab

P-DIP-14-1

Type s TCA 965 B s Not for new design

Ordering Code Q67000-A8338

Package P-DIP-14-1

The window discriminator compares an input voltage to a defined voltage window. The digital outputs show whether the input voltage is below, within or above this window. The TCA 965 B window discriminator is especially suitable as a tracking or compensating controller with a dead band in control engineering and for the selection of DC voltages within a certain tolerance of the required setpoint value in measurement engineering. When it is used as a Schmitt trigger, switching frequencies up to a typical value of 50 kHz are possible.

Semiconductor Group

1998-02-10

TCA 965 B

Functional Description Amplifier Amp 3 increases the voltage of the reference source R to VStab = 2 x VREF. The amplification factor can be altered by external wiring. With direct setting of the window, the input voltage appears on amplifier Amp 1 (V8), the upper edge voltage on comparator K2 (V6) and the lower edge voltage on comparator K1 (V7). With indirect setting of the window, the input voltage appears on inputs V6 and V7, while the center voltage is connected to amplifier A1 (V8). The voltage applied to the input (V9) of amplifier Amp 2 is subtracted symmetrically from the output voltage of amplifier Amp 1 and added. The comparators switch with hysteresis. The logic gates have open-collector outputs. If the inhibit input A or B is connected to ground, output A or B will always be high.

+ VS 11 1

VREF
5

20 k

20 k

Amp 3

10

V7

7 _ +

+ _ K1

Amp 1

V8

8
1

V=1 12 Amp 2 _

V9 V6

9 6 V=1

+ _ K2

Outputs A, B, C, D are open-collector

Block Diagram Semiconductor Group 2 1998-02-10

VStab

4
_ <1

Inhibit A

13

Inhibit B

+
1

14

IEB00091

TCA 965 B

Pin Configuration (top view)

TCA 965 B
GND A D Inhibit A 1 2 3 4 5 6 7 14 13 12 11 10 9 8
IEP00292

B C Inhibit B +V S

V REF V6 V7

V Stab V9 V8

Pin Definitions and Functions Pin Symbol Direct Setting of Window 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND A D Inhibit A GND Logic output A Logic output D = A @ B (AND) Connected to GND: logic output A = HIGH Internal VREF = 3 V Upper edge voltage Lower edge voltage Input voltage GND Input voltage V6/7 Input voltage V6/7 Center voltage Half window width Pin Function in Indirect Setting

VREF V6 V7 V8 V9 VStab + VS
Inhibit B C B

Internal VStab = 6 V Supply voltage Connected to GND: logic output B = HIGH Logic output C = A @ B (NAND) Logic output B 3 1998-02-10

Semiconductor Group

TCA 965 B

Absolute Maximum Ratings Maximum ratings for ambient temperature TA = 25 to 85 C Parameter Symbol Limit Values min. Supply voltage (pin 11) Difference in input voltage between pins 6, 7, 8 Input voltage (pins 6, 7, 8, 9) Output current (pins 2, 3, 13, 14) Output voltage (pins 2, 3, 13, 14) independent of VS Voltage on VREF (pin 5) Output current of stabilized voltage (pin 10) Inhibit input voltage (pins 4, 12) Junction temperature Storage temperature Thermal resistance system - air Operating Range Supply voltage Ambient temperature P-DIP-14-1 max. 30 15 30 50 30 8 10 7 150 125 80 V V V mA V V mA V C C K/W Unit

VS VI VI IQ VQ VR I10 VIH Tj Tstg Rth SA

55

VS TA

4.5 25

30 85

V C

Semiconductor Group

1998-02-10

TCA 965 B

Characteristics VS = 10 V; TA = 25 C Parameter Symbol Limit Values min. typ. max. Current consumption Input current (pins 6, 7, 8) Input current, pin 9 Input offset voltage in direct setting of window Input offset voltage in indirect setting of window Input-voltage range on pins 6, 7, 8 Input-voltage range on pin 9 Differential input voltage Unit Test Condition Test Circuit 1 1 1 1 2 VI < 13 V 1 2

IS II
II

20 50 1.5 50

mA

V2, V13 = VQH

nA 50 20 400 3000 nA 20 50 mV mV

VIO VIO VI VI
V6 (V8 V9) (V8 + V9) V7

VS 1 V VS/2 13 13
3 6 0.4 3.2 6.5 mV V V V

Reference voltage Stabilized voltage on pin 10 TC of reference voltage Sensitivity of reference voltage to supply-voltage variation Output reverse current

V5 V10 V5
V5/VS

2.8 5.5

IREF = 0

V VS > 7.9 V mV/K

2 10

mV/V A mV mV mV V A kHz kHz 1 2

IQH

Output saturation voltage VQL Hysteresis of window edges Inhibit threshold Inhibit current Switching frequency

100 200 500 800 18 1 22 35 1.8

IQ = 10 mA 1 IQ = 50 mA

VU VL V4, 12 I4, 12 fdir find

100 20 50

Semiconductor Group

1998-02-10

TCA 965 B

VS

S11 11 6
6 2 3

RL

RL

RL

RL

QH2 QH3 QH13 QH14

13 7

TCA 965B

14 10

V6

V7

V8

9 9

12

V5

V10

VQL14

VQL13

VQL3

VQL2

IES00086

V4

V12

Test Circuit 1 Direct Setting of Window

Semiconductor Group

1998-02-10

TCA 965 B

VS

S11 11
6 2 3 7

RL

RL

RL

RL

QH2 QH3 QH13 QH14

13

TCA 965B
8

14 10

=
V6/7

V8

V9

12

V5

V10

VQL14

VQL13

VQL3

VQL2

IES00087

V4

V12

Test Circuit 2 Indirect Setting of Window by Center Voltage and Half Window Width

Semiconductor Group

1998-02-10

TCA 965 B

Inhibit Inputs 4,12

VS V4,12
100 1 k GND >7V open > 1.8 V Outputs A, B

V4,12

High Not permitted Normal function Low

Inputs 6, 7, 8

Input 9

V6,7,8

1 k

V9

Outputs VREF , VStab Outputs 2, 3, 13, 14

VStab R VREF
Q

IES00088

Schematic Circuit Diagrams

Semiconductor Group

1998-02-10

TCA 965 B

VS C1 R1
10 11

R4

6 V 6

R2

TCA 965 B
R5 C2 R6 V C3 R3 V9
9 1 4 12 8 V 8 14 B 7 V 7 13 C

R7

IES00294

To increase the switching frequency, pin 9 may be grounded via R 7 ( V9 approx. 30...40 mV).

Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages

V6 V9 = Upper edge voltage V7 + V9 = Lower edge voltage V8 = Input voltage

Semiconductor Group

1998-02-10

TCA 965 B

V10

VL

VU V7

t
IES00296

Definition of the Offset Voltage VIO

VL + VU V 10 = --------------------- V 7
2

Semiconductor Group

10

1998-02-10

TCA 965 B

V8
Upper Edge Lower Edge

V6

V7 t
L

A B C

D Inhibit A Pin 4 on GND A B 1 0 A B C C D D Inhibit B Pin 12 on GND A B C A 1 0 B C 1 0 1 0 1 0

IES00295

1.8 V < Pin

4<7V 1 0

1 0 1 0

1.8 V < Pin

12 < 7 V

Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages Semiconductor Group 11 1998-02-10

TCA 965 B

VS C1
10 11

R1

R3

C2

R5

8 V 8

R6

9 V 9

TCA 965 B
R7 V C3
7 V 7 14 B 6 V 6 13 C

12

R2

R4

IES00297

Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V

V6 = V7 = Input voltage V8 = Center voltage V9 = Half window width

Semiconductor Group

12

1998-02-10

TCA 965 B

V10

VL

VU V8 - V9

V10 =

VL - VU
2

- (V 8 - V 9 )

IES00299

Definition of the Offset Voltage VIO

VL + VU V 10 = --------------------- ( V 8 V 9 )
2

Semiconductor Group

13

1998-02-10

TCA 965 B

V8
Upper Edge Lower Edge

V6

V7 t
A
L

B C

D Inhibit A Pin 4 on GND A B B C C D D Inhibit B Pin 12 on GND A B 1 0 A 1 0 1 0 1 0 1.8 V < Pin 12 < 7 V 1 0 1 0 1 0 A 1.8 V < Pin 4<7V 1 0

B C

C D D

IED00298

Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V Semiconductor Group 14 1998-02-10

TCA 965 B

VS
10 11 13 6 14 2

RL

RL

RL

R1

V R2

TCA 965B
7 3 9

R4

R3

P = R5

V3

VH V8
0

VH V7 V6
IES00089

Application Circuit 3 Symmetrically Enlarged Edge Hysteresis in Direct Setting of Window Calculation of Hysteresis VH

R5 V H = V 10 ------------------R4 + R5
10 ------------------ + -------------------------------- 10 mA R4 + R5 R1 + R2 + R3

V 10

Semiconductor Group

15

1998-02-10

TCA 965 B

VS RL
2 8 14 13

10

11

RL

RL

R1

6 7

TCA 965B

R5
9

R3

R2

R4

V3

V9/1 V9/2 V8
0

VH = V9/2 - V9/1 V6/7

IES00090

Application Circuit 4 Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window Calculation of Hysteresis VH

VH = V9/2 V9/1 R 4 || R 5 V 9/1 = V 10 ------------------------------R 3 + R 4 || R 5 R4 V 9/2 = V 10 ------------------R3 + R4

Semiconductor Group

16

1998-02-10

TCA 965 B

P-DIP-14-1 (Plastic Dual In-line Package)

Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information.

Dimensions in mm

Semiconductor Group

17

1998-02-10

GPD05005

This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.