VHDL LAB ASSIGNMENT (1) DESIGN A HALF ADDER Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.

ALL; Entity half adder is Port (a: in std_logic; b : in std_logic; s : out std_logic; c : out std_logic); end halfadder; architecture Behavioral of halfadder is begin pro1: process(a,b) begin if(a/=b)then s<='1'; else s<='0'; end if; end process pro1; pro2:process(a,b) begin if (a='1'and b='1') then c<='1'; else c<='0'; end if; end process pro2; end Behavioral;

(2) DESIGN A FULLADDER(1 BIT) Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity fullfadder is Port (a: in std_logic; b : in std_logic; cin :in std_logic; s : out std_logic; cout : out std_logic); end fulladder; architecture Behavioral of fulladder is begin s<= (a xor b) xor cin; cout<= (a and b) or (a xor b)and cin end Behavioral; (3) DESIGN A FULL ADDER USING TWO HALF ADDER AND ONE EXTERNAL GATE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity fulladder1 is Port ( x : in std_logic_vector(1 downto 0); sum,carry : out std_logic; c : in std_logic);

end fulladder1; architecture struct of fulladder1 is signal s_w: std_logic_vector(2 downto 0); signal c_w: std_logic_vector(1 downto 0); component halfadder is port(a,b: in std_logic; c,s:out std_logic); end component; begin halfadder(0):halfadder port map(s_w(0),x(0),c_w(0),s_w(1)); halfadder(1):halfadder port map (a=>s_w(1),b=>x(1),c=>c_w(1),s=>s_w(2)); s_w(0)<=cin; sum<=s_w(2); carry<=c_w(1) or c_w(0); end Behavioral; (4)DESIGN A 4 BIT RIPPLE CARRY ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity carryadder_4 is port(a,b : std_logic_vector(3 down to 0); cin: std_logic; cout:std_logic_vector(3 down to 0); s: std_logic_vector(3 down to 0)); end carryadder_4; architecture struct of carryadder_4 is signal c_I: std_logic_vector(4 down to 0); component fulladder is port(a,b.cin : in std_logic; s,cout:out_logic;) end component; begin addlebel:for k in 3 down 0 generate; fulladder(k):fulladder port map(a(k),b(k),s(k),c_I(k),c_I (k+1)); end generate; cout<=c_I (4); cin<=c_I (0); end struct; (5)DESIGN A CARRY LOOK AHEAD ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity fa_n is generic(n:integer:=4); port(a,b : std_logic_vector(n-1 down to 0); cin: std_logic; cout:std_logic; s:out std_logic_logic_vector(n-1 down to 0);) end fa_n; architecture behv of fa_n is signal result :std_logic_vector(n down to 0); sigmal cin_s: std_logic_vector(n-1 down to 0); begin cin_s<=(others=>0); result<=((0& a)+(0& b)+(cin_s&cin)); cout<=result(n); s<=result((n-1)down to 0); end behv;

(6)DESIGN A FULL SUBTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity sub is port(a,b :in std_logic_vector(7 down to 0); res:out std_logic_vector(7 down to 0); car: out std_logic;) end sub; architecture df of sub is signal result:std_logic_vector(8 down to 0); begin result<=(0& a)-(0& b); res<=result(7 down to 0); car<=result; end behv; (7)DESIGN A 4 BIT ADDER SUBTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity sub is port(a,b :in std_logic_vector(3 down to 0); res:out std_logic_vector(3 down to 0); car: out std_logic;) end sub; architecture df of sub is signal result:std_logic_vector(8 down to 0); begin result<=(0& a)+(0&(not b)); res<=result(3 down to 0); car<=result; end behv;

(8)DESIGN A BCD ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); s : out std_logic_vector(4 downto 0)); end bcd; architecture Behavioral of bcd is signal p:std_logic_vector(4 downto 0); signal adjust:std_logic; begin p<=('0'& a)+b; adjust<='1'when p>9 else'0'; s<=p when(adjust='0')else p+6; end Behavioral; (9)DESIGN A MAGNITUDE COMPAPARATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( a : in std_logic_vector(1 downto 0); b : in std_logic_vector(1 downto 0); x : out std_logic; y : out std_logic; z : out std_logic); end comp; architecture Behavioral of comp is begin x<='1'when a=b else '0'; y<='1'when a<b else '0'; z<='1'when a>b else '0'; end Behavioral;

(10)CODE CONVERSION a. BINARY TO GRAY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bg is Port ( bin : in std_logic_vector(3 downto 0); gra : out std_logic_vector(3 downto 0)); end bg; architecture Behavioral of bg is begin process(bin) begin case bin is when"0000"=>gra<="0000"; when"0001"=>gra<="0001"; when"0010"=>gra<="0011"; when"0011"=>gra<="0010"; when"0100"=>gra<="0110"; when"0101"=>gra<="0111"; when"0110"=>gra<="0101"; when"0111"=>gra<="0100"; when"1000"=>gra<="1100"; when"1001"=>gra<="1101"; when"1010"=>gra<="1111"; when"1011"=>gra<="1110"; when"1100"=>gra<="1010"; when"1101"=>gra<="1011"; when"1110"=>gra<="1001"; when"1111"=>gra<="1000"; when others=>null; end case; end process; end Behavioral;

GRAY TO BINARY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gb is Port ( gra : in std_logic_vector(3 downto 0); bin : out std_logic_vector(3 downto 0)); end gb; architecture Behavioral of gb is begin process(gra) begin case gra is when"0000"=>bin<="0000"; when"0001"=>bin<="0001"; when"0010"=>bin<="0011"; when"0011"=>bin<="0010"; when"0100"=>bin<="0111"; when"0101"=>bin<="0110"; when"0110"=>bin<="0100"; when"0111"=>bin<="0101"; when"1000"=>bin<="1111"; when"1001"=>bin<="1110"; when"1010"=>bin<="1100"; when"1011"=>bin<="1101"; when"1100"=>bin<="1000"; when"1101"=>bin<="1011"; when"1110"=>bin<="1001"; when"1111"=>bin<="1010"; when others=>null; end case; end process; end Behavioral; B DECIMAL TO EXCESS-3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity b_excess3 is Port ( bin : in std_logic_vector(3 downto 0); excess3 : out std_logic_vector(3 downto 0)); end b_excess3; architecture Behavioral of b_excess3 is begin process(bin) begin case bin is when"0000"=>excess3<="0011"; when"0001"=>excess3<="0100"; when"0010"=>excess3<="0101"; when"0011"=>excess3<="0110"; when"0100"=>excess3<="0111"; when"0101"=>excess3<="1000"; when"0110"=>excess3<="1001"; when"0111"=>excess3<="1001"; when"1000"=>excess3<="1011"; when"1001"=>excess3<="1100"; when others=>null; end case; end process; end Behavioral; EXCESS-3 TO DECIMAL library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity excess3_b is Port ( excess3 : in std_logic_vector(3 downto 0); excess3 : out std_logic_vector(3 downto 0)); end excess3_b; architecture Behavioral of excess_3is begin process(excess3) begin case bin is when"0011"=>excess3<="0011"; when"0100"=>excess3<="0100"; when"0101"=>excess3<="0101"; when"0110"=>excess3<="0110"; when"0111"=>excess3<="0111"; when"1000"=>excess3<="1000"; when"1001"=>excess3<="1001"; when"1010"=>excess3<="1010"; when"1011"=>excess3<="1011"; when"1100"=>excess3<="1100"; when others=>null; end case; end process; end Behavioral; c.BCD TO SEVEN SEGMENT DISPLAY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity seg7 is Port ( bcd : in std_logic_vector(3 downto 0); leds : out std_logic_vector(7 downto 1)); end seg7; architecture Behavioral of seg7 is begin process(bcd) begin case bcd is when"0000"=>leds<="1111110"; when"0001"=>leds<="0110000"; when"0010"=>leds<="1101101"; when"0011"=>leds<="1111001"; when"0100"=>leds<="0110011"; when"0101"=>leds<="1011011"; when"0110"=>leds<="1011111"; when"0111"=>leds<="1110000"; when"1000"=>leds<="1111111"; when"1001"=>leds<="1111011"; when others=>null; end case; end process; end Behavioral; (11) DESIGN A 2:1,4:1,8:1 MUX 2:1 MULTIPLEXER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_2_1 is Port ( i0 : in std_logic; i1 : in std_logic; s : in std_logic; f : out std_logic); end mux_2_1; architecture Behavioral of mux_2_1 is begin process(i0,i1) begin case s is when '0'=>f<=i0; when '1'=>f<=i1; when others=>null; end case; end process; end Behavioral; 4:1 MULTIPLEXER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_4_1 is Port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; s : in std_logic_vector(1 downto 0); f : out std_logic); end mux_4_1; architecture Behavioral of mux_4_1 is begin with s select f<=i0 when "00", i1 when "01", i2 when "10", i3 when others; end Behavioral; 8:1 MULTIPLEXER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_8_1 is Port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; i4 : in std_logic; i5 : in std_logic; i6 : in std_logic; i7 : in std_logic; s : in std_logic_vector(2 downto 0); f : out std_logic); end mux_8_1; architecture Behavioral of mux_8_1 is begin with s select f<=i0 when "000",

i1 when "001", i2 when "010", i3 when "011", i4 when "100", i5 when "101", i6 when "110", i7 when others; (12)DESIGN A 32:1 MUX USING MUX TREE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux32_1 is Port ( i : in std_logic_vector(31 downto 0); s : in std_logic_vector(4 downto 0); f : out std_logic); end mux32_1; architecture Behavioral of mux32_1 is signal p:std_logic_vector(3 downto 0); component mux_8_1 is Port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; i4 : in std_logic; i5 : in std_logic; i6 : in std_logic; i7 : in std_logic; s : in std_logic_vector(2 downto 0); f : out std_logic); end component; component mux_4_1 is Port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; s : in std_logic_vector(1 downto 0); f : out std_logic); end component; begin GK:for k in 0 to 3 generate mux_k:mux_8_1 port map(i(8*k),i(8*k+1),i(8*k+2),i(8*k+3),i(8*k+4),i(8*k+5),i(8*k+6),i(8*k+7),s(2 downto 0),p(k)); end generate; MUX_5:mux_4_1 port map(p(0),p(1),p(2),p(3),s(4 downto 3),f);end Behavioral; (14)DESIGN A 3:8,2:4,4:16 DECODER 3:8 DECODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec_3_8 is Port ( s : in std_logic_vector(2 downto 0); z : out std_logic_vector(7 downto 0)); end dec_3_8; architecture Behavioral of dec_3_8 is begin process(s) begin if(s="000")then z<="00000001"; elsif(s="001")then z<="00000010"; elsif(s="010")then z<="00000100";

elsif(s="011")then z<="00001000"; elsif(s="100")then z<="00010000"; elsif(s="101")then z<="00100000"; elsif(s="110")then z<="01000000"; else z<="10000000"; end if; end process; end Behavioral; 2:4 DECODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec_2_4 is Port ( s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end dec_2_4; architecture Behavioral of dec_2_4 is begin process(s) begin if (s="00")then z<= "0001"; elsif (s="01")then z<="0010"; elsif (s="10")then z<="0100"; else z<="1000"; end if; end process; end Behavioral; 4:16 DECODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec_4_16 is Port ( s : in std_logic_vector(3 downto 0); z : out std_logic_vector(15 downto 0)); end dec_4_16; architecture Behavioral of dec_4_16 is begin process(s) begin if(s="0000")then z<="0000000000000001"; elsif(s="0001")then z<="0000000000000010"; elsif(s="0010")then z<="0000000000000100"; elsif(s="0011")then z<="0000000000001000"; elsif(s="0100")then z<="0000000000010000"; elsif(s="0101")then z<="0000000000100000"; elsif(s="0110")then z<="0000000001000000"; elsif(s="0111")then z<="0000000010000000"; elsif(s="1000")then z<="0000000100000000"; elsif(s="1001")then z<="0000001000000000"; elsif(s="1010")then z<="0000010000000000"; elsif(s="1011")then z<="0000100000000000"; elsif(s="1100")then z<="0001000000000000"; elsif(s="1101")then z<="0010000000000000"; elsif(s="1110")then z<="0100000000000000"; else z<="1000000000000000"; end if; end process; end behv;

(15)DESIGN A 3:8 DECODER USING 2:4 DECODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity dec3_8usingdec2_4 is Port ( w0,w1 : in std_logic; w2: in std_logic; En: in std_logic; y : out std_logic_vector(7 downto 0)); end dec3_8usingdec2_4 ; architecture struct of dec3_8usingdec2_4 is component dec2_4(1) is port(w0,w1: in std_logic; En: in std_logic; y : out std_logic_vector(3 downto 0)); end component; component dec2_4(2) is port(w0,w1: in std_logic; En: in std_logic; y : out std_logic_vector(7 downto 4)); end component; begin dec2_4(1) : dec2_4(1) portmap (w(0),w(1),((not w2) and '1'),y( 3 downto 0)); dec2_4(2) : dec2_4(2) portmap (w(0),w(1),( w2 and '1'),y( 7 downto 4)); end struct; (16)DESIGN 1:2, 1:4 DEMUX 1:2 DEMUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux 1_2 is port(s:in std_logic; p:in std_logic; do,d1:out std_logic;) end dmux 1_2; architecture behv of dmux 1_2 is begin process(s) variable sbar:std_logic; begin sbar:=not s; d0:sbar and p; d1:s and p; end process; end behv; 1:4 DEMUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux 1_4 is port(s0,S1:in std_logic;

p:in std_logic; do,d1D2,D3:out std_logic;) end dmux 1_4; architecture behv of dmux 1_4 is process(s) variable sbar(0):std_logic; vriable sbar(1):std_logic; begin sbar(0):not so; sbar(1):not s1; d0:sbar(1)and sbar(0)and p; d1:sbar(1)and so and p; d2:sbar(0)and s1 and p; d3:s1 and s0 and p; end process; end behv;

(17)DESIGN A PRIORITY ENCODER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prio_en is port(I:in std_logic_vector(3 down to 0); y:out std_logic_vector(1 down to 0); z:out std_logic;) end prio_en; architecture behv of prio_en is begin y<=11 when I(3)=1else 10 when I(2)=1else 01 when I(1)=1else 00 z<=0when I =0000 else 1 end behv; (18)DESIGN SR,JK,D,T FLIPFLOPS SR FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr is port(r,s,clk:in std_logic_vector; q,qbar:inout std_logic;) end sr; architecture behv of sr is signal s1,s2 :std_logic; begin wait until(clk=1 and clkevent) s1<=r; s2<=s; q<=qbar nor s1; qbar<=s2 nor q;

end behv;
JK FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jk is port(r,s,clk:in std_logic_vector; q,qbar:inout std_logic;) end jk; architecture behv of jk is signal s1,s2 :std_logic; begin wait until(clk=1 and clkevent) s1<=j and k; s2<=k and qbar; q<=qbar nor s1; qbar<=s2 nor q; end behv; D FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is port(d,clk:in std_logic_vector; q,qbar: out std_logic;) end dff; architecture behv of dff is begin process(d,clk) variable state:std_logic; begin if(clk=1 and clkevent)then state:=d; end if; q<=state; qbar<=not state; end process; end behv; T FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is port(d,clk:in std_logic_vector; q,qbar: out std_logic;) end tff; architecture behv of tff is begin process(t,clk) variable state:std_logic; begin if(clk=1 and clkevent)then state:=not t; end if; q<=state; qbar<=not state; end process; end behv; (19)DESIGN SR USING OTHER GATE WHICH YOU HAVE NOT USED ABOVE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr is port(r,s,clk:in std_logic_vector; q,qbar:inout std_logic;) end sr; architecture behv of sr is signal s1,s2 :std_logic; begin wait until(clk=1 and clkevent) s1<=not s; s2<=not r; q<=qbar nand s1; qbar<=s2 nand q;

end behv;
(21)DESIGN A D FLIPFLOP USING PRESET & CLEAR PINS Entity DFF_PC is Port ( D, clear, clock : in std_logic ; Q : out std_logic ); End DFF_PC; Architecture behavior of DFF_PC is Begin Process ( clear, clock ) Begin If clear = 0 then Q <=0; Elseif ( clock event and clock = 1)then Q<=D; End if; End process; End behavior;

(22)DESIGN A 4-BIT SHIFT REGISTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reg is port(d:in std_logic_vector(3 down to 0); clk,rst:in std_logic; q: out std_logic_vector(3 down to 0);) end reg; architecture behv of reg is begin process(d,rst,clk) variable state:std_logic_vector(3 down to 0); bgin wait until(clk=1 and clkevent); if(rst=0)then state<=(others=>0); else state<=d; end process; end behv;

(23)DESIGN A PARALLEL ACCESS SHIFT REGISTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reg is port(d:in std_logic; clk,rst:in std_logic; q: out std_logic_vector(7 down to 0);) end sh_reg; architecture behv of sh_reg is begin process(d,clk) variable state :std_logic_vector(7 down to 0):=(oters=>0); begin if(clk=1 and clkevent) state:=state(6 down to 0) & d; end if; q<=state; end process; end behv; (24)DESIGN A UP COUNTER(3 BIT) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uc_3 is Port ( rst : in std_logic; clk : in std_logic; q : out std_logic_vector(2 downto 0)); end uc_3; architecture Behavioral of uc_3 is signal count:std_logic_vector(2 downto 0); begin process(rst,clk) begin if(rst='0')then count<=(others=>'0'); elsif(clk='1'and clk'event)then count<=count+1; end if; end process; q<=count; end Behavioral; (25)DESIGN A DOWN COUNTER(3 BIT) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dc_3 is Port ( rst : in std_logic; clk : in std_logic; q : out std_logic_vector(2 downto 0)); end dc_3; architecture Behavioral of dc_3 is signal count:std_logic_vector(2 downto 0); begin process(rst,clk)

begin if(rst='0')then count<=(others=>'0'); elsif(clk='1'and clk'event)then count<=count-1; end if; end process; q<=count; end Behavioral; (26)DESIGN A SYNCHRONOUS COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is Port ( rst : in std_logic; clk : in std_logic; q : buffer std_logic_vector(1 downto 0)); end counter; architecture Behavioral of counter is begin if(clk=1 and clkevent)then if clear=1then q<=00; else q<=q+1; end if; end if; end process; end behv; (27)DESIGN A MOD2,MOD3,MOD5,MOD10,MOD6 COUNTER A) DESIGN A MOD_2 COUNTER:Entity MOD_2 is Generic (modulus: integer: =2); Port(clock, L, E: in std_logic; Q: out integer range 0 to modulus-1); End MOD_2; Architecture behavior of MOD_2 is Signal Count : integer range 0 to modulus-1; begin process begin wait until ( clock event and clock =1); If E=1 then If L=1 then Count <= modulus-1; Else Count<= Count-1; End if; End if; End process; Q<=Count; End behavior; B) DESIGN A MOD-3 COUNTER:Entity MOD_3 is Generic (modulus: integer: =3); Port(clock, L, E: in std_logic; Q: out integer range 0 to modulus-1); End MOD_3; Architecture behavior of MOD_3 is

Signal Count : integer range 0 to modulus-1; begin process begin wait until ( clock event and clock =1); If E=1 then If L=1 then Count <= modulus-1; Else Count<= Count-1; End if; End if; End process; Q<=Count; End behavior; 27. C) DESIGN A MOD_5 COUNTER:Entity MOD_5 is Generic (modulus: integer: =5); Port(clock, L, E: in std_logic; Q: out integer range 0 to modulus-1); End MOD_5; Architecture behavior of MOD_5 is Signal Count : integer range 0 to modulus-1; begin process begin wait until ( clock event and clock =1); If E=1 then If L=1 then Count <= modulus-1; Else Count<= Count-1; End if; End if; End process; Q<=Count; End behavior; 27. D) DESIGN A MOD_6 COUNTER:Entity MOD_6 is Generic (modulus: integer: =6); Port(clock, L, E: in std_logic; Q: out integer range 0 to modulus-1); End MOD_6; Architecture behavior of MOD_6 is Signal Count : integer range 0 to modulus-1; begin process begin wait until ( clock event and clock =1); If E=1 then If L=1 then Count <= modulus-1; Else Count<= Count-1; End if; End if; End process; Q<=Count; End behavior;

27. E) DESIGN A MOD_10 COUNTER:Entity MOD_10 is Generic (modulus: integer: =10); Port(clock, L, E: in std_logic; Q: out integer range 0 to modulus-1); End MOD_10; Architecture behavior of MOD_10 is Signal Count : integer range 0 to modulus-1; begin process begin wait until ( clock event and clock =1); If E=1 then If L=1 then Count <= modulus-1; Else Count<= Count-1; End if; End if; End process; Q<=Count; End behavior;

(29)DESIGN A ALU library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is Port ( i : in std_logic_vector(2 down to 0); a,b : in std_logic_vector(3 down to 0); f : out std_logic_vector(3 downto 0)); end alu; architecture Behavioral of alu is signal count:std_logic_vector(2 downto 0); begin process(i,a,b) begin case i is when"000"=>f<="0000"; when"001"=>f<="b-a"; when"010"=>f<="a-b"; when"011"=>f<="a+b"; when"100"=>f<="a xor b"; when"101"=>f<="a or b"; when"110"=>f<="a and b"; when others=>f<=1111;

end case; end process; end Behavioral;

(30)DESIGN A 4*3 MULTIPLIER Entity FULL_ADDER is port ( X, Y, Z :in std_logic; S, C : out std_logic ); End FULL_ADDER; Architecture behavior of FULL_ADDER is Begin S<= ( X xor Y ) xor Z; C <= ( X and Y ) or ( X and Z ) or ( Y and Z ); End behavior; Entity GENERIC_FA is Generic (N : NATURAL ); Port (A, B : in std_logic_vector (3 downto 0 ); SUM : out std_logic_vector (3 downto 0 ); COUT: out std_logic); End GENERIC_FA; Architecture behavior of GENERIC_FA is Component FULL_ADDER port ( X, Y, Z :in std_logic; S, C : out std_logic ); End component; Signal CARRY : std_logic_vector ( 4 downto 0 ); Begin CARRY(0) <=0; COUT<= CARRY(N); G1: for K in 0 to 3 generate FA : FULL_ADDER portmap ( X => A(K), Y=> B(K), Z=> CARRY(K), S=> SUM(K), C=> CARRY(K+1)); End generate; End behavior; Entity 4_3_MUTIPLIER is Generic ( 4,3 : positive ); Port (MPLR : in std_logic_vector(3 downto 0); MPCD: in std_logic_vector(2 downto 0); Result : out std_logic_vector(6 downto 0); End 4_3_MUTIPLIER; Architecture behavior of 4_3_MUTIPLIER is Signal ACARRY : std_logic_vector(3 downto 0); Type SUM_TYPE is array ( 3 downto 0 ) of std_logic_vector(2 downto 0); Signal ASUM: SUM_TYPE; Signal OPD1, OPD2 : SUM_TYPE; Signal RES : std_logic_vector(4 downto 0); Function RESIZE ( A: in std_logic ; SIZE: in NATURAL ); Return std_logic_vector is Variable RES : std_logic_vector( SIZE-1 downto 0 ); Begin RES:= (others =>A); Return (RES); End; Component GENERIC_FA Generic (N : NATURAL ); Port (A, B : in std_logic_vector (3 downto 0 ); SUM : out std_logic_vector (3 downto 0 ); COUT: out std_logic); End component; Begin

G2: for K in 1 to 3 generate G3: if K=1 generate ASUM(0)<= RESIZE(MPLR(0),3 ) and MPCD ; RESULT(0)<= ASUM(0)(0); ACARRY(0)<=0; End generate; OPD2(K)<=ACARRY(K-1) & ASUM(K-1) (2 DOWNTO 0 ); OPD1(K)<= RESIZE(MPLR(K),3) and MPCD; GFA: GENERIC_FA Generic MAP ( 4=>3) Port map ( A=> OPD1(K), B=> OPD2(K), SUM=> ASUM(K), COUT=>ACARRY(K)); RESULT(K)<= ASUM(K)(0); End generate; RESULT( 6 downto 2 ) <=ACARRY(3) & ASUM(3)( 2 downto 1 ); End behavior;

THEORY

VARIABLE a) An object of variable class (often called a variable) can also hold a single value of a given type. However, in this case, different values can be assigned to the variable at different times using a variable assignment statement.

b) Variables can be declared and used inside a process statement.

SIGNAL a) An object belonging to the signal class (often called a signal) holds a list of values, which include the current values of the signal, and a set of possible future values that are to appear on the signal. Future values can be assigned to a signal using a signal assignment statement. b) Signals are assigned values using a signed assignment statement witjin a process or outside of a process. c) Signal assignment statement is, Signal-object <= expression[after delay value];

c) Variable assignment statement is variable-object := expression;

BIT VECTOR:It is a vector of bit values (e:g- bit_vector (0 to 7)) . The Range of values of bit_vector is an array with each element of type bit. Example of a bit_vector :Signal IN BUS : bit_vector ( 7 downto 0); GENERIC:Generic declarations are optional and determine the local constants used for timing and sizing (e.g- bus widths) the entity.

RESOLUTION FUNCTION :In VHDL a resolution function is used to determine what value a signal should take if there are two sources for the signal. For the example, if we see the picture given bellow, there are three drivers for signal Z. Each driver has a sequence of transaction defines the value to appear on the signal and the time at which it is to appear. The resolution function resolves the value for the signal Z from the current value of each of its drives.

PIC:-

RESOLVING SIGNAL DRIVERS

The value of each driver is an input to the resolution function and based on the computation performed within the resolution function, the value returned by this function, becomes the resolved value for the signal. The resolution function is user written and may perform any function. The function is not restricted to perform a wired_and or wired_or operation for example, it could be used to count the number of events on a signal. A signal with more than one driver must have a resolution function associated with it; otherwise, it is an error. Such a signal is called a resolved signal. A resolution function is associated with a signal by specifying its name in the signal declaration. For example:Signal BUSY : WIRED_OR BIT; Here is an example of a WIRED_OR function that can be used as a resolution function. Function WIRED_OR (INPUTS: BIT_VECTOR) return BIT is Begin For J in INPUTSRANGE loop If INPUTS(J) = 1then Return 1; End if; End loop; Return 0; End WIRED_OR;