Escolar Documentos
Profissional Documentos
Cultura Documentos
4, APRIL 2008
1871
AbstractThis paper presents a concept for improving the efciency of a pushpull Class-E inverter. The concept consists of lowering the root-mean-square transistor current (in reducing the transistor power losses) only by adding a differential capacitor to a pushpull Class-E topology. Theoretical explanations and conrming experimental results are given. Index TermsClass E, high-frequency (HF) ampliers, inverters, resonant power conversion, zero-voltage switching (ZVS).
I. I NTRODUCTION High-frequency high-efciency resonant inverters are more and more widely used in various applications to generate power ranging from watts to kilowatts at frequencies ranging from a few kilohertz to tens of megahertz, such as induction heating, dielectric heating, and dcacdc conversion. Therefore, problems concerning their properties are still topical and are still the subject of numerous investigations. For instance, new methods of improving the power capabilities and output power control of resonant Class-D, -DE, and -E inverters have been proposed and analyzed in recently published papers [1][4]. The Class-E inverters are capable of converting power at frequencies in the megahertz range with signicantly reduced switching losses of their transistors [5][7]. At the same time, the poor (highly peaked) shape of the voltage and current waveforms of the transistors results in relatively high conduction losses. Consequently, the Class-E inverters have lower efciency and produce less power per transistor than other inverters with the same voltage and current stresses on their transistors. For instance, comparing the Class-D and -E inverters at lower frequencies, the rst one can deliver 75% more output power. In order to improve the shape of the waveforms, some solutions have been recently introduced. The most effective and applicable ones [2], [8] use the Class-E/F and -EF techniques, which consist of inserting additional circuits and proper harmonic tuning. For instance, Class-EF2 and -E/F3 inverters can produce 43% and 24% more output power, respectively, with the same stresses on their transistors than a classic Class-E inverter [2]. Another interesting and simple solution of improving efciency has been proposed in [9]. The only required change is the addition of a differential capacitor to a pushpull Class-E topology. Unfortunately, this concept has not been illustrated with quantitative information and has not been conrmed experimentally. Therefore, the aim of this paper is to give such information and verify this concept experimentally. II. C ONCEPT FOR I MPROVING E FFICIENCY The circuit diagram of the pushpull Class-E inverter is shown in Fig. 1(a) [5], [9], [10]. It can be divided into two classic single-ended
Manuscript received December 6, 2006; revised July 31, 2007. The authors are with the Department of Power Electronics, Electric Drives and Robotics (RE-5), 44-100 Gliwice, Poland (e-mail: zbigniew. kaczmarczyk@polsl.pl; wojciech.jurczak@polsl.pl). Digital Object Identier 10.1109/TIE.2007.907665
ITrms IT
1
VTm VT
ITrms IT
(1)
where n is the number of the transistors (here, n = 2), VTm is the peak transistor voltage, ITrms is the rms transistor current, PI is the input power, PT is the transistor losses, and RDS(on) is the transistor on-resistance. For a higher value of cpmr and the same voltage VTm and current ITrms stresses on the transistors, the output power PO increases. At the same time, the lower the product of VTm /VT
1872
Fig. 1. (a) Improved pushpull Class-E inverter and normalized waveforms for r = 1, 0.75, 0.5, 0.25, 0. (b) Transistor current waveforms. (c) Transistor voltage waveforms. (d) Output current waveforms.
and ITrms /IT , the higher the inverter efciency achieved, as shown in
2 n RDS(on) ITrms PO n PT =1 1 PI VI I I VI I I
=1
(2)
where n, VTm , ITrms , PI , PT , and RDS(on) are dened as those in (1). Neglecting power losses (1), the value of cpmr is approximately equal to 0.180 (r = 1) and 0.196 (r = 0) for Class-E inverters, is equal to 0.32 for Class-D inverters, and increases to 0.35 for the square voltage and current waveforms of the transistor with a duty cycle of 0.5. The representative properties of the pushpull Class-E inverter with improved efciency are presented in Fig. 2 as a function of factor r. The normalized current ITrms /IT and the modied power output capability cpmr change in opposite directions [Fig. 2(a)]. The normalized voltage VTm /VT remains constant (not shown). Fig. 2(b) illustrates the normalized power losses PT /PT (r=1) of each transistor versus r. They were calculated based on the values of ITrms /IT , assuming that the conduction losses dominate the transistor power losses. Two cases were considered. In the rst simpler case (dashed line), the transistor on-resistance RDS(on) was constant. In the second case (shaded area), its typical dependence on temperature for MOSFET transistors was introduced (RDS(on) (Tj )/RDS(on) (Ta ) = 1.0072(T jT a) ),
Fig. 2. (a) Modied power output capability and normalized rms transistor current, (b) normalized power losses, and (c) normalized output power versus r.
1873
taking into account two transistor junction temperatures (Tj(r=1) = 40 C and 120 C) with ambient temperature Ta = 25 C. It is seen that, by connecting the differential capacitor, the transistor power losses can be maximally reduced by 17%32% [Fig. 2(b), r 0]. Another improvement is possible by properly modifying the inverter parameters. For the same power losses PT and the same peak transistor voltage VTm , the inverter output power PO can be increased by 9% [Fig. 2(c), r 0]. This results directly from the denition (1) and the values of cpmr [Fig. 2(a)]. IV. E XPERIMENTAL R ESULT The obtained theoretical results have been veried experimentally for the two cases: 1) r = 1 (the optimum operation, (1 r) C1 is removed) and 2) r = 0.15 (the suboptimum operation, r C1 is only the transistor output capacitance). Two IRF840 MOSFET transistors (500 V, 8 A) were used as the switching devices. Their switching frequency f was 1 MHz, and duty cycle D was adjusted to approximately 0.5. The pushpull Class-E inverter was successfully designed, fabricated, and tested. The parameters of its components were measured by an HP4294A impedance analyzer. The following results were obtained: L11 = 691 H, L12 = 694 H (ferrite core inductors with air gap), RL11 = 24.9 m, RL12 = 27.2 m (dc parasitic resistances), r C1 = 1.10 nF (r = 1, silver mica capacitors and transistor output capacitance), r C1 = 0.16 nF (r = 0.15, transistor output capacitance), (1 r) C1 = 0.94 nF (r = 0.15, silver mica capacitors), C21 = C22 = 1.63 nF (silver mica capacitors), L21 = 19.9 H, L22 = 20.3 H (iron powder core inductors), RL21 = 0.38 , RL22 = 0.40 (ac parasitic resistances at 1 MHz), and R = 50 (500-CT-FN power termination from Bird Electronic Corp.). The equivalent capacitance of the transistor output capacitance was calculated based on the charge needed to charge it to the value of 350 V. The charge was measured experimentally as in [2]. A Tektronix TDS3034B digital oscilloscope with voltage (P6139A) and current (P6022) probes was used for recording voltage and current waveforms. The oscilloscopic waveforms are presented in Fig. 3. For transistor current iT , only its ac component was measured. The waveforms illustrate the optimum operation of the inverter [Fig. 3(a); r = 1, and iT rises slowly] and the suboptimum operation [Fig. 3(b); r = 0.15, and iT rises sharply]. In both cases, the dc supply voltage VI and current II (Table I), and the peak transistor voltage VTm (Fig. 3) remained almost constant. The inverter output power PO(BIRD) (Table I) was continuously monitored with a Bird 43 power meter. In order to obtain accurate readings of the power losses PT 1 and PT 2 of the transistors, the efciency , and the output power PO of the inverter, a thermal method was applied. First, thermocouples were attached to the cases of the transistors. Next, dc power was supplied to the transistors with their gate-source connected to 12 V, and the temperature rises T1 and T2 were recorded in thermal steady state. The measured characteristics PT 1 = f (T1 ) and PT 2 = f (T2 ) were used to determine power losses PT 1 and PT 2 in the laboratory inverter (Table I). Finally, based on PT 1 , PT 2 , VI , II , RL11 , RL12 , RL21 , RL22 , and the rms load current IOrms (measured by the oscilloscope), the input power PI (PI = VI II ), the power losses PL (PL = (RL11 + RL12 ) (II /2)2 + (RL21 + 2 RL22 ) IOrms ) of the inductors, the output power PO (PO = PI PT 1 PT 2 PL ), and the efciency ( = PO /PI ) were calculated (Table I). Connecting the differential capacitor results in decreasing the temperature rises and in decreasing the transistor power losses (Table I). The output power remains approximately constant, and the inverter efciency increases from 92.0% to 93.7%. The ratio between the power
Fig. 3. Experimental waveforms of laboratory inverter for (a) r = 1 and (b) r = 0.15 (vG : gatesource voltage; vT : transistor voltage; iT : transistor current; voltage, current, and time scales: 10 and 100 V/div, 2 A/div, and 200 ns/div, respectively).
losses (PT 1 + PT 2 )(r=0.15) and (PT 1 + PT 2 )(r=1) of the transistors is equal to 0.71, and it is located in the shaded area of Fig. 2(b). The obtained results are in good agreement with the theoretical predictions. Note that in a general case, the efciency improvement of the pushpull Class-E inverter with the differential capacitor always occurs as a result of reducing the power losses. The higher the ratios of the power losses before and after connecting the differential capacitor to the output power (the lower the respective efciencies), the higher the efciency increase for the given reduction in the power losses. V. C ONCLUSION A concept for improving the efciency of pushpull Class-E inverters has been discussed and conrmed experimentally. The best possible improvement is achieved in the case of the highest value of the differential capacitor, i.e., r = 0. The transistor power losses can be then reduced by 17%32%, or alternatively, the inverter output power can be increased by 9% with the same voltage and current stresses on the transistors. However, the lower limit of r increases with increase in the switching frequency due to the transistor output capacitance. It should be noted that nonzero-current switching on of the transistor for r < 1 can lead to additional power losses. Fortunately, the latter problem can be easily overcome by setting the duty cycle a little more than 0.5 (a short interval of conduction of both transistors) [9].
1874
R EFERENCES
[1] J. Matysik, A new method of integration control with instantaneous current monitoring for Class D series resonant converter, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 15641576, Oct. 2006. [2] Z. Kaczmarczyk, High-efciency Class E, EF2 and E/F3 inverters, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 15841593, Oct. 2006. [3] N.-J. Park, D.-Y. Lee, and D.-S. Hyun, A power-control scheme with constant switching frequency in Class-D inverter for induction-heating jar application, IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 12521260, Jun. 2007. [4] H. Koizumi and K. Kurokawa, Analysis of the Class DE inverter with thinned-out driving patterns, IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 11501160, Apr. 2007. [5] F. H. Raab, Idealized operation of the Class E tuned power amplier, IEEE Trans. Circuits Syst., vol. CAS-24, no. 12, pp. 725735, Dec. 1977. [6] M. K. Kazimierczuk, Exact analysis of class E tuned power amplier at any Q and switch duty cycle, IEEE Trans. Circuits Syst., vol. CAS-34, no. 2, pp. 149159, Feb. 1987. [7] N. O. Sokal, Class-E RF power ampliers, QEX, no. 204, pp. 920, Jan./Feb. 2001. [8] S. Kee, I. Aoki, A. Hajimiri, and D. Rutledge, The class E/F family of ZVS switching ampliers, IEEE Trans. Microw. Theory Tech., vol. 51, no. 6, pp. 16771690, Jun. 2003. [9] H. Hu, Y. Li, and Z. Wang, An improved pushpull Class-E RF tuned power amplier with low maximum transistor current, in Proc. 4th Int. Conf. ASIC, 2001, pp. 322325. [10] S. C. Wong and C. K. Tse, Design of symmetrical Class-E power ampliers for very low harmonic-content applications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 16841690, Aug. 2005.
Fig. 1.
High Efciency Active Clamp Forward Converter for Sustaining Power Module of Plasma Display Panel
Tae-Sung Kim, Sang-Kyoo Han, Gun-Woo Moon, and Myung-Joong Youn
AbstractA new high efciency active clamp forward converter for the sustaining power module of a plasma display panel is proposed. It features zero voltage switching, a simpler structure, lower cost, less mass, and no effective duty loss. Furthermore, voltages across all rectier diodes are clamped on the output voltage, which results in higher efciency. Index TermsActive clamp forward (ACF), plasma display panel (PDP), sustaining power module (SPM).
I. I NTRODUCTION The plasma display panel (PDP) is currently one of the leading candidates for large screen TVs due to its desirable merits that include a wide view angle, light weight, thinness, long lifetime, high contrast, and large size [1]. Since the sustaining power module (SPM)
Manuscript received January 23, 2006; revised October 8, 2007. T.-S. Kim, G.-W. Moon, and M.-J. Youn are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: mmyoun@ee.kaist.ac.kr). S.-K. Han is with Kookmin University, Seoul 136-702, Korea. Digital Object Identier 10.1109/TIE.2007.911208
(among various power modules used in the PDP) handles most power requirements at over 85%, it determines the overall system efciency. Therefore, it is necessary to increase the efciency of the SPM to improve the overall system efciency. Since a prior active clamp forward (ACF) converter with a centertapped transformer (CTT) presented in [2] achieves the zero voltage switching (ZVS) of switches by using the additional resonant inductor, it features low switching losses and high efciency. Furthermore, since rectier diodes have a full rectication conguration, its voltage conversion ratio is higher than that of the traditional single-ended ACF converter, resulting in a higher efciency. Because of these advantages, it can be adopted for the SPM of the PDP. However, in high voltage low current applications such as the SPM, the additional large resonant inductor in series with the leakage inductor Llkg is necessary to achieve the ZVS of all switches over the wide load range. This poses several serious problems, including a large effective duty loss, serious voltage ringing in the rectier diodes, considerable heating, and noisy output voltage. Above all, the dissipative resistorcapacitor (RC) snubber is necessary to absorb the serious ringing voltage across the rectier diodes, degrading the overall system efciency. To overcome these problems, a new high efciency ACF converter for the SPM is proposed as shown in Fig. 1(a). In the proposed converter, since the magnetizing inductor Lm is used to achieve the ZVS of all switches, no additional large resonant inductor is required for the wide ZVS range. In addition, since it has no large output lter