ECE 667 Project 2 Report

Keypad Scanner with Asynchronous Serial Transmitter

Group # 1 Fei Gong Amrita Ghosh Kin Fung Lam Maydeline Que

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Abstract
This project involved the design and implementation of a keypad scanner with serial transmitter. The keypad scanner from the previous project was added the functionality of sending data from the keypad to the computer through serial port. For the CPLD, we designed 1) a baud rate generator capable of generating 1200bps, 2400bps, 4800bps, and 9600bps, 2) a serial transmitter that converts parallel data to serial data, and 3) a system controller that coordinates the signals for proper functionality of the serial transmitter. For the hardware part, we added a MAX232 chip to convert our signals to the RS232 electrical standards. Using hyperterminal to test our design, we were able to successfully demonstrate correct functionality of our system.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Introduction
This project expanded on the features of the keypad scanner and display from project 1 by adding a serial transmitter to communicate with a computer. The system identifies what key is being pressed by the user and displays it in Hyperterminal on the computer. The data is sent from the CPLD to the computer via the serial port. For this project, we added a MAX232 chip and a serial cable to the previous setup. The MAX232 chip converts the TTL signals to the appropriate RS232 signal standards. For the CPLD, we designed three blocks for serial communication: 1. Baud rate generator The baud rate generator is capable of generating clock cycles: 1200 bps, 2400 bps, 2800 bps, and 9600 bps. 2. Asynchronous Serial Transmitter The serial transmitter stores and converts parallel data to serial data. 3. System Controller The system controller coordinates the signals from the keypad scanner to the serial transmitter. The three blocks works as follows: 1. The user chooses which baud rate he uses by setting S1 and S0 appropriately. 2. When the user presses a key, the system will determine what key is pressed and this data is sent to the serial transmitter. 3. The serial transmitter converts the parallel data to serial data and sends this data through the serial cable once transmission has been enabled by the system controller. This laboratory report includes detailed discussion of the baud rate generator, asynchronous serial transmitter, system controller, and the hardware that was implemented. In addition, this report discusses how the components work together to implement the whole serial transmitter system.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Discussion
Baud Rate Generator
We designed a baud rate generator for the asynchronous serial transmitter of project 2. The baud rate can be selected from one of the four possible bit rates. The following table shows the clock frequency the circuit can generate and some implementation information: Rate Select 0(00) 1(01) 2(10) 3(11) Bit Rate 1200 bit/s 2400 bit/s 4800 bit/s 9600 bit/s Clock Frequency 1200 Hz 2400 Hz 4800 Hz 9600 Hz Division Ratio Binary Code to implement

The circuit is similar to the 1 kHz clock generator form the previous project, except that a selectable frequency function has been added. The block diagram for this circuit is shown in Figure 1.

From External Oscillator External Baud Rate Selection

4MHz S1 S0 BAUD_CLK To Asynchronous Transmitter

Figure 1. Baud Rate Generator Block Diagram

In the previous design, we used a T-flip-flop to toggle the output every time it reaches a certain number of counting and reset the counter. This counting monitoring circuit is just simply an AND gate. For this project, we used four counting monitoring circuit to achieve the selectable frequency function. All four counting monitoring circuit will monitor not only the number of counts, but also the status of the input S1 and S0. They are then eventually connected to the output T-flip-flop with an OR gate. The expression for the input of the output T-flip-flop is . The schematic of the final circuit is shown in Figure 2.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Figure 2. Baud Rate Generator Schematic

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Simulation results for the four baud rates are shown in the figures below.

Simulation 1: Output frequency = 1200 Hz

Figure 3. Simulation result for 1200 bps

The resulting frequency is 1198Hz. Percentage of error compared to ideal frequency is 0.166%.

Simulation 2: Output frequency = 2400 Hz

Figure 4. Simulation result for 2400 bps

The resulting frequency is 2395Hz. Percentage of error compared to ideal frequency is 0.208%.

Simulation 3: Output frequency = 4800 Hz

Figure 5. Simulation result for 4800 bps

The resulting frequency is 4773 Hz. Percentage of error compared to ideal frequency is 0.5625%.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

Simulation 4: Output frequency = 9600 Hz

Figure 6. Simulation result for 9600 bps

The resulting frequency is 9527 Hz. Percentage of error compared to ideal frequency is 0.7604%.

Simulation 5: Variable Output frequency

Figure 7. Output Waveform for Different Select Inputs

Asynchronous Serial Transmitter

The function of the transmitter is to store parallel data from the input and retransmit it bit by bit to the serial receiver. The rate of transmission is determined by the baud-rate generator from the previous session. The transmitter is designed to transmit in the standard RS-232 protocol. The format for the protocol is shown in the Figure 8. Start Bit LSB MSB P
Figure 8. Serial Transmission Data Format

Stop Bit

Sometimes, there is a parity bit right after the 7th bit. We simplified the design by eliminating the parity calculation. The design will transmit 8 bits of data instead.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

The overall diagram for the transmitter is shown below. Parallel Data In Transmission Enable Baud Rate Clock P[70] TX CLK TX_RDY TX_DATA To System controller Serial Data Transmission

Figure 9. Serial Transmitter Block Diagram

We divided the system into three sub-systems, namely a state machine, a counter and a parallel-toserial output register.

1. State Machine
The state machine is the main controller of the system. Its behavior can be described by the following state diagram.

Figure 10. State Diagram for State Machine Block of Serial Transmitter

In the state diagram, SX(S(1) S(0)) is denoting different state and their binary representation: S0(00) State when transmission is not enabled S1(01) State when transmission is enabled and transmitting the Start-Bit S2(10) The parallel to serial transmission is ongoing S3(11) Transmission is done and stop bit is being sent RX is the output of the parallel to serial output register. Thus, we derive the following equation from the state diagram.

Gong, Ghosh, Lam, Que ECE 667 Project 2 Report

EN is the output of the state machine to control the operation of both counter and parallel to serial registers. The excitation table of the state machine is shown below.

S(1) 0 0 0 0 1 1 1 1

S(0) 0 0 1 1 0 0 1 1

TX 0 1 X X X X X X

Count_7 X X X X 0 1 X X

S(1)(n+1) 0 0 1 1 1 1 0 0

S(0)(n+1) 0 1 0 0 0 1 0 0

By using K-map, We can easily get the expression for S(1) and S(0). For S(1) TX Count_7 00 S(1)S(0) 00 0 01 1 11 0 10 1 We get the expression For S(0), TX Count_7 S(1)S(0) 00 01 11 10

01 0 1 0 1

11 0 1 0 1

10 0 1 0 1

00 0 0 0 0

01 0 0 0 1

11 1 0 0 1

10 1 0 0 0

We get the expression The circuit for the state machine is shown in figure 11.

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Figure 11. Schematic for State Machine Block of Serial Transmitter

2. Counter
After we have designed the state machine, we move on to the design of 3-bit counter. The counter counts when the ENABLE is high and once it reaches stage 7, the output of counter_7 is high. The block representation of the counter is in Figure 12. ENABLE CLK
Figure 12. Block Diagram of Counter Block of Serial Transmitter

Count_7

Figure 13 shows the schematic of the counter block.

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Figure 13. Schematic of Counter Block of Serial Transmitter

3. Parallel to Serial Output Register

Finally, we need to design a parallel to serial register to wrap up the design. The register will store the value from parallel input when TX is high, and the value will be transmitted when ENABLE from state machine is high. The logic expression for each register is

The schematic of the parallel to serial register is shown in Figure 14.

Figure 14. Schematic Diagram for Parallel to Serial Register

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Combined Blocks
The combined schematic for the Asynchronous Serial Transmitter is shown in Figure 15.

Figure 15. Schematic for Asychronous Serial Transmitter

A simulation result is shown below to verify the functionality of the design. Looking at the red boxed part and comparing it with the green boxed part, we see that from LSB to MSB, the data 00010110 is successfully transmitted in the correct RS232 format.

Figure 16. Output Waveform for Serial Transmitter

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System Controller
A system controller is used to coordinate the work of the keypad scanner and a transmitter. The block representation of the system controller is shown in Figure 17.

Transmitter Status Keypad Scanner Status 4 MHz Clock Signal

TX RDY KP VALID 4M CLK

TX TXMIT

To Transmitter Enable

Figure 17. Block Diagram of System Controller

When the system begins operation, transmission Enable will be low. When the controller detects that a valid key is pressed, that is KP_VALID is high, the controller will enable copying of the current key code to the parallel to serial register by setting TX_TXMIT high. Once the Asynchronous Serial Transmitter gets the key code, it will start the transmission process and providing low signal in TX_RDY. Once TX RDY is low, the controller should reset TX_TXMIT to low to avoid distortion to the transmission until TX_RDY is set high again. We can use D-flip-flop to implement this functionality. Figure 18 shows the state diagram of the system controller.

Figure 18. State Diagram of System Controller

S0(00) is representing the stage no VALID Key Code is found. S1(01) is representing the stage a VALID Key Code is found and TX_RDY is HIGH. S2(11) is representing the stage a TX_RDY is set to low from High, dont care the present state of KP_VALID

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The excitation table for the design is the following: Q1 Q0 KP_VALID TX_RDY 0 0 0 X 0 0 1 X 0 1 X 0 0 1 X 1 1 0 X X 1 0 X X 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

Q1 0 0 1 0 0 0 1 0 1 1

Q0 0 1 1 1 0 0 1 0 1 1

From the excitation table and K-map, Q1: KP_VALID TX_RDY 00 01 Q1 Q0 00 0 0 01 1 0 11 1 0 10 0 0 Therefore, Q0: KP_VALID TX_RDY 00 Q1 Q0 00 01 11 10 Therefore, Besides, 0 1 1 0 0 1 0 0 01

11 0 0 1 0

10 0 1 1 0

11 1 1 1 0

10 1 1 1 0 .

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The schematic of the system is shown below.

Figure 19. Schematic of System Controller

Figure 20 shows the design achieves our design functionality. We see that when a valid key press is detected, the control signal for transmitting data goes high.

Figure 20. Output Waveform of System Controller

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Keypad Scanner with Asynchronous Serial Transmitter (Whole System)

Figure 21 shows the three design block connected to each other to build the keypad scanner with serial transmitter system.

Figure 21. Schematic of Keypad Scanner with Serial Transmitter (CPLD part)

Note that since we only have 4 bits to define the number key that is being pressed, the first 4 bits of parallel data were assigned 0011 respectively. This value was chosen for the data to correspond to the ASCII representation of the numbers. The relevant ASCII code is summarized below. P7 P6 P5 P4 P3 P2 P1 P0 Hex Character 0 0 1 1 0 0 0 0 30 0 0 0 1 1 0 0 0 1 31 1 0 0 1 1 0 0 1 0 32 2 0 0 1 1 0 0 1 1 33 3 0 0 1 1 0 1 0 0 34 4 0 0 1 1 0 1 0 1 35 5 0 0 1 1 0 1 1 0 36 6 0 0 1 1 0 1 1 1 37 7 0 0 1 1 1 0 0 0 38 8 0 0 1 1 1 0 0 1 39 9 0 0 1 1 0 0 0 0 3A : 0 0 1 1 0 0 0 1 3B ; 0 0 1 1 0 0 1 0 3C < 0 0 1 1 0 0 1 1 3D = 0 0 1 1 0 1 0 0 3E > 0 0 1 1 0 1 0 1 3F ?

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Figure 22 shows the simulation results.

Figure 22. Output Waveform for Whole System

Checking TX_DATA, we see that our design achieves the specified functionality.

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Implementation and Testing

We programmed our CPLD with our logic design. Additional pin assignments were done as shown in the table below. PORT I/O PIN # S1 Input 5 S0 Input 4 TX_DATA Output 40 S1 and S0 are for selecting the baud rate and TX_DATA is where the serial data is transmitted.

Figure 23. MAX232 Block Diagram

Figure 23 shows the block diagram of MAX232. RS232 protocol has different electrical definitions for logic 1 and logic 0 as compared to the CPLD. Thus, we need to use a MAX232 to convert the TTL logic signals to RS232 protocol. The electrical specifications of the RS232 protocol are summarized in the table below. TX/RX 1 0 TX -5V to -15V +5V to +15V RX -3V to -15V +3V to +15V The output pin of the MAX232 is connected to a DB-9 connector. For this project, we made use of the most basic pins: just 2 pins of the DB-9, one for ground and one for the transmitted data. Other pins of the DB-9 connector are used for handshaking and receiving data which we did not need for our purposes. Figure 24 shows the pin descriptions of the DB-9 connector.

Figure 24. DB-9 Connector Pin Descriptions

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Figure 25. Circuit Schematic of the Keypad Scanner with Serial Transmitter

Figure 25 shows the connections of the chips and components that were used for this project. The DB-9 connector was connected to the serial port of the computer. Hyperterminal was run to test our design. We chose the appropriate baud rate and configured the following properties: Data bits: 8 Parity: None Stop Bits: 1 Flow Control: None When we tested our design, we encountered 2 problems: 1. Our initial design displayed the same character multiple times for every key press. Keeping the key pressed will result in continuous sending of data. This means that our controller is enabling the sending of the same data multiple times. By changing the system controller state diagram and taking note when the key is released, we were able to solve this problem. 2. Once the first problem was solved, we then encountered a problem with timing. Hyperterminal would display the key that was pressed in the previous key-press. We solved this problem by postponing the VALID signal by one clock cycle.

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Figure 26 shows the screenshot of Hyperterminal when we tested our design with the 4 baud rates. The image also shows the settings used. Note that the baud rate was changed after testing the 16 keys and the baud rate used is indicated before the 16 key presses.

Figure 26. Hyperterminal Screen Shot of Settings and Results

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Conclusion
For this project, we designed and implemented the serial transmitter to be connected to our keypad scanner design from project 1. The keypad scanner system determines what key was pressed and the serial transmitter converts the data to serial data and transmits it to the MAX232, which the converts the signals to the appropriate RS232 signal levels. This data is sent to the computer using a serial cable with DB-9 connectors. When we tested our design, we encountered some problems relating to state diagram design and timing. Changing our design slightly to correct the problems, we were able to demonstrate correct functionality of our system for the four different baud rates.