A High Data Rate QPSK Demodulator for Inductively Powered Electronics Implants

Shihong Deng 1, Yamu Hu 2, and Mohamad Sawan 1

1

Polystim Neurotechnologies Laboratory, Ecole Polytechnique de Montreal, Canada 2 Texas Instruments, Dallas, USA shihong.deng@polymtl.ca In some biomedical applications such as cochlear and visual implants, a downlink with high transmission rate is required to transfer large amount of data for real-time signal processing. Hence, a signal modulation scheme should be chosen to help establish this high data transfer rate link. There are a lot of modulation schemes existing for telemetry and telecommunication applications. Recently some works are mainly focus on the phase shift keying (PSK) [2], amplitude shift keying (ASK) [3][4][5] and binary frequency shifted keying (BFSK) [6][7][8] modulation methods. Among them, ASK has no constant envelop and is not suitable for downlink power transfer The carrier using either FSK or PSK has constant amplitude, which may increase the maximum amount of transferred power. In Table 1, three common modulation schemes are compared. From BPSK to QPSK, a doubled transmitted data rate is achieved within a given bandwidth, at the expense of noise or distortion immunity. BPSK and QPSK have 3dB BER advantage over BFSK. In BFSK, the carrier frequency is changed between two discrete values. Although easier to implement, BFSK has its major disadvantage poor bandwidth efficiency, which in turn limits the data rate for a given bandwidth. So, BFSK is widely used in low data rate applications such as pagers. As the order of PSK becomes higher, the number of bits per symbol will also increase. Nowadays PSK is the most widely used digital modulation. Among different PSK schemes, the QPSK is particularly attractive because of its bandwidth efficiency and high data rate. In this paper, we use QPSK to improve our previous work on BPSK [2].
TABLE I. Mod. scheme
Stimulator Sensor

AbstractA high data transfer rate quadrature phase shift keying (QPSK) demodulator is proposed for wireless implantable electronic medical devices. The QPSK demodulator is an improved version from our previous binary phase shift keying (BPSK) demodulator, which is based on a modified Costas loop. Simulated QPSK model under Matlab Simulink obtained a data transmission rate of 8 Mbps with 13.56 MHz carrier frequency. Also, implemented differential topology of the proposed circuit using a 0.18m CMOS technology achieves a data transmission rate up to 4Mbps with the same carrier frequency. The simulated power dissipation of the schematic is 0.75mw under 1.8V power supply. I. INTRODUCTION The inductive link between two magnetically-coupled coils is now one of the most common methods to wirelessly transfer power and data from the external world to implantable smart medical devices [1]. As shown in Fig. 1, such a system is composed of two parts, the external subsystem and the implant. These two parts are wirelessly connected by an inductive link, allowing power transfer and data communication through the skin. With the ability of bidirectional data transmission, the system mainly consists of a power recovery module, external and internal modulators and demodulators, coils, I/O stages, and controllers. There are two data transmission paths: the external controller sends commands and stimulation parameters to the implanted part (downlink); and, the monitored neuromuscular signals and implants status are sent to the external controller (uplink).
External Skin Implant
Power Recovery Circuitry External Controller Modulator Demodulator Modulator (Uplink)

COMPARASON OF COMMON M ODULATION SCHEMES

Bit Error Rate Advantages -Increased noise immunity -2 bits/symbol -Better bandwidth efficiency -Easy to implement Disadvantages -1 bit/symbol -Increased susceptibility to phase noise - Poor bandwidth efficiency. -High power demond.

BPSK

-3dB better than BFSK

QPSK -Same as BPSK BFSK -3dB worse than BPSK or QPSK

Data Power

Demodulator (Downlink)

Internal Controller

Fig. 1. Block diagram of an implantable system with a wireless inductive link.

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The maximum carrier frequency of the wireless inductive link for biomedical implants is limited to a few tens of MHz due to the human health issues, the coupled coils selfresonant frequency, the power loss in the power transfer circuitry, and the power dissipated in the tissue, which increases as square of the carrier frequency [9]. On the other hand, the determination of the carrier frequency used must follow the guidelines of the spectrum management and telecommunications policies published by authorities. Considering the power loss due to tissue dissipation, we choose the carrier frequency of 13.56 MHz, which is legally designated for industrial, scientific and medical (ISM) applications in many counties [10]. In this paper, the architecture of the QPSK demodulator is determined through Simulink simulation, and then it has been implemented using TSMC 0.18m CMOS technology. In section II, the proposed QPSK demodulator is illustrated. Simulation results of the proposed demodulator and conclusions are given in section III and IV respectively. II. QUADRATURE PHASE SHIFT KEYING DEMODULATION

onto. The aligned data transitions make this effect worse. In offset QPSK (OQPSK) shown in Fig. 2(b), the odd data stream is offset by T. The two data streams no longer change their states simultaneously, but are staggered in time. This timing change makes the effect less severe and does not have any impact on channel capacity or bandwidth. In our design, the input signal of the proposed demodulator is OQPSK modulated signal. B. QPSK demodulation There are three popular PSK demodulation techniques: the Costas loop, remodulation, and the multiply-filter-divide method. The remodulator is stochastically equivalent to the hard-limited Costas loop, while the third method is always used in high-rate, burst-mode systems. Since we have already presented a hard-limited Costas loop BPSK demodulator in [2], the proposed QPSK demodulator also uses the Costas loop method. In order to compare these two demodulators, the BPSK demodulator is redrawn in Fig. 3. The Costas loop may be extended to lock onto a modulated QPSK signal. Such a modified hard-limited Costas loop is shown in Fig. 4 [11], whose structure is close to that of the BPSK loop shown in Fig. 3. The two low-pass filters in the I and Q branches of the QPSK demodulator are followed by limiters, which directly change the filter output voltages to the highest level or lowest level when there is a phase error, and thus speeds up the tracking process of the loops. If linear amplifiers were substituted for the limiters, the Costas loop would fail to lock [11].
I branch Data Out m (t)cos(12)

A. Modulation considerations Before studying QPSK demodulation, it is helpful to analyze its modulation process first. In BPSK, only one carrier is used, and the carriers polarity is controlled by a binary data signal (one-bit data stream). In QPSK, we generate two carriers that are the in-phase component and the 90 quadrature phase component. These two carriers are offset in phase by 90. Their polarities are switched respectively by two binary signals (two-bit data streams). Hence, QPSK has four possible transmitted phases, and it doubles the data rate of BPSK, but without requiring additional bandwidth. Suppose a binary data stream as delivered by the data source is shown in Fig. 2. To apply QPSK modulation, this sequence should be partitioned into two independent data streams: the even bit (b0, b2, etc.) data stream modulates the in-phase carrier, while the odd bits (b1, b3, etc.) modulate the quadrature carrier. In Fig. 2, T is the symbol period of the source signal. In standard QPSK as shown in Fig. 2(a), the even and odd bit streams are both transmitted at the rate of 1/2T bit/s and are synchronously aligned, such that their transitions coincide. Since the modulated carrier temporarily fades away whenever a data signal changes polarity, the demodulator temporarily loose the signal that it tries to lock
(Data)

LPF Incoming BPSK Signal m(t ) sin(1t +1) sin(1t +2)

90 Phase Shifter

VCO

LPF

1 2 m (t)sin2( ) 1 2 2

cos(1t+2) LPF

m(t )sin(12) Q branch

Fig. 3. Costas loop for BPSK demodulation [2].

(Data)

b0

b1

b2

b3

b4

b5

(Data)

b0

b1

b2

b3

b4

b5

b0

b1

b2

b3

b4

b5

(Data)

b0

b1

b2

b3

b4

b5

(Even) b0

b2

b4

(Even)

b0

b2

b4

(Even)

b0

b2

b4

(Even)

b0

b2

b4

(Odd)
(Odd)

b1 0 T

b3

b5

(Odd) 0 T

b1

b3 2T 3T 4T (b) OQPSK 5T

b5

b1 T 2T 3T

b3 4T 5T

b5

(Odd)

b1 0 T 2T 3T

b3
(b) OQPSK

b5 4T 5T

2T 3T 4T 5T (a) Standard QPSK

(a) Standard QPSK

Fig. 2. Principle of QPSK and OQPSK. The timing of the odd data streams is different for (a) and (b).

Fig. 4. Modified Costas loop for QPSK demodulation.

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Providing that two independent binary messages x(t) and y(t) modulate the two orthogonal components of the carrier, where x(t) and y(t) have the values of +1 or -1 representing binary one or zero respectively. Then, the transmitted signal can be represented as Vs(t) = x(t) cos(1t + 1) - y(t) sin(1t + 1). (1) When the loop has locked, the VCO generates a signal of the form uVCO(t) = sin(1t + 2) (2) After applying usual multiplications and trigonometric identities, the low frequency output of the adder will be Vd(t)=[x(t)sin(e)+y(t)cos(e)]sgn[x(t)cos(e)-y(t)sin(e)] -[x(t)cos(e)-y(t)sin(e)]sgn[x(t)sin(e)+y(t)cos(e)] (3) where e =1-2 is phase error, and sgn( ) is the hard limiting operation. For rectangular data signals, the average DC outputs can be calculated as

significantly degrade the bit-error rate (BER) performance since one bit error will destroy all the following data. The most common solution calls for the periodical insertion of a unique word as a data preamble or synchronization marker for framed data transmission. After preamble decoding, the demodulator inverts those data lines which are in error. Then, the two data lines may be multiplexed together, and the original data sequence can be recovered. In our design, we choose the use of preamble, since it not only resolves the phase ambiguity, but also helps the frame synchronization. III. SIMULATION RESULTS

sin e , if 45 < e < 45 cos e , if 45 < e < 135 Vd ( t ) = sin e , if 135 < e < 225 cos e , if 225 < e < 315

(4)

A. Demodulator architecture validation To validate the architecture of the proposed QPSK demodulator shown in Fig. 4, we carry out numerical simulation using Matlab Simulink. The waveforms of the input OQPSK modulated signal, two input data streams, and two output streams are shown in Fig. 6. Results illustrate that the modified hard-limited Costas loop can effectively perform both carrier reconstruction and synchronous data detection. However, in Fig. 6, because of the inherent phase ambiguity, the output A locks to the complement of input B, while the output B recovers the data of input A, showing the necessity of resolving the fourfold phase ambiguity. In Matlab simulation, the total data transmission rate of the two data streams can be up to 8Mbps with the carrier frequency of 13.56MHz. Note that since the noise in channel and circuitry is not considered, this is an idealized transmission rate. B. Circuit implementation Although there are a lot of on-the-shelf QPSK demodulator products on market, they are not suitable for wireless implantable applications for their too high power dissipation. We have to design the modulator using mixed signal circuit to avoid the complexity if it is realized by pure analog circuits. Following the main idea of our previous

If e=0 , Vd(t)=sin e, which can be approached by e for small phase error. The Costas loop then operates like a conventional PLL, and locks at e=0. Similarly, the loop can also lock at e=90, 180, and 270. This is illustrated by the sawtooth characteristic shown in Fig. 5. Hence, there is an inherent fourfold phase ambiguity that must be resolved by other means. C. Phase ambiguity solution The phase ambiguity stems from an inability of the PSK demodulators carrier recovery circuitry to select the correct reference phase from the four possible stable lock points. The ambiguous condition may arise during the initial lockup of the loop or may result from noise in the channel, which causes the carrier recovery circuit to skip to another equilibrium phase. With this phase ambiguity, the loop can lock to any of four possible phase points, only one of which has the correct phase relationship with the carrier. The QPSK fourfold phase ambiguity may be resolved by use of differential coding technique, at a cost of reduced power efficiency. More importantly, differential coding produces a highly correlated data sequence, which may
Vd

-180

-135

-90

-45

45

90

135

180 e(Deg)

Fig. 5. Phase detector characteristics of QPSK Costas loop.

Fig. 6. Simulink simulation result of the proposed QPSK demodulator.

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IV.
RC LPF

CONCLUSIONS

Chopper Multiplier

OQPSK Signal
Quadrature Signal Generator

Data Out A

VCO

Subtracter & LPF

RC LPF

Data Out B

Chopper Multiplier

Fig. 7. Modified Costas loop for QPSK demodulation.

In this paper, the QPSK modulation is chosen because of its bandwidth efficiency and high data rate. Based on our previous work on BPSK demodulator, a modified hardlimited Costas loop QPSK demodulator has been implemented using a 0.18 m CMOS technology. In schematic simulation, the data transmission rate of the proposed QPSK demodulator can be up to 4Mbps and its power dissipation is 0.75mW under 1.8V power supply. Results show that PSK modulation scheme is very appropriate for those wireless implantable applications targeting high data transmission rate and low power dissipation. Circuit improvement and optimization are undertaken to push the data transmission rate higher. In [12], a method is presented to reduce the fourfold phase ambiguity to twofold at no power efficiency. Integrating such kind of block in the proposed QPSK demodulator to interleave the two bit streams and resolve any 180 phase ambiguity will be part of our next work. ACKNOWLEDGMENTS Authors would like to acknowledge the financial support from NSERC and the design tools provided by CMC Microsystems. REFERENCES
[1] M. Sawan, Y. Hu, and J. Coulombe, Wireless smart implants dedicated to multichannel monitoring and microstimulation, IEEE Circuits and Systems Magazine, vol.5, Issue 1, 2005. [2] Y. Hu, and M. Sawan, A fully-integrated low-power BPSK based wireless inductive link for implantable medical, MWSCAS'04, vol.3, pp 25-28, July 25-28, 2004. [3] W. Liu, et al. A neuro-stimulus chip with telemetry unit for retinal prosthetic device, IEEE JSSC, vol.35, Oct. 2000. [4] J. Coulombe, J.-F. Gervais, and M. Sawan, A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link, ISCAS '03, vol.5, pp.53-56, May 2003. [5] K.D. Wise, D.J. Anderson, etc, Wireless implantable microsystems: high-density electronic interfaces to the nervous system, Proceedings of the IEEE, vol.92, pp.76-97, Jan 2004. [6] M. Ghovanloo, and K. Najafi, A Wideband Frequency-Shift Keying Wireless Link for Inductively Powered Biomedical Implants, IEEE Trans. on Circuits & Systems I: vol. 51, pp. 2374-2383, Dec. 2004. [7] M. Ghovanloo, and K. Najafi, A high-rate frequency shift keying demodulator chip for wireless biomedical implants, Proceedings of ISCAS '03, vol.5, pp.45-48, May 2003. [8] M. Ghovanloo, and K. Najafi, A high data transfer rate frequency shift keying demodulator chip for the wireless biomedical implants, MWSCAS02, vol.3, pp.433-436, Aug. 2002. [9] C. Polk, and E. Postow, Handbook of Biological Effects of Electromagnetic Fields, CRC Press, 1986. [10] Canadian Table of Frequency Allocations 9 kHz to 275 GHz, by Industry Canada, http://strategis.gc.ca/spectrum. [11] J. K. Holmes, Coherent Spread Spectrum Systems, Wiley, 1981. [12] J. Berner, and P. Kinman, "Reduction of Phase Ambiguity in an Offset-QPSK Receiver," NASA Tech Briefs, May 2004.

BPSK demodulator [2], an input comparator is also adopted to convert the input OQPSK modulated signal into square waveform, allowing a XOR phase detector used in each branch. Fig. 7 shows the block diagram of the proposed QPSK demodulator. In order to achieve better noise immunity and power supply rejection ratio, the actual structure is fully differential. Most of the building blocks are similar to those of the BPSK demodulator, except the subtracter, which may be easily realized using opamp and resistor network. The proposed QPSK demodulator has been implemented using TSMC 0.18 m CMOS technology. By using Cadence Spectre simulator, a data rate up to 4Mbps was achieved with a 13.56MHz carrier. The simulated total power dissipation is 0.75mW. In Table II, the performance of the proposed QPSK demodulator is compared with the results of other references.
TABLE II.

COMPARISON OF RESULTS
DFSK[6] BPSK[2] QPSK CMOS CMOS CMOS 1.5m 0.18m 0.18m 5/10, 50.5 13.56 13.56 based clock 8 (Matlab) 4(S) 1.12 (S) 4 (S) 2.5(M) 0.414 0.75 0.38 at 1.12 at 4Mbps Mbps

Process

FDSFSK[8] RDFSK[7] CMOS CMOS 3m 1.5m

Carrier 2 ~ 20 2 ~ 20 (MHz) Max. data 2.5 (S*) 4 (S) rate (Mbps) 1 (M**) 1.5(M) Power 0.55 0.45 dissipa. at 100 kbps at 200 kbps (mW) *S = Simulated, **M = Measured

For the proposed QPSK demodulator, the data transmission rate in Simulink (Matlab) simulation is up to 8Mbps, while with same structure, it is only 4Mbps in circuit simulation. This is because that all models in Simulink simulation are ideal. All the noise and device nonideality are not taken into account. For example, we use the model of ideal comparator to simulate the limiters. However, in circuit, the performance of comparators is far from ideal. On the other hand, the fact shows our design is potential to be improved to approach the ideal performance. Now the circuit optimization and fabrication are on the way.

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