Escolar Documentos
Profissional Documentos
Cultura Documentos
Summary
Guide GU0101 (v1.2) November 30, 2005
This guide gives an overview of using the Altium Designer environment to develop an FPGA design. Once you have read this document, refer to the linked documents for a detailed description of that area of the design process.
Over the last 50 years the electronics engineer has had a rapidly changing palette to work with. The introduction of the transistor in 1947 heralded the arrival of solid-state electronics, fostering the development of binary or digital electronics. With the implementation of multiple transistors on a single piece of silicon in 1959 the integrated circuit (IC) was born. With it came the application of Boolean logic a form of algebra where all values are reduced to true or false giving rise to the computer age. The spread of computers throughout the developed world, and the rapid improvements in IC development capabilities saw more and more transistors being squeezed onto an IC. The result of this has been more and more powerful devices, identified by the term large scale integration, or LSI circuits. This process has continued in harmony with the introduction of numerous computer interface standards. Bringing together LSI fabrication capabilities with these defined standards has resulted in the development of powerful, application specific integrated circuits (ASICs) for networking, communications, image processing, computer bus management, and so on. Typically these components are combined with microprocessors and other logic to form sophisticated electronic products, capable of performing an incredible variety of tasks each solving some problem that the engineer set out to resolve. Along with the growth in the size and functionality of application-specific ICs, there has been a corresponding growth in the size and capabilities of programmable logic. Larger programmable devices typically have their functionality arranged as an array of general purpose logic blocks, with programmable interconnections between them. These are known as Field Programmable Gate Arrays (FPGAs). With their ability to operate at high switching frequencies FPGAs have provided an ideal solution for implementing large amounts of high speed signal processing circuitry, allowing the designer to reduce the size and cost of a product. Today these devices have sufficient capacity to implement more than just some of the hardware in a product they can potentially be programmed to implement an entire digital system, including the microprocessor, peripheral components and the interface logic. To do this the engineer needs a design environment that solves the system integration issues where they can capture the hardware design, write the embedded software for the processor, and implement, test and debug both the hardware and software on the target FPGA.
GU0101 (v1.2) November 30, 2005
FPGA Designers Quickstart Guide Altium Designer brings together the required tools and the necessary communications systems. Combine this with an FPGA implementation platform the NanoBoard and you have a complete FPGA design environment. This QuickStart guide will give you an overview of how you can capture and implement an entire digital system in an FPGA in this design environment.
The Knowledge Center panel includes a powerful PDF searching feature, available at the bottom of the panel. Pages that include all words in the search string are returned (except common words such as and, or, etc). The search scope is determined by your current location in the navigation structure.
Figure 1. Use the Knowledge Center panel to learn about what you are doing, or use it to browse and search the extensive PDF-based documentation library.
Discrete Processors 32-bit processor-based projects that specifically target the discrete 32-bit processors (PowerPC PPC405CR and ARM720T LH79520) and features on the NanoBoard. FPGA Core Integration simple FPGA project and related core component project. FPGA Design Tips projects that demonstrate a feature of the design system, including projects that demonstrate bus constants and bus interconnects. FPGA Hardware designs that do not include an embedded processor. FPGA Processor Tests projects for testing the functionality of the NanoBoard. FPGA Processors processor-based projects that demonstrate a specific processor (TSK165x, TSK51x, TSK52x, TSK80x) and features on the NanoBoard. FPGA Processors 32-bit processor-based projects that specifically target the 32-bit RISC processors (TSK3000A, PPC405A, MicroBlaze) and features on the NanoBoard. FPGA Third Party Boards designs that can be implemented in an FPGA on a variety of 3rd party development boards. NanoBoard Testing designs used for testing the functionality of the NanoBoard, referred to in the NanoBoard 1 Technical Reference. Reference Designs working designs that include both an FPGA project and a PCB project. Tutorials files used by the tutorials included in the documentation.
Code Conversion
EDIF
HDL Simulation
FPGA Synthesis
FPGA pin assignments
Figure 2. System diagram, showing the flow of the hardware design, embedded software, and PCB design.
Once the hardware design is complete it is synthesized, a process that transforms it from the capture form into a low-level gate form. After design synthesis a place and route is performed, a process where device-aware software implements the design in the target FPGA. The Vendor-specific place and route software required to synthesize for the target architecture is operated by the Altium Designer environment, which automatically manages all project and file handling aspects required to generate an FPGA program file. To test and debug the design the system includes a NanoBoard, an implementation platform that includes an FPGA, as well as an array of general purpose peripheral components. The software communicates directly with the NanoBoard via a port on the PC, programming the FPGA and implementing your design. Once the design has been implemented on the NanoBoard it can be debugged, using virtual instruments and boundary scan pin status technology to debug the hardware, and the integrated debugger for the embedded software. Since debugging is performed live from within the same environment as the design is captured in, design iterations can be carried out quickly and software/hardware solutions rapidly explored.
Write code
Program device
Most projects target a single implementation for example a PCB project becomes one PCB, and an FPGA project is implemented in a single FPGA. The project document itself is an ASCII file that stores project information, such as the documents that belong to the project, output settings, compilation settings, error checking settings, and so on. The hardware design in an FPGA project is captured as a set of schematic sheets, or as a mixture of both schematic sheets and HDL code (VHDL or Verilog). In the latter case, the minimum requirement is a single schematic top-sheet on which to define the ports for the design. The schematic is captured in the schematic editor, with each schematic sheet being stored as a separate file. VHDL is captured in the syntax-aware VHDL editor. Verilog is captured in the syntax-aware Verilog editor. Click the Project button on the Projects panel to add new source documents into the project. For detailed information on how to create an FPGA project, add schematic sheets, place and wire components and implement the design in an FPGA, refer to the Getting Started with FPGA Design tutorial.
Figure 4. A compiled FPGA project, showing the hierarchical relationship between project documents.
For more information on multi-sheet designs, refer to the Connectivity and Multi-sheet Design article.
FPGA Designers Quickstart Guide instantiated the required number of times. The advantage of multi-channel design is that it allows you to maintain a single copy of the source channel, even after the design has move to implementation in the FPGA or on the PCB. For more information on how to capture a design with repeated sections, refer to the Multi-Channel Design Concepts article.
Figure 5. Document hierarchy is created by placing sheet symbols to represent the document below.
Figure 6. Hierarchical net connectivity is from the sheet entries to matching ports on the document below.
For details on placing the wiring, refer to the Getting Started with FPGA Design tutorial. For more information on connectivity in multi-sheet designs, refer to the Connectivity and Multisheet Design article.
Note that apart from the JB-type joiner, all bus joiner pins have an IO direction use the correct joiner to maintain the IO flow. Pin IO can be displayed on sheet by enabling the Pin Direction option on the Schematic General page of the Preferences dialog.
The JB-type bus joiner allows you to match nets in buses of different widths. It does this via 2 component parameters, IndexA and IndexB that map from one bus through to the other bus. These indices must be defined when you use a JB-type bus joiner.
Figure 9. JB-type bus joiner, note that there is no IO direction for a JB component
10
FPGA Designers Quickstart Guide Read the flow of nets through a JB-type bus joiner by matching from the nets in the attached bus, to the first index on the bus joiner, to the second index in the bus joiner, to the nets defined in the second bus net label. Left Bus IndexA IndexB Right Bus The rules for matching nets at each of the points are as follows:
Figure 10. An example of using the JB bus joiner to achieve sub-set mapping.
If both bus ranges are descending, match by same bus index (one range must lie within the other for valid connections). In Figure 10 the matching is:
ADDR9 IndexA9 IndexB9 ROMADDR9, thru to ADDR0 IndexA0 IndexB0 ROMADDR0
If one bus range is descending and another is ascending, the indices are matched from left to right. In Figure 12 the matching is:
INPUTS0 IndexA15 IndexB31 PORTB31, thru to IndexB16 PORTB16 INPUTS15 IndexA0
Figure 13. Another example of using a bus joiner for range inversion.
For an example of using bus joiners, refer to the example \Program Files\Altium Designer 6\Examples\FPGA Design Tips\Bus Interconnect\Interconnect.PRJFPG.
11
As well as components that you use to implement your design, the available FPGA libraries include components for the virtual instruments, and the components that are mounted on the NanoBoard and are accessible via the pins on the FPGA.
Model linkage
EDIF model linkage is not handled like standard component model linkage, since the model must be chosen to suit the target device. For EDIF models the target device family is used to select the correct folder of EDIF models (for example \Xilinx\Spartan2E), and then the components Library Reference is used to select the EDIF model file from within that folder. Models included with the system are stored in a hierarchy of folders under \Program Files\Altium Designer 6\Library\Edif. As well as system supplied models, user-created pre-synthesized EDIF models are supported. These can be stored in a user model folder, this folder is specified on the FPGA Synthesis page of the Preferences dialog (DXP Preferences). User models can also be stored in a hierarchy of folders if you are developing a model for multiple target devices. The search sequence for EDIF models is: $project_dir $user_edif\$vendor\$family $user_edif\$vendor $user_edif $system_edif\$vendor\$family $system_edif\$vendor $system_edif Pre-synthesized user models are developed by creating a Core project, whose EDIF output becomes the model for your user-defined component. There are a number of features to support this process, including commands to synthesize for all targets, publish the EDIF model (package it with all other required EDIF models), and generate a component symbol to represent the core. For more details refer to the Creating a Core Component tutorial. The tutorial also details how to use that component in an FPGA project while still developing the core. For an example of a core component project that is linked to an FPGA project, open the design workspace \Program Files\Altium Designer 6\Examples\FPGA Core Integration\LCD Controller And Keypad\LCD_Keypad.DSNWRK. To use this example you must define a user model location first, then generate the model for the keypad scanner before attempting to process the FPGA design (LCD_Keypad) that uses the model.
12
ARM720T_LH79520 Wishbone-compliant wrapper to the Sharp BlueStreak LH79520 (ARM720T) 32-bit discrete processor MicroBlaze 32-bit RISC Processor. This processor can only be used with Xilinx FPGA devices and requires the Xilinx EDK and a valid MicroBlaze license. The Altium Designer Documentation Library includes both hardware and software reference manuals for each processor. From the bottom section of the Knowledge Center panel, navigate to Embedded Processors and Software Development > FPGA Based and Discrete Processors.
Peripheral components
Peripherals can be placed from the \Program Files\Altium Designer 6\Library\Fpga\FPGA Peripherals.IntLib library. The following peripheral components are available: CAN Controller parallel to serial interface, implementing a Controller Area Network serial communications bus on the serial side. The CAN serial bus provides high bit rate, high noise immunity and error detection. The Controller implements the BOSCH CAN 2.0B Data Link Layer Protocol. 8-bit
GU0101 (v1.2) November 30, 2005
13
FPGA Designers Quickstart Guide Wishbone and non-Wishbone variants available. The CAN controller can be used in conjunction with the CAN interface hardware on the NanoBoard. EMAC Controller parallel to serial interface providing 10/100Mbps interface between a host processor and a standard Physical Layer device (PHY) through support of the IEEE802.3 Media Independent Interface (MII). 8-bit (Wishbone and non-Wishbone) and 32-bit (Wishbone) variants available. FPGA Startup Unit user-definable power-up delay, used to implement power-on reset. An internal counter starts on power up, counting the number of clock cycles specified by the Delay pin, the output pin being asserted when the count is reached. Variants available with 8-, 16- and 32-bit delays. I2C Controller parallel to serial interface, implementing an Inter-Integrated Circuit (I2C) 2-wire serial bus on the serial side. Controllers only support a single master I2C serial bus system. 8-bit Wishbone and non-Wishbone variants available. The I2C controller can be used in conjunction with the I2C interface hardware on the NanoBoard. Keypad Controller 4 by 4 keypad scanner with de-bounce. Can be used in a polled or interrupt driven system. Available in either Wishbone or nonWishbone variants. The Keypad controller can be used in conjunction with the keypad on the NanoBoard.
For help on an FPGAready component, click on the components entry in the Libraries panel, or hover over the placed component, and press F1.
LCD Controller easy to use controller for a 2 line by 16 character LCD module. Available in Wishbone and non-Wishbone variants. Also provides a variant that caters for non-simultaneous access to both a physical memory device and a target LCD panel. The LCD controller can be used in conjunction with the LCD display on the NanoBoard.
MAX1104 DAC Controller parallel to serial interface providing a simple interface to the MAX1104 8bit CODEC device on the NanoBoard. PRT Unit simple parallel port interface providing register storage for data to be transferred to/from another device in a design. Three families of non-Wishbone device are available, offering output only, I/O and I/O with additional tristate buffer enable for each output port. Within each family, single, two and four port devices with 8- or 32-bit port widths are available. PS2 Controller parallel to serial interface providing a bidirectional, synchronous serial interface between a host processor and a PS/2 device (keyboard or mouse). The PS2 controller can be used in conjunction with either of the two sets of PS2 interface hardware on the NanoBoard. SPI Controller provides an SPI Master interface, enabling a Wishbone-compliant host processor to communicate with a slave SPI peripheral device which resides outside of the physical FPGA device to which the design is targeted, such as the audio DAC and serial Flash RAM devices located on the NanoBoard. SRL0 Unit simple parallel to serial interface, full duplex, single byte buffering. Both Wishbone and non-Wishbone variants are available. The SRL0 can be used in conjunction with the RS-232 interface hardware on the NanoBoard. TMR3 Unit dual timer unit, configurable as either Timer or Counter with four possible modes of operation for each. Available in Wishbone and non-Wishbone variants. VGA Controller providing a simple interface between a host processor and any VGA-compatible monitor. Available in 8-bit (non-Wishbone) and 32-bit (Wishbone-compliant) variants. The VGA controller can be used in conjunction with the VGA output on the NanoBoard.
14
FPGA Designers Quickstart Guide WB_DUALMASTER configurable Wishbone device providing a simple means of sharing a slave Wishbone device between two masters for example, sharing a physical memory device between either two processors or a processor and a memory-based peripheral, such as a VGA Controller. WB_INTERCON configurable Wishbone device providing a means of accessing one or more Wishbone-compliant slave devices over a single Wishbone interface. Connecting directly to either the External Memory or Peripheral I/O Interfaces of a processor, the device facilitates communication with physical memory devices or I/O peripherals, respectively. WB_MEM_CTRL configurable Wishbone memory controller that, depending on its configuration, provides a simple interface between a 32-bit processor (such as the TSK3000A or PPC405A) and either Static RAM or 32-bit wide Block RAM (single or dual port). WB_PRTIO configurable Wishbone parallel port unit, providing a simple register interface for storing data to be transferred to/from another device in a design. Supports three port types I/O, Output only and Tristate. Ability to define 1, 2 or 4 port interfaces with port data bus widths of 8-, 16- or 32-bit. WB_PWMx Wishbone Pulse Width Modulation Controller, capable of generating PWM Counter and/or Pre-Scaler Counter interrupts and a differential pulse-width-modulated rectangular wave output signal. Available in standard (8-bit resolution) and extended (software-selectable 8-, 10-, 12- and 14-bit resolution) variants. WB_UART8 providing a serial communications port with hardware hand-shake and FIFO buffers. Full duplex, fixed to no parity, 8 data bits and 1 stop bit. Includes a dedicated, high precision internal baud rate generator. This device can be used with the RS-232 interface hardware on the NanoBoard. The Altium Designer Documentation Library includes a hardware reference for each peripheral device. From the bottom section of the Knowledge Center panel, navigate to Designing with FPGAs > FPGA Core Components
Generic components
Generic components can be placed from the \Program Files\Altium Designer 6\Library\Fpga\FPGA Generic.IntLib library. This library is included to implement the interface logic in your design. It includes pin-wide and bus-wide versions for many components, simplifying the wiring complexity when working with buses. As well as a broad range of logic functions, the Generic library also includes pullup and pulldown components as well as a range of bus joiners, used to manage the merging, splitting and renaming of buses. For a definition of the naming convention used in the generic library and a complete listing of available devices, refer to the FPGA Generic Library Guide. For information on working with buses and using bus joiners, refer to the topic Using buses and bus joiners earlier in this document.
15
Virtual Instruments
To test the state of internal nodes in the design you can wire in virtual instruments. The hardware portion of the instrument is placed and wired on the schematic like other components, and then synthesized into the FPGA. Virtual instruments are placed from the \Program Files\Altium Designer 6\Library\Fpga\FPGA Instruments.IntLib library. The interface to each instrument is accessed in the Devices view once the design has been synthesized and the FPGA programmed. For information on working in the Devices view, refer to the Processing the Captured FPGA Design application note. The instrument hardware that has been synthesized into the FPGA communicates with its interface using the Nexus communications standard, over the JTAG link. For information on the JTAG communications, refer to the PC to NanoBoard Communications article. The following virtual instruments are available:
Figure 15. Digital IO module, used to monitor and control nodes in the design
The digital I/O is a general purpose tool that can be used for both monitoring and activating nodes in the circuit. It is available in either 8-bit wide or 16-bit wide variants, with 1 to 4 channels. Each input bit presents as an LED, and the set of 8 or 16 bits also present as a HEX value. Outputs can be set on a bit-basis by clicking the appropriate bit in the Outputs display, or a HEX value can be typed in the HEX field. The Synchronize button can be used to transfer the current input value to the outputs. For more detailed information on using the Digital I/O instrument, refer to the IOB_x Digital I/O Module core reference.
16
For more detailed information on using the Frequency Generator instrument, refer to the CLKGEN Frequency Generator core reference.
For more detailed information on using the Frequency Counter instrument, refer to the FRQCNT2 Frequency Counter core reference.
Figure 18. Logic analyzer instrument, with a logic analyzer component shown in the inset. Use the LAX to monitor multiple nets in the design, then display the results as a digital or an analog waveform.
17
FPGA Designers Quickstart Guide Captured data The capture results are displayed in the associated LAX panel for the instrument, which can be accessed by clicking the Show Panel button on the instrument panel. Data is listed in terms of its Index - its position within the sample buffer - and can appear in the following formats, the display of which is enabled using the corresponding check boxes in the panel: Hexadecimal Binary Decimal ASCII Character.
The time at which each sample is captured is also shown. The number of samples displayed will be equal to the size of memory that is connected to the Logic Analyzer (LAX_8 and LAX_16) or comes predefined as part of the Logic Analyzer device (1K, 2K and 4K devices). The LAX panel is also used to set up software triggering for the instrument. Waveform display features There are also two waveform display modes. The first is a digital mode, where each capture bit is displayed as a separate waveform and the capture events define the timeline. Note that the capture clock must be set in the logic analyzer options for the timeline to be calculated correctly. Click the Show Waves button associated to digital output on the instrument panel to display the digital waveform.
Figure 19. Digital waveform capture results from the logic analyzer
The second waveform mode is an analog mode, where the value on all the logic analyzer inputs is displayed as a voltage, for each capture event. The voltage range is from zero to the maximum possible count value, scaled to a default of 3.3V (defined in the Logic Analyzer - Options dialog). Click
18
FPGA Designers Quickstart Guide the Show Waves button associated to analog output on the instrument panel to display the analog waveform.
Figure 20. Analog waveform capture results from the logic analyzer
Continuous Display Mode Note that updates performed in the logic analyzer instrument panel are displayed immediately as a waveform, allowing you to interactively examine capture results. There is also a continuous display mode, enable/disable this using the buttons on the toolbar in either the digital or analog wave display window.
For more detailed information on using the Standard Logic Analyzer instrument, see the LAX_x Logic Analyzer core reference.
Figure 22. Feed the required signals into the LAX in sets, then monitor and trigger off any set during runtime.
19
FPGA Designers Quickstart Guide Right-click on the schematic symbol for the instrument and choose Configure to define the number of nets and buses to be monitored, to name them, and to group them into logical sets. To expedite the configuration process, you can select net labels on the schematic and then use the Paste button in the Configure dialog signals with the corresponding names will be added to the currently selected signal set. Disassembly of LAX Data When using the Configurable Logic Analyzer instrument in your design, you have the added ability to interpret the data being captured as the code under execution. Simply select the processor being monitored using the Disassembler field in the LAX panel, and a Disassembly column will be displayed, giving immediate feedback on the state of the code running in that processor.
Figure 24. Use the disassembly view to interpret the LAX data as processor instructions.
20
FPGA Designers Quickstart Guide a logic analyzer) without having to explicitly wire that net up through the design hierarchy to the sheet with the instrument on it. Simply place an instrument probe directive at the point of interest, then define a value for its InstrumentProbe parameter. Enter a meaningful name for the probe point, for example the name of the associated net or the particular signal being monitored. Then, connect a wire to the required input of the monitoring instrument and attach a net label to the wire, the name of which is the same name you have defined for the InstrumentProbe parameter.
Figure 25. Instrument Probes let you monitor any point in the design without having to wire through the design hierarchy to the instrument.
If the instrument probe directive is placed on a net that connects to an FPGA pin, it can be used to monitor the status of that pin directly on the schematic sheet, as well as being used as an input source to a monitoring instrument. The former is achieved using the directives ProbeValueDisplay parameter. When an instrument probe is attached to a bus, the entire bus is taken up to the top-level sheet, irrespective of the name you assign to the InstrumentProbe parameter. When you add a net label to the input for the monitoring instrument, you must define the bus width required. For example, you may have attached an instrument probe to a bus with identifier Port1_Out[7..0] on a lower level sheet. The value for the InstrumentProbe parameter could be simply set to Port1_Out. The entire bus will be connected up to the sheet with the monitoring device (e.g. a LAX). Should you wish to wire up the entire bus as an input signal to the device, you would place a bus to the required input and add a net label of Port1_Out[7..0]. If you only wanted a particular signal or range of signals from the bus, you can simply define the width required in the attached net label.
21
Figure 26. the soft devices JTAG chain is implemented by placing the NEXUS_JTAG_PORT (on the left) from the FPGA Generic library and the NEXUS_JTAG_CONNECTOR from the FPGA NanoBoard Port-Plugin library.
For an overview of the Devices view, refer to the Devices view section later in this guide. For information on the JTAG chains, refer to the PC to NanoBoard Communications article.
22
23
FPGA Designers Quickstart Guide Watches panel Locals panel Evaluate panel Call stack panel Code Explorer panel Memory space panels Debug Console panel The Altium Designer Documentation Library includes Embedded Tools user guides and reference manuals for each processor. From the bottom section of the Knowledge Center panel, navigate to Embedded Processors and Software Development > FPGA Based and Discrete Processors.
The RTOS panel is a runtime status panel, which can display information such as System Status, Alarms, Tasks and Resources. Open the RTOS panel via the Embedded button at the bottom right of the workspace, then enable the required RTOS information by clicking the RTOS button on the Debug toolbar. For detailed information on the RTOS, refer to the TSK51x/TSK52x RTOS Guide. For detailed information on the RTOS panel, press F1 with the cursor over the (focused) panel.
24
Figure 27. Use the Structure Editor to link the embedded project to the processor in the FPGA hardware design.
Figure 28. The name and location of the linked sub-project is displayed in the Component Properties dialog, of the processor that the embedded code runs on.
25
26
Memory Synthesizer
EDIF
Figure 29. The flow of the embedded software development and the hardware design
Before the design can be implemented in an FPGA there are a number of steps that must be carried out. These include: Compiling this process analyzes the design structure and checks for numerous design errors, such as connectivity. Synthesizing this process translates the high-level source design files into a low level description, capable of being read by vendor place and route tools. Building this is the process of implementing the design in the target FPGA. It requires that you have appropriate vendor place and route tools installed on your PC, such as Actels Libero, Alteras Quartus, Lattices ispLEVER, or Xilinxs ISE. Most vendors offer freely downloadable versions of these tools from their websites. These steps are all performed in the Devices view. If you have a NanoBoard connected to the parallel port on your PC when you open the Devices view, the NanoBoard and the FPGA mounted on it will appear as shown in the upper part of Figure 30. Once the FPGA design has been compiled any processors or virtual instruments in the design will appear in the soft chain.
27
FPGA Designers Quickstart Guide For detailed information on connecting and using a third party development board or custom/production board with the software, see the Using Altium Designer with a Third Party Board application note.
Figure 30. The Devices view, used to process and implement the design in the target FPGA device, then communicate with it during debugging.
The NanoBoard chain The first chain is referred to as the NanoBoard chain. When targeting an FPGA device plugged into a NanoBoard, this chain essentially detects the presence of that NanoBoards Controller device. It provides access to the NanoBoard features including the programmable clock and the SPI configuration devices. Double click on the board icon to display the NanoBoard Controller instrument and configure one of these features. The Hard Devices chain The second chain is referred to as the Hard Devices chain. It shows all JTAG compliant devices on the board that are currently accessible in the chain. The buttons above the chain are used to process the design and program the FPGA, below the chain is the name of the
28
FPGA Designers Quickstart Guide project/configuration combination that is currently targeted to the FPGA. The status of this project/configuration is reflected by the color of the indicators in the Compile, Synthesize, Build and Program FPGA buttons. This chain is also used to enable the Live Update feature that performs boundary scan monitoring of the status of component pins. The Soft Devices chain The third chain is referred to as the Soft Devices chain. It shows all Nexus compatible devices that have been implemented inside the FPGA, including processors and virtual instruments. Double click on a processor or virtual instrument to open an instrument panel to control that processor or instrument.
Figure 31. Use the NanoBoard controller to set the clock frequency and program the two flash RAM devices
29
Design synthesis
Synthesis is the process of converting the high level schematic / behavioral HDL description to a lowlevel gate description, suitable for processing by the FPGA vendor place and route tools. The built-in synthesis engine first produces a hierarchical HDL netlist of the design, which is then synthesized into an EDIF description. As well as the EDIF file that describes the design connectivity, the presynthesized EDIF description of each component is also copied into the project sub-folder that is automatically created under the project folder. Synthesis options are configured in the Options for Project dialog (Project menu). Note: Two built-in synthesis engines are available and can be selected for use from the Synthesis tab of the Options for Project dialog the Altium Synthesizer and DXP Synthesizer respectively. The difference between these two is that the Altium Synthesizer supports the synthesis of schematic, VHDL and Verilog files, whereas the legacy DXP Synthesizer supports only synthesis of schematic and VHDL files. New FPGA projects will be set, by default, to use the Altium Synthesizer.
You can also include vendor constraint files in your design, refer to the specific working with vendor tools documents, including Working with Altera Devices and Place and Route Tools and Working with Xilinx Devices and Place and Route Tools for more information.
Figure 32. Click the Options icons to configure that stage of the Build
Program FPGA
This button downloads the device program file to the device. The download progress is displayed on the status bar.
30
Figure 33. Enable the Live Update option in the device's associated JTAG Viewer panel to monitor the state of the FPGA pins.
The JTAG Viewer panel uses the JTAG communications standard to interrogate the state of the pins in any JTAG compliant device in your design, not just the FPGAs. It presents the state of each pin, and includes an image of both the schematic symbol and the footprint, helping you to analyze and debug your design. Live Update can be controlled at the individual pin level. You can also monitor the pin status back on the schematic, place a Probe object on any net that connects to an FPGA pin to see the current status of that net or bus (Place Directives Probe).
Note that for this feature to function, the source FPGA design must be downloaded to the physical FPGA device and the associated JTAG Viewer panel for the device must be open and remain open.
31
Figure 35. Generic JTAG device detected in the Hard Devices chain.
In this case no specific Nexus driver exists for the device (no .NEX file in the \System folder of the installation). To get the system to drive a Hard Devices chain containing such a device, you will need to attach a Boundary Scan Description Language (BSDL) file for the specific device you are using. Such files can be obtained from the relevant vendor website. Once attached, the system will use the information in the file - including the device's ID Code and Instruction Register Length - to correctly configure the Hard Devices chain. A BSDL file is attached to a Generic JTAG Device by right-clicking on the icon for the device in the Hard Devices chain of the Devices view and choosing the Configure JTAG ID Mapping command. The Generic JTAG Device dialog will appear.
Simply click the Add button in the BSDL File Links region of the dialog and navigate to the required file. By default, the path is set to the \Library\BSDL\Generic folder of the installation. BSDL files should be placed in this folder.
32
FPGA Designers Quickstart Guide By including the standard BSDL file supplied with each JTAG compliant device, you have access to the pins on every JTAG device in your design, through the real-time JTAG Viewer panel (Figure 33). Click on the BSDL Information button in the JTAG Viewer panel to access data contained in the BSDL file that you have attached.
The system can even handle the situation where a BSDL file is not available for a device in the Hard Devices chain. Simply set the instruction length for this device to zero (in the Generic JTAG Device dialog) and the JTAG system can continue to communicate to other devices in the chain. Without a BSDL file you will, however, not be able to interrogate the state of pins for the device using the JTAG Viewer panel.
33
Rather than attempting to write the source HDL so that it is both simulation and synthesis ready, and then simulate the entire digital system, the Altium Designer-based FPGA design environment supports the same test and debug methodology used in traditional PCB development. It includes: Embedded software debug tools Instruments, including logic analysers Boundary scan monitoring that show the state of pins on the FPGA The NanoBoard an implementation platform that allows the design to be tested before moving it to the final PCB, and then supports integrated testing of the design on the final PCB.
34
Figure 38. Use the Workspace map to manage the FPGA to PCB project linkage.
For complete details on creating and maintaining the FPGA to PCB project linkage and performing PCB pin optimizations, see the Linking an FPGA Project to a PCB Project application note.
35
Revision History
Date 26-Jan-2004 18-Jul-2005 30-Nov-2005 Version No. 1.0 1.1 1.2 Revision New product release Updated for Altium Designer SP4 Reviewed and Updated for Altium Designer 6
Software, hardware, documentation and related materials: Copyright 2005 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, CAMtastic, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, CircuitStudio, Nexar, nVisage, P-CAD, Protel, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed.
36