IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.

3, JUNE 2002

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An Overvoltage Suppression Scheme for AC Motor Drives Using a Half DC-Link Voltage Level at Each PWM Transition
Sangcheol Lee, Student Member, IEEE, and Kwanghee Nam, Member, IEEE
AbstractPassive filters are conventionally used to suppress overvoltage in the motor terminal, either by reducing the voltage rising rate at the inverter output, or by decreasing the motor terminal impedance. We propose an overvoltage suppression scheme that renders the use of passive filters unnecessary. This approach differs from general filter methods, in that it is independent of and does not try to reduce . Our scheme utilizes the middle voltage level DC 2 at each pulsewidth modulation voltage transition, where DC represents the dc-link voltage. The duration of the middle voltage level is controlled in such a way that reflected voltages are cancelled out at the motor terminal. Optimal cancellation is achieved when the duration of DC 2 is equal to twice the transport delay of the cable. Further, if reflection coefficients at the motor terminal and the inverter output are equal to 1, no overvoltage takes place. The proposed scheme requires the use of six auxiliary insulated gate bipolar transistor switches. Simulation as well as experimental results are presented here. Index TermsOvervoltage suppression, pulsewidth modulation drive, transmission line, transport delay.

I. INTRODUCTION T IS WELL KNOWN that voltage overshoot takes place at the motor terminal if the motor is driven by a pulsewidth modulation (PWM) inverter through a long feeding cable. This overshoot phenomenon has been illustrated with the use of transmission theory, since, the motor feeding cable behaves as a transmission line for PWM pulses [1]. The voltage-source inverter is regarded as a short circuit because its impedance is low compared with cable characteristic impedance. However, the motor impedance presents an effective open circuit [8]. These impedance mismatches cause a voltage reflection, and thereby constitute a factor in the voltage overshoot phenomenon. Note that PWM pulses travel through the cable at approximately half the speed of light (150200 m s) [1], [3]. Hence, a pulse propagation delay occurs in feeding cable transmission. If the pulse rise time is short compared to the propagation delay, voltage overshoot takes place at the motor terminal, since the reflection coefficients at both ends are normally high. To be specific, if the pulse transport delay time from inverter to motor is longer than one-third of the rise time, the pulse amplitude will
Manuscript received December 25, 2000; revised November 1, 2001. Abstract published on the Internet March 7, 2002. The authors are with the Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea (e-mail: kwnam@postech.ac.kr). Publisher Item Identifier S 0278-0046(02)04924-9.

approximately double under full reflection conditions [1], [3]. Further, it was observed by Kerkman et al. [4] that the oscillation(ringing) period is equal to four times that of the pulse transport delay. This means that the shorter the cable length, the higher the oscillation frequency. Insulated gate bipolar transistors (IGBTs) have been develin order to satisfy the oped in the direction of increasing requirements for high PWM switching frequency. With modern IGBT inverters, it takes 0.1 s to rise to 600 V from 0 V, i.e., V/ s. However, such a high rise rate creates a motor terminal voltage doubling with lead as short as 1020 m [10], and the repeated overvoltage results in serious damage to the motor insulation [3], [5], [9]. One method to suppress the overvoltage is to use an LCR filter at the inverter terminal to decrease the voltage rising rate below a critical value [6], [9]. The other method is to install a shunt RC filter at the motor terminals to reduce the reflection coefficient [3]. However, such filtering methods necessitate the use of bulky LCR passive components. The other limitation is that it is difficult to adjust filter parameters when the capacity of the motor and cable length vary. In suppressing voltage overshoot, this work departs from previous works which permit any passive filter to be used. Instead, we modify the PWM transition pattern so that the voltage overshoot mode disappears. We develop an idea based on the observation that high-order reflection terms can be cancelled out if half of the dc-link voltage is provided temporarily at each PWM voltage transition. First, the voltage equations at the inverter output and motor terminal are derived under the dispersionless condition. The canceling method of high-order reflection terms is illustrated when the inverter and motor impedances are zero and infinity, respectively. Secondly, the hardware implementation structure is illustrated with the use of six additional auxiliary IGBT switches. II. VOLTAGE RESPONSE OF A TRANSMISSION LINE PWM pulses traveling between the inverter and the motor behave similarly to traveling waves on transmission lines. To show the graphical analysis, Persson [1] and Enjeti [3] used the snapshot of the voltages on the line at various points in time. These snapshot plots give a global picture of how the waves reflect and re-reflect off the motor or inverter. Another analysis method called a bounce diagram is often utilized for the illustration of voltage wave propagation through the cable. Fig. 1 shows a bounce diagram in which the progres-

0278-0046/02$17.00 2002 IEEE

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Fig. 1. Transmission line bounce diagram between inverter output and motor terminal when a voltage u(t) is injected over a cable whose length is l and whose transport delay is  . U (s) denotes Laplace transform of u(t). K is a reflection coefficient at the inverter output and K is a reflection coefficient at the motor terminal.

Fig. 2. Proposed inverter structure that provides V =2 voltage level and the PWM voltage pattern. (a) Inverter with six auxiliary switches. (b) Proposed PWM voltage pattern having V =2 level each voltage transition.

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Fig. 3. Voltage decomposition of the inverter output voltages and their resulting voltages at the motor terminal. (a) A component of inverter output voltage, (b) a time-delayed component of inverter output voltage, (c) the proposed PWM voltage pattern which is a sum of (a) and (b), and (d)(f) the corresponding output voltages at the motor terminal.

sion of the leading edges of the incident and reflected voltage waves are displayed as functions of both time and position . We assume that the length of the cable is equal to , and that the , , respectively. inverter and the motor are located at and . If the Two time axes are drawn vertically at transmission line has no dispersion, the transmission delay is completely characterized by the properties of the cable in such , where is the inductance (henrys per a way that meter) and is the capacitance (farads per meter) of the cable. The injected (PWM) voltage from the inverter is denoted by and its Laplace transform by . The first progress of at a distance from the inverter is the leading edge of denoted by . Since is assumed to be delayed by at position, we obtain that , where is the Laplace transform of and the

superscript denotes forward propagation to the motor from the inverter. Note that the incident voltage is reflected at the motor terminal due to an impedance mismatch. The reflection coefficient , where at the motor is given by represents the motor impedance and is the characteristic impedance of the cable. Hence, the reflected voltage at the motor terminal is given by , where the superscript denotes backward propagation to the inverter from the motor. At a distance from the inverter, the (initial) reflected voltage is given by . At the inverter side, reflection reoccurs. The reflection coefficient at the inverter is given by , where denotes the inverter impedance. The reflected

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voltage at the inverter output is given by . Note that the voltage reflection at the inverter terminal initiates another forward propagation and that the subscript 2 is used to denote we have the second propagation. Further, at position . is much larger than , is close to Note that when is much smaller than , is close one. However, when implies that the wave is fully to 1. Note further that reflected at the motor terminal without the phase change, and implies that the wave is fully reflected at the inverter output with a 180 phase change. A bouncing process occurs infinitely, as shown in a bounce diagram (Fig. 1). Hence, the voltages on the cable is represented as the sum of infinite reflections. For the convenience of computing the power series, we add forward-traveling voltages and as backward-traveling voltages separately. We denote the sum of the sum of forward-traveling voltages and , , it folbackward-traveling voltages. Since lows that

Fig. 4. Percentage overshoot voltage level at the motor terminal for various K and K when  = 2 .

(1)

(2) Hence, the Laplace transform of the voltage at any point the cable is given by [2] on

(3) For example, the inverter output voltage and the motor terminal and , respectively, voltage are obtained by putting as follows: (4) (5) The voltage at the inverter output is a sum of even transport delayed signals, and the voltage at the motor terminal is a sum of odd transport delayed signals from the inverter to the motor feeding cable. III. A VOLTAGE OVERSHOOT REDUCTION METHOD AT THE MOTOR TERMINAL In this section, we describe a strategy to reduce voltage overshoot at the motor terminal by inserting the middle voltage

level at each voltage transition. Note that the PWM voltage does , where denotes the not increase/decrease steadily to dc-link voltage. Instead, it retains at the middle level for time at each rising/faling transition of PWM. The middle voltage level can be implemented by using the bidirectional switches between the center point of the dc-link capacitors and the inverter output terminals as shown in Fig. 2(a). Fig. 2(b) shows the proposed PWM pattern generated at the inverter output terminal. To illustrate, we consider the rising edge of the proposed PWM voltage as the sum of the two voltages, as shown in Fig. 3, . Note that the two components i.e., are identical, except that one is time delayed by . Thus, its . Laplace transform is given by Fig. 3 shows the components of inverter output voltages and their corresponding virtual motor terminal voltages when , . Note in this simulation that the load is modeled as a pure resistor. Since the reflection coefficients are set to be large, huge voltage oscillations appear at the motor terminal with the period of . Hence, the output voltage pulse width shown in Fig. 3(e) is . However, notice that has time delayed by from shown in Fig. 3(d) in the same pattern that the corresponding inputs are spread. Hence, , the two components overlay in it is noteworthy that if the form of toothing. That is, the peaks of Fig. 3(d) overlap the valleys of Fig. 3(e), so that almost no voltage overshoot takes place at the motor terminal, as shown in Fig. 3(f). This can be justified by a mathematical expression; at the , we obtain from (5) that motor terminal (6) Expressing (6) in series, we obtain

(7)

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Fig. 5.

Equivalent circuit for invertercablemotor system.

If we let

, it follows that

(8) (9) enables grouping It should be noted from (9) that and that in most with the coefficient , being large, implies cases. Since motor impedance and inverter impedance , being small, implies . Therefore, the second term in (9) is negligible. This implies , almost no voltage overshoot takes that if we choose place. If and in an extreme case, then the , i.e., motor terminal voltage is given by . In this case, a slight delay is observed with no voltage overshoot at the motor terminal. The maximum percent overshoot can be derived from the first two terms of (8), such that (10) Fig. 4 shows the percentage overshoot voltage level at the motor and . For example, the terminal for various values of . If peak overshoot value reaches 12.5% when and , the peak overshoot value is below 13.05%. This is a remarkably low value when compared to the conventional case, which has a 90% overshoot. IV. SIMULATION Fig. 5 shows an equivalent circuit of the inverter-cable-motor system that is used for simulation study. The inverter is modeled , as an ideal PWM voltage source plus a series resistor,

which is a big value for dc or the fundamental frequency component. However, we are concerned at the high-frequency components in the rising and falling edges of the PWM pulses. For such high-frequency components, the inverter contains large stray inductance, skin effects, and RF emission losses. If such losses are included in , it goes up to 7 and we call it surge impedance. For the purpose of comparision with the experimental data, we utilize the measured values for simulation parameters. Inductance, capacitance, and resistance of the cable H/m, pF/m, and are chosen as m /m. These values are calculated from the measured S-parameters by a network analyzer. Further, they are confirmed by a high-speed digital sampling oscilloscope which is used ns and characteristic to measure transport delay . The inductance and capacitance impedance of the cable are obtained, such that H/m, pF/m. Since the length of the cable is set to be m, the entire transport delay is calculated sec. The attenuation loss factor is as . The estimated to be motor is modeled by a high-frequency ( pF, ), in parallel with a low-frequency model ( , H) that was used in [7]. The motor parameters are calculated from the measured values, using an impedance analyzer. Simulations are performed using MATLAB/SIMULINK.1 Fig. 6 shows a block diagram for computing the inverter output voltage and the motor terminal voltage . The transsince it is assumed mission line is represented by a block that only transport delay and attenuation occurs in the cable. block is obtained from the motor model, such that The is defined as shown at the bottom of the page. Similarly, the block is obtained such that . The computation is performed sequentially, as indicated by a large arrow in Fig. 6. By adding up the inputs and outputs of
1SIMULINK

MATLAB, The MathWorks, Inc., Natick, MA, 2000.

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Fig. 6.

Simulation block diagram for invertercablemotor system with MATLAB/SIMULINK.

Fig. 7. (a) Inverter output voltage (upper u(t)) and its corresponding motor terminal voltage (lower v (l; t)) with the conventional PWMsimulation result. (b) Inverter output voltage (upper v (t)) and its corresponding motor terminal voltage (lower v (l; t)) when there is a V =2 level  duration at each transitionsimulation result.

blocks, we obtain the motor terminal voltage . In the same way, by adding up the injected voltage and the inputs blocks, we obtain the voltage at and outputs of the inverter output terminal. In general, it is difficult to obtain , by taking the inverse Laplace transformation of , .

Fig. 7 shows two simulation results with the conventional PWM method [Fig. 7(a)] and with the proposed PWM method [Fig. 7(b)]. Note from the upper part of Fig. 7(b) that the center voltage lasts for at each rising and falling PWM transition. A significant reduction in voltage overshoot is achieved with the proposed method.

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Fig. 8. Gate signal generation scheme for auxiliary IGBT switches.

Fig. 9. IGBT gating pulses and inverter output PWM voltage pattern in the case of current flow (a) out of the inverter and (b) into the inverter.

V. GATING SIGNAL IMPLEMENTATION EXPERIMENTAL RESULTS

AND

For the experiment, the main inverter legs were constructed with 50-A/600-V IGBTs. Fig. 8 shows the gating signal generation scheme for the main switches and the auxiliary switches. The current rating of the auxiliary switches needs to be the same as the main switches, but the voltage rating of the auxiliary switches is a half that of the main switches. The pair of signals , are regular PWM patterns, with a deadtime of . Gating pulses , are generated during the deadtime interval, and the pulse duration is . There are negative edge-triggered monostable multivibrators, which generate the pulses with a dujust after the negative edges of PWM pulse or . ration of and OR The outputs of the pulse generators are shifted by gated with the direct outputs to make the desired signals , .

Fig. 9 shows the gating logic signals for , , , along when the phase current is positive with the pole voltage [Fig. 9(a)] and negative [Fig. 9(b)]. Note that auxiliary gating signals occur during the deadtime interval. Note also that pulse is always close to the edges of pulse , while pulse is always close to the edges of pulse . However, no deadtime exists between the main gating signals , and the auxiliary gating signals , . The deadtime is unnecessary, since both auxiliary switches are not turned on at the same time. The above gating logics can be implemented by the erasable programmable logic device (EPLD) or the field-programmable gate array (FPGA). Voltage utilization may differ, due to the existence of the level. However, the voltage error is less than the error caused by the deadtime interval. For our experiment, we utilized the 2.2-kW induction motor and the 100-m 2.0-mm PVC cable, whose parameters were used in the previous simulation. Fig. 10

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(a)

(b)

Fig. 10. (a) Inverter output voltage (upper u(t)) and its corresponding motor terminal voltage (lower v (l; t)) with the conventional PWMexperimental result. (b) Inverter output voltage (upper v (t)) and its corresponding motor terminal voltage (lower v (l; t)) when there is a V =2 level  duration at each transitionexperimental result.

shows the experimental results. Comparing it with Fig. 7, one can see that the experimental results are similar to the simulation results.

VI. DISCUSSION AND CONCLUSION Our proposed method is to insert a step at every transition of PWM voltage for , where represents the transport delay time. Note that is determined by the characteristic impedance and length of the cable. Hence, it may be difficult to obtain an accurate in many practical cases. However, in practical situations, it is advisable to directly adjust the pulse duration for auxiliary switches so that voltage overshoot is minimized, rather than trying to obtain from the electrical characteristics of the motor feeding cable. Conventional methods to attenuate the problem of voltage overshoot are to utilize an RLC filter at the inverter side, or an RC filter at the load side. However, passive filters are usually bulky and take up a large amount of space. Further, the RLC filter is not so adaptable to the change of environments, such as variation in cable length. With this proposed method, however, all that is required to adapt to changed conditions is to adjust . This adjustment of the duration can be the duration of easily accomplished by changing a parameter of the inverter. In other words, it does not require any hardware change. On the other hand, the downside of the proposed method lies in the fact that it utilizes an additional six IGBT switches. Although its voltage rating is half of the main IGBT, the manufacturing cost will be higher. If a user-specified power converter structure assembly is made, with the advance of IGBT package technology, it is competitive with other overvoltage suppressing

schemes. Nevertheless, further study is needed on the issue of eliminating additionally required auxiliary IGBTs. It has been shown through analysis that voltage overshoot at the motor terminal can be attenuated below 15% in most cases. Simulation and experimental results support the usefulness of the proposed idea. REFERENCES
[1] E. Persson, Transient effects in application of PWM inverters to induction motors, IEEE Trans. Ind. Applicat., vol. 28, pp. 10951101, Sept./Oct. 1992. [2] P. Van Poucke, R. Belmans, W. Geysen, and E. Ternier, Overvoltage in inverter fed induction machines using high frequency power electronic components, in Proc. IEEE APEC94, 1994, pp. 536541. [3] A. von Jouanne, D. A. Rendusara, P. N. Enjeti, and J. W. Gray, Filtering techniques to minimize the effect of long motor leads on PWM inverter-fed AC motor drive systems, IEEE Trans. Ind. Applicat., vol. 32, pp. 919926, July/Aug. 1996. [4] R. J. Kerkman, D. Leggate, and G. L. Skibinski, Interaction of drive modulation and cable parameters on AC motor transients, IEEE Trans. Ind. Applicat., vol. 33, pp. 722731, May/June 1997. [5] C. J. Melhorn and L. Tang, Transient effects of PWM drives on induction motors, IEEE Trans. Ind. Applicat., vol. 33, pp. 10651072, July/Aug. 1997. [6] A. von Jouanne and P. N. Enjeti, Design considerations for an inverter output filter to mitigate the effects of long motor leads in ASD applications, IEEE Trans. Ind. Applicat., vol. 33, pp. 11381145, Sept./Oct. 1997. [7] G. Skibinski, R. Kerkman, D. Leggate, J. Pankau, and D. Schlegel, Reflected wave modeling techniques for PWM AC motor drives, in Proc. IEEE APEC98, vol. 2, 1998, pp. 10211029. [8] E. Zhong, T. A. Lipo, and S. Rossiter, Transient modeling and analysis of motor terminal voltage on PWM inverter-fed AC motor drives, in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 1, 1998, pp. 773780. [9] P. T. Finlayson, Output filters for PWM drives with induction motors, IEEE Ind. Applicat. Mag., vol. 4, pp. 4652, Jan./Feb. 1998. [10] T. G. Habetler, R. Naik, and T. A. Nondahl, Design and implementation of an inverter output LC filter used for dv=dt reduction, in Proc. IEEE APEC99, vol. 2, 1999, pp. 12791284.

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Sangcheol Lee (S01) was born in Taegu, Korea, in 1970. He received the B.S. and M.S. degrees in electrical and electronic engineering in 1994 and 1996, respectively, from Pohang University of Science and Technology, Pohang, Korea, where he is currently working toward the Ph.D. degree in electrical and electronic engineering. He was with the Power Electronics Team, POSCON, Seoul, Korea, and the Mechanical and Electrical Engineering Team, Pohang Research Institute of Science and Technology (RIST), Pohang, Korea. His main research interests are power converter/inverter systems, passivity-based control, and hybrid system control.

Kwanghee Nam (S83M86) was born in Seoul, Korea, in 1956. He received the B.S. and M.S. degrees in chemical technology and control and instrumentation engineering from Seoul National University, Seoul, Korea, in 1980 and 1982, respectively, and the M.A. and Ph.D. degrees in mathematics and electrical engineering from the University of Texas, Austin, in 1986. He is currently a Professor in the Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea. He served as director of the POSTECH Information Research Laboratories and Dean of the Graduate School of Information Technology from 1998 to 2000. His main interests are ac motor control, power converters, computer networks, and nonlinear systems analysis. Prof. Nam received a Best Paper Award from the IEEE Industrial Electronics Society in 2000.