8.

Phase-Locked Loop
(Lab Guide for X37LBR)

In this lab you investigate phase-locked loop operation using the well known 74HC/HCT4046 PLL integrated circuit and an external divide-by-n counter. The experiment comprises design of circuit parameters, choice of used components, and circuit performance verication.

Lab Assignment
1. Prostudujte si prilozene obvodove schema zapojen fazoveho zavesu s integrova ny obvody 74HC/HCT4046 a 74HC/HCT4059 a jeho realizaci na propojovacm mi poli. 2. Urcete hodnoty prvku R1 , R2 a C1 tak, aby bylo mozne napetm rzeny oscila tor obvodu 74HC/HCT4046 preladovat s urcitou rezervou v rozsahu od 2 MHz do 3 MHz. 3. Zmerte prevodn charaktristiku VCO, tj. zavislost vy stupnho kmitoctu VCO na rdicm napet VCO. Obvodove prvky R1 , R2 a C1 korigujte tak, aby VCO splnoval pozadavek na preladen z predchozho bodu zadan. Urcete citlivost laden (zisk) oscilatoru Ko . 4. Navrhnete hodnoty prvku R3 , R4 a C2 pasivnho ltru smycky PLL. 5. Promerte prenosovou funkci systemu PLL. 6. Promerte odezvu systemu PLL na skokovou zmenu kmitoctu. 7. Vypoctete prenosovou funkci systemu PLL a odezvu systemu PLL na skokovou zmenu kmitoctu. Vy sledky porovnejte s namereny hodnotami z predchozch mi ukolu meren.

Instruments
Generator HP33120A Cslicovy osciloskop Napajec stabilizovany zdroj stejnosmerneho napet Kontaktn pole s obvodem PLL
Revision 1.0.0 z 28. dubna 2008

 PC & Matlab

Bibliography
[1] Gardner,F. M.: Phase Lock Techniques. 2nd edition, Wiley, New York 1967. [2] Best,R. E.: Phase-Locked Loops Design, Simulation, and Applications. 5th edition, McGraw-Hill 2003. [3] : 74HC/HCT4046 Phase-locked-loop with VCO Product specication. Philips Semiconductors 1997. [4] : 74HC/HCT4059 Programmable divide-by-n counter Product specication. Philips Semiconductors 1998.

Contents
1 Introduction 1.1 Mixed-Signal PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 PLL Performance in the Locked State . . . . . . . . . . . . . . . . . . . . . 2 Construction and Measurement 2.1 Phase Locked Loop Design . . . . . 2.2 Voltage Controlled Oscillator Design 2.3 Low-pass Filter Design . . . . . . . 2.4 Frequency Response Measurement . 2.5 Transient Response Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6 6 7 7 8 9

Laboratory 8 Phase-Locked Loop

1 Introduction
The rst Phase Lock Loop (PLL) was proposed in 1932 by French engineer de Bellescize, who is considered the inventor of coherent communication. However, the PLL found broader industrial applications in 60s when it become available as an integrated circuit. Today, the PLL is key component of modern communication systems, where it has many different applications such as frequency synthesizers, FM demodulators, carrier synchronization, carrier recovery, frequency division and multiplication etc. Generally, the PLL is a circuit synchronizing a self-generated output signal with a reference or input signal in frequency and phase. In the synchronized state (locked state) the phase error between the output signal and the reference signal is zero or constant. If a phase error occurs, a PLLs control mechanism acts on produced output signal in such a way that the phase error is minimized this is why it is reffered to as a phase-locked loop. There are basically four classes of PLL: the linear or analog PLL (LPLL), the digital PLL (DPLL), the all-digital PLL (ADPLL), and the software PLL (SPLL). In this lab, we will deal with so called mixed-signal PLL that are hybrids of both linear and digital circuits. Such type of PLL belongs to the group of DPLL.

1.1 Mixed-Signal PLL

The mixed-signal PLL is a negative feedback control system comprising of phase detector (PD), loop lter (LF), voltage-controlled oscillator (VCO), and frequency divider 1/N see Fig. 1. The function of the phase detector is to generate an output waveform based on the phase and frequency difference between the VCO output signal divided by frequency divider and a xed reference. The phase detector is followed by a loop lter, a low pass lter, whose function is to lter out high frequency components from the phase detector output and to produce voltage controlling the VCO.

Figure 1. Basic phase-lock loop diagram

Phase detector

A phase detector is circuit which produces voltage that is proportional to the phase and frequency difference between two input signals. In mixed-signal PLL, four basic types of phase detectors are used: the multiplier phase detector, the EXOR gate, the edge-triggered JK-ipop, and the phase-frequency edge-triggered detector with tristate output. The basic characteristic of phase detector is plot of averaged output signal versus phase error between input signals. For small phase error the averaged output voltage Vd is exactly proportional to phase error e and can be written as Vd = Kd e = Kd (1 2 ) (1) where the Kd is phase detector gain. The dimension of Kd is radians per volt (rad/V) and the Kd is determined by the type of phase detector, input voltage for multiplier phase detector, and the logic levels for the digital detectors. For example, the phase-frequency edge-triggered tristate output detector gain is computed by V1 V0 Kd = (2) 4 3

X37LBR Laborator radiove komunikacn techniky where the detector output logic levels are V1 or V0 , respectively. Note that the bonus offered by this type of detector is its ability to produce the average output voltage varying monotonically with the frequency error. For this reason the phase-frequency detector is the prefferred phase detector in PLLs. Besides, the PLL lock range of this detector is egual to the capture range and is independent of the low pass lter.
Loop lter

The output signal of the phase detector in locked state consists of a DC component and a variety of AC componets having frequencies of nc , where c is input signal frequency, n = 1, 2, ... These higher frequencies are unwanted signals, therefore, they are ltered out by the loop lter a low-pass lter. In most PLLs a rst-order low-pass lters are used. We can use the higher-order loop lters to improve some PLL parameters but loop stability becomes issue. Moreover, we can split the lters to passive variants, where only passive components are used, and active variants, where an amplier is a key part of the lter. The passive lter is quite simple and often satisfactory for many purposes. The active lter requires high gain DC amplier but provides better tracking performance. Next we will pay our attention only to a passive so-called lead-lag lter having one pole and one zero see Fig. 2. Its transfer function is given by F (s) = 1 + s2 1 + s(1 + 2 ) (3)

where 1 = R1 C and 2 = R2 C. The amplitude and phase response (Bode diagram) is shown in Fig. 2.

Figure 2. Frequency response of lead-lag lter

Voltage Controlled Oscillator

As the name explains, the VCO produces a periodic signal, the frequenncy of which is proportional to the input control voltage V2 and is given by 2 = 0 + Ko V2 (4)

where Ko is called VCO gain (its unit is radians per volt per second) and 0 is the center frequency of the PLL. The VCO output frequency varies in proportion to the control voltage over range which is restricted between a lower and upper threshold min , max . Between these thresholds the VCO characteristic is linear. The control voltage should not pull out of this range. The designer of PLL must ensure the sufcient frequency range of VCO and determine the VCO gain. All parameters can be derived from the basic characteristic of VCO plot of the VCO frequency versus VCO control voltage. 4

Laboratory 8 Phase-Locked Loop

Frequency dividers

Frequency dividers can be omitted in some PLL designs, but they come into play when the PLL is used as a frequency synthesizer. The frequency divider divides the VCO output frequency by a factor N , which is commonly programmable. In this case, the relation between phase detector input signal frequency 1 and VCO frequency 2 simply follows 2 = N 1 (5) where the factor N can be an integer number only we talk about integer-PLLs or noninteger number we talk about fractional-N PLLs or fractional-N frequency synthesizers.

1.2 PLL Performance in the Locked State

The Laplace transform permits the representation of the PLL response in the complex s-domain. We start with the model of PLL in Fig. 1. This model enables us to analyze the tracking performance of the PLL in locked and near-locked state, i.e., the ability of the PLL to maintain phase tracking when excited by phase step, frequency step, or other excitation signals. By using the Laplace transform the following equations hold Vd (s) = Kd (1 (s) 2 (s)) V2 (s) = Vd (s)F (s) 2 (s) = V2 (s)Ko /s 2 (s) = 2 (s)/N (6) (7) (8) (9)

Note that the frequency is the derivative of phase and thus the VCO operation may be described by (8); the phase of the VCO output is proportional to the integral of the input control voltage. Combination of these equations results in the basic loop characteristics: closed loop phase-transfer function H(s) Ko /sKd F (s)/N Ko Kd F (s)/N (s) = = (10) H(s) = 2 1 (s) 1 + Ko /sKd F (s)/N s + Ko Kd F (s)/N and error transfer function He (s) He (s) = 1 (s) 2 (s) e (s) 1 s = = = 1 (s) 1 (s) 1 + Ko /sKd F (s)/N s + Ko Kd F (s)/N (11)

which relates phase error e to the input phase 1 . Note that H(s) + He (s) = 1. According to control loop theory, the closed loop transfer function for a specic input anywhere in the loop is given by the forward loop gain (from that input to the output) divided by 1 + the total open loop gain. Equation (10) proves this rule. Two terms are used in literature to specify PLL systems: type and order. The type of the PLL system refers to the number of poles located in the origin of the second term in the denominator of (10), that is Ko /sKd F (s)/N . The order of the PLL system refers to the highest power of s of the polynomial expression 1 + Ko /sKd F (s)/N = 0 (12) which is called the characteristic equation. The roots of the characteristic equation become the closed loop poles of the transfer function.
PLL with passive lead-lag lter

For the passive lead-lag lter the closed loop transfer function is given by Ko Kd 1 + s2 N 1 + 2 H(s) = 1 + 2 Ko Kd /N Ko Kd /N s2 + s + 1 + 2 1 + 2 (13)

X37LBR Laborator radiove komunikacn techniky and thus it is the second order PLL system. This closed loop transfer function may be rewritten as sn 2 H(s) = n 2 + n Ko Kd /N 2 s2 + 2sn + n

(14)

in which n is the natural frequency of the loop and is the damping factor n = 1 2 Ko Kd N (1 + 2 ) 2 + N Ko Kd (15)

Ko Kd N (1 + 2 )

(16)

well known parameters from servo system theory. The transfer function H(s) has a well-dened 3dB bandwidth but there is very little reason to be interested in this parameter.

2 Construction and Measurement

2.1 Phase Locked Loop Design
The design of a PLL typically involves determining the type of the loop required, selecting the proper bandwidth, and establishing the desired stability. It is desired for the system to fulll the following specications and requirements: frequency range or tuning bandwidth, step size or frequency resolution, phase noise requirements, spurious signal levels, loop bandwidth and dynamic speed of the feedback loop, switching speed or locking time, etc. Other parameters deal with size, power, supply voltage, control interface, temperature range and, surely, reliability. A detailed design of PLL system is beyond the scope of this lab see [1], [2] for this objective. We will focus only on simplied design of the second order phase lock loop with passive lead-lag lter taking full advantage of well known PLL IC 74HC/HCT4046 [3]. Suppose that we design frequency synthesizer with following specications: Output frequency range from 2 MHz to 3 MHz Frequency synthesis step 100 kHz Reference frequency equals to synthesis step, that is 100 kHz Scaler ratio N varies from 20 to 30 Lock up time between adjacent channels 1 ms Overshot lower that 20 percent The circuit diagram of our phase lock loop system is shown in Fig. 3. The phase locked loop integrated circuit 74HC/HCT4046 comprises a linear voltage controled oscillator and three different phase comparators. We use phase comparator 2 (PC2), which is a positive edge-triggered phase and frequency detector with tristate output. Thus the loop is controlled by positive signal transitions and the duty cycles of SIGIN and COMPIN are not important. It should be noted that the PLL lock range for this type of phase detector is egual to the capture range and is independent of the low-pass lter. The phase-frequency detector gain is given by Kd = VCC 4 [V/rad] (17)

where VCC is IC power supply voltage. The passive lead-lag lter R3 , R4 , C2 is connected directly between phase-frequency comparator output PC2 and high-impedance VCO input. The VCO is set by 6

Laboratory 8 Phase-Locked Loop

Figure 3. PLL circuit the values of R1 , R2 , and C1 in order to be tunable from 2 MHz to 3 MHz. The VCO output feeds programmable divider 74HC/HCT4059 [4]. This IC is a divide-by-n conter which can be programmed to divide an input frequency by any number from 3 to 15999. In our design the counter runs in mode 10 (see datasheet for details) and only two least signicant decades are used to set the division ratio N where N = 10 (23 J8 + 22 J7 + 21 J6 + 20 J5) + (23 J4 + 22 J3 + 21 J2 + 20 J1) (18)

The output of programmable divider is connected to phase-frequency comparator input COMPIN . The external sine wave generator drives the second phase-frequency comparator input SIGIN via capacitive coupling Cc . Since the passive lead-lag lter output is sensitive to capacitive load we use DEMOUT demodulator output of 74HC/HCT4046 VCO section to measure VCO control voltage test point TP1.

2.2 Voltage Controlled Oscillator Design

The 74HC/HCT4046 VCO requires one external calacitor C1 between C1A and C1B and two external resistors R1 and R2 between R1 and ground, and R2 and ground. Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. A guide for the approximation of values of external components C1 , R1 , and R2 can be found in IC datasheet [3], where parameters fo = (3 + 2)/2 MHz = 2.5 MHz and fL = (3 2)/2 MHz = 500 kHz. Find the approximation values of C1 , R1 , and R2 for reguired VCO frequency range. The obtained values are only approximative. Plug the C1 , R1 , and R2 to 74HC/HCT4046 and run the VCO. Use the trimmer Rv to vary the control voltage at pin 9 from 0 to Vcc and check the VCO frequency range by digital oscilloscope. The loop lter is disconnected in this part. Change the values of C1 , R1 , or R2 to obtain required frequency range with small reserve (for example 100 kHz over required frequency range). Write down new values of C1 , R1 , and R2 and measure the frequency characteristic of VCO, i.e. the VCO output frequency versus input control voltage. Plot measured frequency characteristic and determine VCO gain Ko from linear part of this characteristic.

2.3 Low-pass Filter Design

The low-pass lter located between the phase detector output and the VCO input is another key part of the PLL which enables to establish the overall loop characteristic. We have to nd proper values of and n to meet the overshot and lock-up time requirements. Noise is not of concern in this PLL design, so the PLL noise parameters are discarded. 7

X37LBR Laborator radiove komunikacn techniky At this point we are appreciative for software tools help or we can use precalculated results/plots from literature [gardner], [best]. It can be seen that the damping factor 0.7 will ensure an overshoot of less than 20 % where the acceptable damping factor between 0.5 and 1.0 is recommended for second order PLL with lead-lag lter. The lesser damping ratio the longer settling time, therefore, we choose = 0.7 to ensure the in recommended range for different division ratio N . The settling time TL is given by approximative equation 2 TL = (19) n thus the resultant values for damping factor and natural frequency are n = 6300 rad/s = 0.7 for Nmean = . Nmin Nmax = 24. (20)

Because the passive lead-lag loop lter is selected, the formula (15) for n can be used to calculate the sum 1 + 2 . The maximum overshoot occurs at Nmax , thus 1 + 2 = Now the 2 can be calculated from (15), (16) 2 = 2n (1 + 2 ) 1 Ko Kd 1/N (22) Ko Kd /Nmax 2 n (21)

Given 1 and 2 , the loop lter components R3 , R4 , and C2 can be simply determined. For optimum noise immunity of loop lter, capacitor C2 should be chosen as large and resistors R3 , R4 as low as allowed by phase comparator output. Then R4 = 2n (1 + 2 ) 1 Ko Kd 1/N C2 1 + 2 R4 C2 (23) (24)

R3 =

Calculate 1 , 2 and values of R3 and R4 for C2 = 470 nF. Use Matlab code to plot Bode diagram for designad passive lead-lag lter. Matlab code: >> >> >> >> >> >> >> >> s = tf(s); R1 = 2000; R2 = 390; C = 10e-9; tau1 = R1*C; tau2 = R2*C; F = (1 + s*tau2)/(1 + s*(tau1 + tau2)); bode(F)

2.4 Frequency Response Measurement

Firstly, we will measure closed loop gain transfer function. A direct method of determining frequency response would utilize the phase modulated signal generator and phase detector see [gardner], however simpler alternative methods are to be preffered. One of such alternative is to utilize a frequency-modulated signal generator and the test setup illustrated in Fig. 4. We utilize the fact, that the frequency sinemodulated signal is equal to phase-modulated signal clearly, the derivative/integration of sine wave is again sine wave but with different phase and amplitude. Therefore, this technique simply determines 8

Laboratory 8 Phase-Locked Loop frequency response to within an arbitrary gain constant. However, it is known that H(j0) = 1, thus the value of gain constant is unimportant only the shape of H(j) is needed. Measure the AC voltage amplitude at pin 10 of 74HC/HCT4046 for different modulating frequency. Plot the amplitude of closed loop transfer function H(j) versus frequency. Change the capacitor C2 in the loop lter to 10 nF and repeat measurement. Again, plot the amplitude of closed loop transfer function H(j) versus frequency.

Figure 4. Frequency response measurement using FM signal generator

2.5 Transient Response Measurement

Linear transient response measurement is performed by using the same test arrangement shown for frequency response measurement. All that is required is that the test input voltage has the appropriate waveshape rather than the sinewave used for requency response measurement. We use FSK signal with f1 = 100 kHz, f2 = 110 kHz, and repetition 100 Hz. Measure the step response at pin 10 of 74HC/HCT4046 for C2 = 470 nF. Change the capacitor C2 in the loop lter to 10 nF and repeat measurement. Draw both step responses to your exercise book, determine the overshoot and try to read natural frequency from ringing period. Compare results.