PERFORMANCE COMPARISON OF STEPWISE PARALLEL AND SERIAL CELL SEARCH IN WCDMA

Eung Bae Kim', Moon Kyou Song2

I ETRI, Daejon 305-350, KOREA, ebkim@etri.re.kr Wonkwang University, Jeonbuk 570-749, KOREA. mksong@wonkwang.ac.!a

Abstract - For three-step cell search in WCDMA system, a stepwise serial scheme is conventionally employed, where each step operates in serial. In order to reduce cell search time, a stepwise parallel cell search scheme can be considered, where each step works in pipelined operation. However, in this parallel scheme where the processing time in every step is equal, excessive accumulations are caused in step (1) and step (3), because the code period for step (2) is much longer than those for the other steps and the effect of accumulations becomes saturated with the number of accumulations. This will reduce benefit of the parallel scheme. In this paper, the performance of parallel cell search is analyzed and compared with that of serial cell search over Rayleigh fading channels. The results are presented for varying parameters. Finally, it is shown that the performance of parallel cell search can he improved by adjusting appropriately the processing time in each step. Keywords - Acquisition, cell search, spread spectrum, synchronization, WCDMA

A parallel scheme has been also considered in [ 5 ] . The performance analysis of cell search is helpful to optimize the values for cell search parameters. While the performance analysis for a serial scheme has been presented in [4], the performance of a parallel scheme has never been dealt with through an analytic method. In this paper, the performance of a parallel cell search in WCDMA will be analyzed over Rayleigh fading channels. And the result will be used to investigate the effect for varying values of cell search parameters, and it will be compared with that of a serial scheme. Finally, we will try to improve cell search performance by choosing the relevant parameter values carefully, based on the analytic results. 11. SERIAL AND PARALLEL CELL SEARCH During cell search process, a MS searches for the best cell and determines the downlink scrambling code and the frame synchronization of that cell. Cell search is typically carried out in three steps[2]. : ( I ) slot synchronization, (2) frame synchronization and code group identification, and (3) scrambling code identification. In step (I), a MS uses the PSCH (primary synchronization channel)'s PSC (primary synchronization code) to acquire slot synchronization to the best cell having the largest power received at the MS. In step (2), a MS uses the S-SCH (secondary synchronization channel) sequences to find frame synchronization and the code group for the cell found in step (1). The CP code used as a S-SCH sequence has the property that the cyclic shift is unique. Hence, the code group and the frame timing can be identified simultaneously by using it. In step (3), a scrambling code is identified through exhaustive correlations over the P-CPICH (primary common pilot channel) with all the scrambling code candidates within the code group identified in step (2). If a scrambling code is identified successhlly, the cell search is completed. The 3-step cell search can be performed in either a serial nr parallel manner. When the cell search fails at the end of each step, the control flow should retum to the beginning and repeat the whole cell search process in a serial scheme. On the contrary, in a parallel scheme, it is sufficient to repeat only the failed step, as every step always runs concumently to be ready to produce outputs.

I. INTRODUCTION In Code Division Multiple Access (CDMA) systems, a mobile station (MS) needs to code and time-synchronize to the scrambling code used by the serving cell before any communications with the base station can take place[l]. This process is called as cell search. The cell search in WCDMA consists of 3 steps. Each step is typically performed in serial [11,[31,[4], where the control is retum to the beginning in case of a failure in each step. On the contrary, the pipelined operation among the steps can also be considered for cell search. Here, all steps are running concurrently to produce the results for the following step, so that a new output from the previous step might be immediately available in case of a decision failure in each step. In this paper, the former will be called as serial cell search and the latter as parallel. As the cell search performance depends strongly on the receiver design parameters such as the number of accumulations and the system parameters such as charnel power allocation, the performance analysis is very useful to design a receiver with improved cell search performance. A serial scheme has been dealt with in [ 1-41,

0-7803-8523-3/04/$20.00 02004 IEEE

.~

11

SearchStan

Slot synchronization [PSC matched filter)

very L,slot

Frame synchmnimion & code ~ m idintification p

identification (scnmbiing code comlarions)

rmrr Or false alarm

Fig. 1 The operational flow of 3-step parallel cell search

111. PERFORMANCE ANALYSIS In this section, we will analyze the cell search performance over a Rayleigh fading channel. The cell search time is defined as the total latency that is required from the beginning of cell search to the end of step (3). The minimum cell search time should he no longer than 48 slots because of clock drift[5]. This corresponds to 1/4 chip error for clock oscillators of 2ppm (parts per million). Cell search process can he regarded as a series of spreading code acquisition. Assuming that the Rayleigh fading is slow enough that the amplitude as well as the phase remain constant over the dwell duration at each step, hut fast enough that successive dwells are independent, cell search acquisition can he modeled as Markovian so that a flow graph model can he used for analyzing the aquisition performance[7-91. Fig. 2 illustrates a signal flow graph for a parallel scheme. The probability of occurrence and the latency time is denoted at each branch in the flow graph. The exponent of a variable z means the latency time for the process of the corresponding branch, which has the time unit of Tsi,/2. The K represents a false alarm penalty time. The Hi means a hypothesis that a correct signal is present at a testing dwell output. For step (l), it implies that the received signal is aligned within one chip. For the other steps, it means that the previous step has been camed out successfully. That is, HI in step ( 2 ) means that a correct slot synchronization has been acquired in step (l), and HI in step (3) represents that a correct code group has been found in step (2). The Ho

represents the alternative hypothesis. Maximum likelihood (ML) decision is carried out in each step, where the probabilities of detection PD;,miss PM; and false alarm PF,in the ith step are respectively defined as follows : PD = Pr { one of outputs for correct test cells is the maximum, and it is greater than the threshold) PA, = Pr { there is no test cell output which is greater than the threshold} PF = Pr { one of outputs for incorrect test cells is the maximum, and it is greater than the threshold) PMjlHi and PF;lHi represent the conditional The PDilH;, probabilities on condition that a hypothesis Hj, 0' = 0 or 1) has been given for the ith step [4]. Now, we consider the signal flow graph shown in Fig. 2. Each step consists of a start point, a decision point and an end point. After correlations and post-detection integrations have been camed out between start and decision points, a ML decision is performed based on the correlation result at the decision point. According to the decision, the direction of a process is divided. In cases of correct detection and false alarm, the control will proceed to the next step. In case of a miss event, however, the corresponding step needs to be repeated. For convenience of description, we will use the notation of A-B to denote the path from point A to point B. In step ( l ) , slot synchronization is acquired with a matched filter or any similar device matched to the PSC. As the PSC is repeated once at evely slot, it takes L I slot times to carry out L , accumulations in step (1). And this process corresponds to A-B from the start point A to the decision point B in Fig. 2. The ML slot timing can be obtained by detecting a peak among nriO, candidate outputs of the matched filter, which is also greater than the threshold SI, where nYi,,=2560 is the'numher of chips within a slot. If the decision is either a correct detection or a false alarm, then the flow will proceed to step ( 2 ) (B-C or B-D). However, if the decision turns out to be a miss, the flow will be returned to the beginning of step (1) and restart a new cell search process (B-A). If the threshold is typically set as zero to make the miss probability into zero, the feedback path 0fB-A disappears.

Fig. 2 Signal flow graph for a parallel scheme

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Once step (1) has been finished, a slot synchronization point is obtained, and step (2) should begin from that point. There are two candidate start points E and F for step (2), which respectively corresponds to a correct detection or a falsealarm. As the end point C or D of step (1) is generally different from the point E or F, a MS should wait until the proper slot synchronization point can be met while receiving an incoming signal. With no prior information, it can be assumed that all nrb,candidates are equally likely to be the start point of step (2). Thus, it takes average latency time of T,/,,/2 for transition (C-E or D - Q before step (2) begins. The Stan point E for a correct detection in step (1) is then corresponding to a HI cell for step (2), and the false alarmed start point F is to a Hacell. In step (2), a received signal is correlated in parallel with all possible S-SCH sequences which consist of M=15 SSCs. To accumulate the correlation results with S-SCH sequences by L2times, the correlation dwell with a SSC code (secondary synchronization codes) should be repeated L2M times in step (2). As the length of S-SCH sequence and the number of slots in a frame are the same as M, and a SSC is transmitted once in each slot, it takes L2M slot times for the Lz accumulations of a S-SCH sequence (E-G or F-H). Then, a ML decision is made at the decision point G or H of step (2) to obtain the frame synchronization and the code group identification at the same time. In case that a S-SCH sequence is correctly detected or falsely alarmed at the decision point G corresponding to a HI cell for step (2), the process will proceed to step (3) as G -I with probability of PD2pl G-J with PRIHI. is or This just the same case for the decision point H corresponding to a Hacell for step (2). Namely, the path from point H divides into two paths, where H-I is for a correct detection with probability ofPD21m, and H-tJfor a false alarm with P , q ~ u . As every step runs concurrently in parallel cell search, a new decision result of step (1) is already available when the decision in step (2) is made. Therefore, when a miss event happens at the end of step (2), a MS can immediately use the new available result from step (I) instead of returning to the beginning. That is, returning to point B (G-B or H+B) is sufficient to get a new slot synchronization point. If a correct S-SCH sequence is chosen in step (2), a comect scrambling code group and frame synchronization can be obtained. Whether the acquired frame synchronization point is correct or not, it will be the start point of step (3) (point K or L). Before step (3) begins, it is necessary to wait until the received signal amves at the acquired frame start point. It takes multiples of a slot time in range of 0 to M-1 slot times for this transition ( I P K or J-L). The average transition time is (M-1)&0J2 as the probability that each slot would be the start slot of a frame is the same. In step (3) (K M or L N), the scrambling code is identified through symbol-by-symbol correlation over the P+

CCPCH with all scrambling codes belonging to the code group identified in step (2). After L, accumulations, the maximal correlation value which exceeds the threshold S , indicates the transmitted scrambling code. It takes L3 slot times for this process. If a correct scrambling code is chosen at the decision point M which corresponds to a HI cell for step (3), cell search is successfully completed (M-0). In case that a wrong code group is selected in step (2), the decision is made at the decision point N, which corresponds to a Ho cell for step (3). Here, there is no possibility that a correct scrambling code would be selected. So the path N+ 0 does not exist in Fig. 2. If a false alarmed scrambling code is selected at point M o r N as a result of step (3), the flow goes to the end point P ( M -P or N-P). After the false alarm penalty time K is elapsed, the flow will return to the decision point Mor N ( P -M or P-N) to utilize a new result of step (3) that will he available at the point M o r N through the stepwise pipelined operation. Remember that point M is corresponding to the case that a correct code group is selected in step (2) and point N is a result of false alarm in step (2). Denoting the probability and from point P to each point Mor IV as Pnr P,v respectively, these can be described respectively as follows : p ,

=%
AD

(1)

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Denoting the probabilities that the flow returns to point G and H as Pc and PHrespectively, each is simply the same as the transfer probability from the beginning point A to either point G or H. Thus, Pc and PHcan be written respectively as

Using the transfer function of a signal flow graph, the average time and its variance for cell search can be obtained[7-91. Denoting the transfer function for parallel scheme as U,(z), it can be obtained as follows :

where P , ( ~ and )

AJZ)

are given by eq. (9) and (lo), and

= 2Lj + M - 1

(11) The average cell search time roc,, given by substituting is z=l into the first order derivative of UD(z)[7-S].

a = ZL, , p= 2L:M + I , y

The Po&) defined as the probability that cell search is completed before n unit times can be obtained by [7]

Eqs. (12) and (13) has the time unit of T,,,,J2. Comparing Fig. 2 with the result for the serial scheme in [4], the difference between parallel and serial schemes is the next step from which the cell search restarts when the decision at each step fails.
W . NUMERICAL RESULTS In this section, we will compare the performance of serial and parallel cell search numerically over Rayleigh fading channels. In the following numerical calculations, the

number of samples per each chip is assumed as 1, and the timing error is assumed as 0. The false alarm penalty time is assumed as 250111s. The threshold value for ML decision in each step is set as zero, which means the miss probability is zero. The cell search performance depends on the number of accumulations in each step and the ratio of power allocation among the channels. The latency in each step is directly related to the number of accumulations performed in that step, which is L , slot times for step (l), L2M slot times for step (2), and L3 slot times for step ( 3 ) . The processing time of step (2) is much longer. This is because both step (1) and ( 3 ) operate in a slot base, while step ( 2 ) works in a frame base. Thus, the number of accumulations in step (2) has more influences on the cell search time than any other steps. Hence, it is critical to determine the value of L2. For a serial scheme, L2 = 2 is selected after several numerical trials. This reveals much better performance than no accumulation of L2 = 1. Then, the processing time in step ( 2 ) is 30 slot times. Now it is necessary to choose the combination of values for L , and L,. Because of clock drift, the minimum processing time for cell search has to be bound within 48 slot times. This corresponds to 1/4 chip drift for 2ppm clock employed during the acquisition[4]. Therefore, we limit the minimum processing time as 46 slot times. This can be done by letting the sum of L I and L3 be fixed as 16 for serial scheme. For a parallel scheme, setting L2 = 2 will requires at least 90 slot times for total cell search if the processing time in each step is set to be all equal as in [ 5 ] .If we set L2 = 1, which requires 15 slot times for step (2), then we can make L I = L3 = 15 and the minimum cell search time can be made as 45 slot times. In summary, L2=2 is not appropriate in a parallel scheme, as it results in excessive processing time. Thus, only the case of L2=l will be considered for a parallel scheme. In addition, it is worth to consider the effect of the power allocation ratio among channels such as a and R.The a is the P-SCH loading factor defined as the power ratio of P-SCH to total SCHs, and R is defmed as the power ratio of P-CPICH to total SCHs. As we

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vaty the value of a in 0.1 steps from 0 to 1, we will determine the best value for combination of parameter set (Li, L z , L 3 } .For the values ofR, two cases of 0 and 3 dB are considered. Fig. 3 shows the result of average cell search time obtained for a serial scheme as a function of EJIa based on the PCPICH. Assuming that the target cell search time is within looms, the best choice of the parameters is ~ 0 . and 4 ( L I = l l ,L2=2,L3=5) forR=OdB, and ~ 0 . and {L,=9,L2=2, 4 L3=7) for R=3dB. However, the variation of the parameters near the optimal values does not give critical impact on the performance and the optimal value of a is affected by EJIo. For a parallel scheme, where the processing time in each step is set to be all the same as in [SI, only two combinations of {L,=lS, L2=l, L3= 15) and (Ll=30, L2=2, L3= 3 0 ) are possible candidates. Through the analysis under the same situation as the previous one, it can be seen from Fig. 4 that ~ 0 . shows the best performance for both cases, assuming 3 that the target average cell search time is near looms. In the figure, the dotted curves are included only for comparison purpose, which is the best one for a serial scheme in Fig. 3. Accumulation in step (2) increases the minimum required time for cell search. If the processing time of evely step is the same, accumulation in step (2) will lead to excessive accumulation for step ( I ) and step (3). The effect of accumulation becomes saturated and the cell search time increases as the number of accumulations increases.

As a result, {LI=30, Lz=2, L3= 3 0 ) leads to longer cell search time and vulnerable to clock drift. Comparing Fig. 3 with Fig. 4, a parallel scheme generally outperform a serial scheme. However, it should be noted that this situation can ' he reversed at less than -13dB of E& for R=OdB.
V. ADJUSTMENTS IN PARALLEL SCHEME Although a parallel scheme generally outperform a serial scheme, it may be reversed under certain circumstances. In addition, a parallel scheme has a drawback in terms of power dissipation. Furthermore, as the latency in step (2) is much longer than others, excessive accumulation will be caused in step (1) and (3). If all three steps are successfully performed in a single trial, a parallel scheme is the same as a serial scheme, except that each step runs concurrently. Thus, the performance of a parallel scheme can be improved by appropriately setting the processing time of each step. Now we evaluate the performance of a parallel scheme with each step having different processing time. Fig. 5 shows the result, which is obtained under the same condition as Fig. 3. Again. assuming the target time of looms for cell search, the best choice of parameters for a parallel scheme is a = 0.4 and (L,=l I , Lz=2, L3= 5 ) for R = OdB, and a = 0.4 and {LI=9,L2=2, L3= 7 ) forR=3dB

4'

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Fig. 5 Performance of parallel scheme with unequal processing time for each step; R=OdB

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0.5

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Fig. 4 Average cell search time for parallel scheme with equal processing time for evely step; R=OdB

P-SCH loading factor. n

Fig. 6 The effect of a in 0.1 steps

15

100

200

300

400

Average cell Search lime [msl

Fig. 7 The cumulative distribution function of average cell search time at E,/Io-18dB

As for a parallel scheme having equal processing time in each step, accumulation in step (2) leads to excessive accumulation in steps ( I ) and (3). In addition to causing longer processing time, it provides no gain in performance, particularly at high value of EJIo. As a result, a parallel scheme can be outperformed by a serial scheme. Thus, it is not proper to employ a parallel scheme in such way that each step has equal processing time. By adjusting the processing time of each step properly so that a new outcome might be readily taken from the previous step in case of a failure in each step, the performance of a parallel scheme can be improved. Although there exist many kinds of cell search parameters such as the number of accumulations (or the processing time) of each step and the power allocation ratio between channels, they are all related to each other. Thus, the analysis presented in this paper can be helpful to choose the values of the parameters and improve the cell search performance. AKNOWLEDGEMENTS This research was supported by University IT Research Center Project. REFERENCES

Power ratio of SCHs Io P-CPICH. R [dB1

Fig. 8 Average cell search time against R for Ec/Io=-18dB Fig. 6 shows the effect of a in 0.1 steps. The changes of a has less influence on the performance at higher values of Ed&. The optimal value for a changes according to several factors such as the target cell search time and EJIo. Particularly, it depends strongly on the relative performance between step (1) and (2). The optimal value of a increases as step (2) has better Performance than step (I). Fig. 7 shows the cumulative distribution function of average cell search time at EJIo=-18dB obtained by using eq. (13). Fig. 8 illustrates the average cell search time against R at EJIo= -18dB. It can be seen from Fig. 7 and Fig. 8 that a parallel scheme having equal processing time in each step can have poorer performance than a serial scheme at EJIo = -18dB. Also, we can see that the performance of a parallel scheme can be improved by adjusting the processing time required for each step appropriately. VI. CONCLUSIONS In this paper, we have analyzed the cell search performance of a parallel scheme in WCDMA and compared it with a serial scheme. The effect of parameters such as the number of accumulations in each step and the ratio of power allocation among channels has been taken into account in the analysis.

K. Higuchi, M. Sawahashi, and F. Adachi, "Fast Cell Search Algorithm in Inter-Cell Asynchronous DSCDMA Mobile Radio," IEICE Trans. Commun., vol. ESI-B, no. 7, Jul. 1998. [ 2 ] 3GPP TSG-RAN WG1, "Physical layer procedure (FDD)," TS 25.214 v3.2.0, ETSI, Mar 2000. [31 S. Sriram and S. Hosur, "Cyclically Permutable Codes for Rapid Acquisition in DS-CDMA Systems with Asynchronous Base Stations," IEEE Trans. J Select. Areas Commum., vol. 19, no. 1, pp. 83-94, Jan. 2001. [4] M. K. Song and V. K. Bhargava, "Performance Analysis of Cell Search in W-CDMA Systems over Rayleigh Fading Channels," IEEE Trans. Veh. Technol., vol. 51, No. 4, pp. 749-759, Jul. 2002. [5] Yi-Pin Eric Wang and Tony Ottosson, "Cell Search in W-CDMA, " IEEE Trans. J. Select. Areas Commum., vol. 18, no 8, pp.1470-1481, Aug. 2000. [ 6 ] 3GPP TSG-RAN WG1, "Spreading and Modulation (FDD)," TS 25.213 v3.2.0 ETSI Mar. 2000. [7] A. J. Viterbi, CDMA: Principles o Spread Spectrum f Communication, Addison-Wesley Publishing Co., ch 3, 1995. [E] M. K. Simon, J. K. Omura, R. A. Scholtz and B. K. Levitt, Spread Spectrum Communication, Vol. 111, ch. 1, Computer Science Press 1985. [SI H. Park and B. Kang, "On the performance of a Maximum-Likelihood Code-Acquisition Technique for Preamble Search in a CDMA Reverse Link" IEEE Trans. Veh. Technol., vol. 47, no. 1, pp 65-74, Feb. 1998.
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