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2 128K x 8 SRAMs & 2 512K x 8 Flash Die in One MCM I Access Times of 25ns (SRAM) and 60ns (Flash) or 35ns (SRAM) and 70 or 90ns (Flash) I Organized as 128K x 16 of SRAM and 512K x 16 of Flash Memory with Separate Data Buses I Both Blocks of Memory are User Configurable as 512KX8 AND 1MX8 Respectively I Low Power CMOS I Input and Output TTL Compatible Design I MIL-PRF-38534 Compliant MCMs Available I Decoupling Capacitors and Multiple Grounds for Low Noise I Industrial and Military Temperature Ranges I Industry Standard Pinouts
Note: Programming information available upon request
Equal Sectors of 64K bytes each G Any combination of sectors can be erased with one command sequence
I I I I I
+5V Programing, +5V Supply Embedded Erase and Program Algorithms Hardware and Software Write Protection Internal Program Control Time. 10,000 Erase / Program Cycles
Block Diagram PGA Type Packages (P3 & P7) & CQFP (F18)
Pin Description SWE 1 SCE1 SWE2 SCE2 OE A0 A18 128Kx8 SRAM 8 SI/O0-7 128Kx8 SRAM 8 SI/O8-15 512Kx8 Flash 8 FI/O0-7 512Kx8 Flash 8 FI/O8-15 FWE1 FCE1 FWE2 FCE2 FI/O0-15 SI/O0-15 A018 FWE 1-2 Flash Data I/O SRAM Data I/O Address Inputs Flash Write Enables
SWE 1-2 SRAM Write Enables FCE1-2 SCE1-2 OE NC VCC GND Flash Chip Enables SRAM Chip Enables Output Enable Not Connected Power Supply Ground
Capacitance
(VIN = 0V, f = 1MHz, TC = 25C) Symbol CAD COE CWE1,2 CCE1,2 CI/O Parameter A0 A18 Capacitance OE Capacitance F/S Write Enable Capacitance F/S Chip Enable Capacitance I/O0 I/O15 Capacitance Maximum 50 50 20 20 20 Units pF pF pF pF pF
DC Characteristics
(VCC = 5.0V, VSS = 0V, Tc = -55C to +125C, unless otherwise indicated) Parameter Input Leakage Current Output Leakage Current Sym ILI ILO Conditions VCC = Max, VIN = 0 to VCC FCE = SCE = VIH, OE = VIH, VOUT = 0 to VCC Min Max Units 10 10 325 40 0.4 2.4 130 150 0.45 0.85 x VCC 3.2 A A mA mA V V mA mA V V V
SRAM Operating Supply Current x 16 I x16 SCE = VIL, OE = VIH, f = 5MHz, VCC = CC Max, FCE = VIH Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash Vcc Active Current for Read (1) Flash Vcc Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Low Vcc Lock Out Voltage ISB VOL VOH ICC1 ICC2 VOL VOH VLKO FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max IOL = 8 mA, VCC = Min, FCE = VIH IOH = -4.0 mA, , VCC = Min, FCE = VIH FCE = VIL, OE = VIH, SCE = VIH FCE = VIL, OE = VIH, SCE = VIH IOL = 8 mA, VCC = Min, SCE = VIH IOH = -2.5 mA, , VCC = Min, SCE = VIH
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
2
SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, Tc= -55C to +125C)
Read Cycle
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Enable to Output Valid Chip Select to Output in Low Z * Output Enable to Output in Low Z * Chip Deselect to Output in High Z * Output Disable to Output in High Z * * Parameters guaranteed by design but not tested Symbol tRC tAA tACE tOH tOE tCLZ tOLZ tCHZ tOHZ 3 0 12 12 0 15 3 0 20 20 025 Min Max 25 25 25 0 20 035 Min Max 35 35 35 Units ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Output Active from End of Write * Write to Output in High Z * Data Hold from Write Time Address Hold Time * Parameters guaranteed by design but not tested Symbol tWC tCW tAW tDW tWP tAS tOW tWHZ tDH tAH 0 0 025 Min Max 25 20 20 15 20 0 0 10 0 0 035 Min Max 35 25 25 20 25 0 0 20 Units ns ns ns ns ns ns ns ns ns ns
Truth Table
Mode Standby Read Output Disable Write SCE H L L L OE X L H X SWE X H H L Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
tWP
tWHZ
tOW tDH
DI/O
tAH tCW
SCE
tOHZ
SEE NOTE
DI/O
High Z
Data Valid
UNDEFINED
DONT CARE
AC Test Circuit
Current Source IOL
AC Test Conditions
Parameter Typical 0 3.0 5 1.5 Units V ns V
Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level
Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and I OH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output High Z (1) Output Enable High to Output High Z(1) Output Hold from Address, CE or OE Change, Whichever is First Note 1. Guaranteed by design, but not tested
Symbol 60 70 90 Units JEDEC Standd Min Max Min Max Min Max
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 60 60 60 30 20 20 0 70 70 70 35 20 20 0 90 90 90 35 20 20 ns ns ns ns ns ns ns
Parameter
Write Cycle Time Chip Enable Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation Sector Erase Time Read Recovery Time before Write Vcc Setup Time Chip Programming Time Chip Enable Hold Time Chip Erase Time 1. Toggle and Data Polling only.
Units
ns ns ns ns ns ns ns ns s Sec s s Sec ns Sec
tGHWL
tVCE tOEH 1 tWHWH3
10
Parameter
Write Cycle Time Write Enable Setup Time Chip Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Enable Pulse Width High Duration of Byte Programming Sector Erase Time Read Recovery Time Chip Programming Time Chip Erase Time
Units
ns ns ns ns ns ns ns ns s Sec ns Sec Sec
tGHEL
tWHWH3 5
120
tRC
Addresses Addresses Stable
tACC
FCE
tDF
OE
tOE
FWE
tCE
Outputs High Z
t OH
Output Valid High Z
5.0V tCE
Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
FCE tGHWL OE tWP FWE tCE Data tWPH tDH AAH tDS VCC 55H 80H AAH 55H 10H/30H
tVCE
Notes: 1. SA is the sector address for sector erase.
AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory
tCH
FCE
tDF tOE
OE
tOEH
FWE
tCE tOH *
DQ7 DQ7 DQ7= Valid Data High Z
t WHWH1 or 2
DQ0-DQ6 DQ0DQ6=Invalid
DQ0DQ6 Valid Data
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
5.0V
Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
"P3" 1.08" SQ PGA Type Package Standard (without shoulders) "P7" 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66)
Pin 1
.100 TYP
1.000 TYP
.145 MIN
.100 TYP
Pin 9 Pin 10
Detail A
.050 TYP
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
ACTSF2816N26P3Q ACTSF2816N37P3Q ACTSF2816N39P3Q ACTSF2816N26P7Q ACTSF2816N37P7Q ACTSF2816N39P7Q ACTSF2816N26F18Q ACTSF2816N37F18Q ACTSF2816N39F18Q
Note: (S) = Speed for SRAM, (F) = Speed for FLASH
Speed
25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns
Package
1.08"sq PGA-Type 1.08"sq PGA-Type 1.08"sq PGA-Type 1.08"sq PGA-Type 1.08"sq PGA-Type 1.08"sq PGA-Type .94"sq CQFP .94"sq CQFP .94"sq CQFP
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11
SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
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